1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 59 "Debug level"); 60 u_int sdhci_quirk_clear = 0; 61 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 62 0, "Mask of quirks to clear"); 63 u_int sdhci_quirk_set = 0; 64 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 65 "Mask of quirks to set"); 66 67 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 68 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 69 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 70 #define RD_MULTI_4(slot, off, ptr, count) \ 71 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 72 73 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 74 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 75 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 76 #define WR_MULTI_4(slot, off, ptr, count) \ 77 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 78 79 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 80 static void sdhci_start(struct sdhci_slot *slot); 81 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 82 83 static void sdhci_card_poll(void *); 84 static void sdhci_card_task(void *, int); 85 86 /* helper routines */ 87 static void sdhci_dumpregs(struct sdhci_slot *slot); 88 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 89 __printflike(2, 3); 90 91 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93 #define SDHCI_LOCK_INIT(_slot) \ 94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98 99 #define SDHCI_DEFAULT_MAX_FREQ 50 100 101 #define SDHCI_200_MAX_DIVIDER 256 102 #define SDHCI_300_MAX_DIVIDER 2046 103 104 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 105 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 106 107 /* 108 * Broadcom BCM577xx Controller Constants 109 */ 110 /* Maximum divider supported by the default clock source. */ 111 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 112 /* Alternative clock's base frequency. */ 113 #define BCM577XX_ALT_CLOCK_BASE 63000000 114 115 #define BCM577XX_HOST_CONTROL 0x198 116 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 117 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 118 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 119 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 120 121 static void 122 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 123 { 124 125 if (error != 0) { 126 printf("getaddr: error %d\n", error); 127 return; 128 } 129 *(bus_addr_t *)arg = segs[0].ds_addr; 130 } 131 132 static int 133 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 134 { 135 va_list ap; 136 int retval; 137 138 retval = printf("%s-slot%d: ", 139 device_get_nameunit(slot->bus), slot->num); 140 141 va_start(ap, fmt); 142 retval += vprintf(fmt, ap); 143 va_end(ap); 144 return (retval); 145 } 146 147 static void 148 sdhci_dumpregs(struct sdhci_slot *slot) 149 { 150 151 slot_printf(slot, 152 "============== REGISTER DUMP ==============\n"); 153 154 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 155 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 156 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 157 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 158 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 159 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 160 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 161 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 162 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 163 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 164 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 165 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 166 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 167 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 168 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 169 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 170 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 171 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 172 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 173 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 174 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 175 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 176 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 177 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 178 179 slot_printf(slot, 180 "===========================================\n"); 181 } 182 183 static void 184 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 185 { 186 int timeout; 187 uint32_t clock; 188 189 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 190 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 191 return; 192 } 193 194 /* Some controllers need this kick or reset won't work. */ 195 if ((mask & SDHCI_RESET_ALL) == 0 && 196 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 197 /* This is to force an update */ 198 clock = slot->clock; 199 slot->clock = 0; 200 sdhci_set_clock(slot, clock); 201 } 202 203 if (mask & SDHCI_RESET_ALL) { 204 slot->clock = 0; 205 slot->power = 0; 206 } 207 208 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 209 210 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 211 /* 212 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 213 * specification. The reset bit has internal propagation delay, 214 * so a fast read after write returns 0 even if reset process is 215 * in progress. The workaround is to poll for 1 before polling 216 * for 0. In the worst case, if we miss seeing it asserted the 217 * time we spent waiting is enough to ensure the reset finishes. 218 */ 219 timeout = 10000; 220 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 221 if (timeout <= 0) 222 break; 223 timeout--; 224 DELAY(1); 225 } 226 } 227 228 /* Wait max 100 ms */ 229 timeout = 10000; 230 /* Controller clears the bits when it's done */ 231 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 232 if (timeout <= 0) { 233 slot_printf(slot, "Reset 0x%x never completed.\n", 234 mask); 235 sdhci_dumpregs(slot); 236 return; 237 } 238 timeout--; 239 DELAY(10); 240 } 241 } 242 243 static void 244 sdhci_init(struct sdhci_slot *slot) 245 { 246 247 sdhci_reset(slot, SDHCI_RESET_ALL); 248 249 /* Enable interrupts. */ 250 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 251 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 252 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 253 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 254 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 255 SDHCI_INT_ACMD12ERR; 256 257 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 258 !(slot->opt & SDHCI_NON_REMOVABLE)) { 259 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 260 } 261 262 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 263 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 264 } 265 266 static void 267 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 268 { 269 uint32_t clk_base; 270 uint32_t clk_sel; 271 uint32_t res; 272 uint16_t clk; 273 uint16_t div; 274 int timeout; 275 276 if (clock == slot->clock) 277 return; 278 slot->clock = clock; 279 280 /* Turn off the clock. */ 281 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 282 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 283 /* If no clock requested - leave it so. */ 284 if (clock == 0) 285 return; 286 287 /* Determine the clock base frequency */ 288 clk_base = slot->max_clk; 289 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 290 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 291 BCM577XX_CTRL_CLKSEL_MASK; 292 293 /* 294 * Select clock source appropriate for the requested frequency. 295 */ 296 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 297 clk_base = BCM577XX_ALT_CLOCK_BASE; 298 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 299 BCM577XX_CTRL_CLKSEL_SHIFT); 300 } else { 301 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 302 BCM577XX_CTRL_CLKSEL_SHIFT); 303 } 304 305 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 306 } 307 308 /* Recalculate timeout clock frequency based on the new sd clock. */ 309 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 310 slot->timeout_clk = slot->clock / 1000; 311 312 if (slot->version < SDHCI_SPEC_300) { 313 /* Looking for highest freq <= clock. */ 314 res = clk_base; 315 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 316 if (res <= clock) 317 break; 318 res >>= 1; 319 } 320 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 321 div >>= 1; 322 } else { 323 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 324 if (clock >= clk_base) 325 div = 0; 326 else { 327 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 328 if ((clk_base / div) <= clock) 329 break; 330 } 331 } 332 div >>= 1; 333 } 334 335 if (bootverbose || sdhci_debug) 336 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 337 div, clock, clk_base); 338 339 /* Now we have got divider, set it. */ 340 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 341 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 342 << SDHCI_DIVIDER_HI_SHIFT; 343 344 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 345 /* Enable clock. */ 346 clk |= SDHCI_CLOCK_INT_EN; 347 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 348 /* Wait up to 10 ms until it stabilize. */ 349 timeout = 10; 350 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 351 & SDHCI_CLOCK_INT_STABLE)) { 352 if (timeout == 0) { 353 slot_printf(slot, 354 "Internal clock never stabilised.\n"); 355 sdhci_dumpregs(slot); 356 return; 357 } 358 timeout--; 359 DELAY(1000); 360 } 361 /* Pass clock signal to the bus. */ 362 clk |= SDHCI_CLOCK_CARD_EN; 363 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 364 } 365 366 static void 367 sdhci_set_power(struct sdhci_slot *slot, u_char power) 368 { 369 int i; 370 uint8_t pwr; 371 372 if (slot->power == power) 373 return; 374 375 slot->power = power; 376 377 /* Turn off the power. */ 378 pwr = 0; 379 WR1(slot, SDHCI_POWER_CONTROL, pwr); 380 /* If power down requested - leave it so. */ 381 if (power == 0) 382 return; 383 /* Set voltage. */ 384 switch (1 << power) { 385 case MMC_OCR_LOW_VOLTAGE: 386 pwr |= SDHCI_POWER_180; 387 break; 388 case MMC_OCR_290_300: 389 case MMC_OCR_300_310: 390 pwr |= SDHCI_POWER_300; 391 break; 392 case MMC_OCR_320_330: 393 case MMC_OCR_330_340: 394 pwr |= SDHCI_POWER_330; 395 break; 396 } 397 WR1(slot, SDHCI_POWER_CONTROL, pwr); 398 /* 399 * Turn on VDD1 power. Note that at least some Intel controllers can 400 * fail to enable bus power on the first try after transiting from D3 401 * to D0, so we give them up to 2 ms. 402 */ 403 pwr |= SDHCI_POWER_ON; 404 for (i = 0; i < 20; i++) { 405 WR1(slot, SDHCI_POWER_CONTROL, pwr); 406 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 407 break; 408 DELAY(100); 409 } 410 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 411 slot_printf(slot, "Bus power failed to enable"); 412 413 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 414 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 415 DELAY(10); 416 WR1(slot, SDHCI_POWER_CONTROL, pwr); 417 DELAY(300); 418 } 419 } 420 421 static void 422 sdhci_read_block_pio(struct sdhci_slot *slot) 423 { 424 uint32_t data; 425 char *buffer; 426 size_t left; 427 428 buffer = slot->curcmd->data->data; 429 buffer += slot->offset; 430 /* Transfer one block at a time. */ 431 left = min(512, slot->curcmd->data->len - slot->offset); 432 slot->offset += left; 433 434 /* If we are too fast, broken controllers return zeroes. */ 435 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 436 DELAY(10); 437 /* Handle unaligned and aligned buffer cases. */ 438 if ((intptr_t)buffer & 3) { 439 while (left > 3) { 440 data = RD4(slot, SDHCI_BUFFER); 441 buffer[0] = data; 442 buffer[1] = (data >> 8); 443 buffer[2] = (data >> 16); 444 buffer[3] = (data >> 24); 445 buffer += 4; 446 left -= 4; 447 } 448 } else { 449 RD_MULTI_4(slot, SDHCI_BUFFER, 450 (uint32_t *)buffer, left >> 2); 451 left &= 3; 452 } 453 /* Handle uneven size case. */ 454 if (left > 0) { 455 data = RD4(slot, SDHCI_BUFFER); 456 while (left > 0) { 457 *(buffer++) = data; 458 data >>= 8; 459 left--; 460 } 461 } 462 } 463 464 static void 465 sdhci_write_block_pio(struct sdhci_slot *slot) 466 { 467 uint32_t data = 0; 468 char *buffer; 469 size_t left; 470 471 buffer = slot->curcmd->data->data; 472 buffer += slot->offset; 473 /* Transfer one block at a time. */ 474 left = min(512, slot->curcmd->data->len - slot->offset); 475 slot->offset += left; 476 477 /* Handle unaligned and aligned buffer cases. */ 478 if ((intptr_t)buffer & 3) { 479 while (left > 3) { 480 data = buffer[0] + 481 (buffer[1] << 8) + 482 (buffer[2] << 16) + 483 (buffer[3] << 24); 484 left -= 4; 485 buffer += 4; 486 WR4(slot, SDHCI_BUFFER, data); 487 } 488 } else { 489 WR_MULTI_4(slot, SDHCI_BUFFER, 490 (uint32_t *)buffer, left >> 2); 491 left &= 3; 492 } 493 /* Handle uneven size case. */ 494 if (left > 0) { 495 while (left > 0) { 496 data <<= 8; 497 data += *(buffer++); 498 left--; 499 } 500 WR4(slot, SDHCI_BUFFER, data); 501 } 502 } 503 504 static void 505 sdhci_transfer_pio(struct sdhci_slot *slot) 506 { 507 508 /* Read as many blocks as possible. */ 509 if (slot->curcmd->data->flags & MMC_DATA_READ) { 510 while (RD4(slot, SDHCI_PRESENT_STATE) & 511 SDHCI_DATA_AVAILABLE) { 512 sdhci_read_block_pio(slot); 513 if (slot->offset >= slot->curcmd->data->len) 514 break; 515 } 516 } else { 517 while (RD4(slot, SDHCI_PRESENT_STATE) & 518 SDHCI_SPACE_AVAILABLE) { 519 sdhci_write_block_pio(slot); 520 if (slot->offset >= slot->curcmd->data->len) 521 break; 522 } 523 } 524 } 525 526 static void 527 sdhci_card_task(void *arg, int pending __unused) 528 { 529 struct sdhci_slot *slot = arg; 530 device_t d; 531 532 SDHCI_LOCK(slot); 533 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 534 if (slot->dev == NULL) { 535 /* If card is present - attach mmc bus. */ 536 if (bootverbose || sdhci_debug) 537 slot_printf(slot, "Card inserted\n"); 538 slot->dev = device_add_child(slot->bus, "mmc", -1); 539 device_set_ivars(slot->dev, slot); 540 SDHCI_UNLOCK(slot); 541 device_probe_and_attach(slot->dev); 542 } else 543 SDHCI_UNLOCK(slot); 544 } else { 545 if (slot->dev != NULL) { 546 /* If no card present - detach mmc bus. */ 547 if (bootverbose || sdhci_debug) 548 slot_printf(slot, "Card removed\n"); 549 d = slot->dev; 550 slot->dev = NULL; 551 SDHCI_UNLOCK(slot); 552 device_delete_child(slot->bus, d); 553 } else 554 SDHCI_UNLOCK(slot); 555 } 556 } 557 558 static void 559 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 560 { 561 bool was_present; 562 563 /* 564 * If there was no card and now there is one, schedule the task to 565 * create the child device after a short delay. The delay is to 566 * debounce the card insert (sometimes the card detect pin stabilizes 567 * before the other pins have made good contact). 568 * 569 * If there was a card present and now it's gone, immediately schedule 570 * the task to delete the child device. No debouncing -- gone is gone, 571 * because once power is removed, a full card re-init is needed, and 572 * that happens by deleting and recreating the child device. 573 */ 574 was_present = slot->dev != NULL; 575 if (!was_present && is_present) { 576 taskqueue_enqueue_timeout(taskqueue_swi_giant, 577 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 578 } else if (was_present && !is_present) { 579 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 580 } 581 } 582 583 void 584 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 585 { 586 587 SDHCI_LOCK(slot); 588 sdhci_handle_card_present_locked(slot, is_present); 589 SDHCI_UNLOCK(slot); 590 } 591 592 static void 593 sdhci_card_poll(void *arg) 594 { 595 struct sdhci_slot *slot = arg; 596 597 sdhci_handle_card_present(slot, 598 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 599 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 600 sdhci_card_poll, slot); 601 } 602 603 int 604 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 605 { 606 uint32_t caps, caps2, freq, host_caps; 607 int err; 608 609 SDHCI_LOCK_INIT(slot); 610 slot->num = num; 611 slot->bus = dev; 612 613 /* Allocate DMA tag. */ 614 err = bus_dma_tag_create(bus_get_dma_tag(dev), 615 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 616 BUS_SPACE_MAXADDR, NULL, NULL, 617 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 618 BUS_DMA_ALLOCNOW, NULL, NULL, 619 &slot->dmatag); 620 if (err != 0) { 621 device_printf(dev, "Can't create DMA tag\n"); 622 SDHCI_LOCK_DESTROY(slot); 623 return (err); 624 } 625 /* Allocate DMA memory. */ 626 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 627 BUS_DMA_NOWAIT, &slot->dmamap); 628 if (err != 0) { 629 device_printf(dev, "Can't alloc DMA memory\n"); 630 SDHCI_LOCK_DESTROY(slot); 631 return (err); 632 } 633 /* Map the memory. */ 634 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 635 (void *)slot->dmamem, DMA_BLOCK_SIZE, 636 sdhci_getaddr, &slot->paddr, 0); 637 if (err != 0 || slot->paddr == 0) { 638 device_printf(dev, "Can't load DMA memory\n"); 639 SDHCI_LOCK_DESTROY(slot); 640 if (err) 641 return (err); 642 else 643 return (EFAULT); 644 } 645 646 /* Initialize slot. */ 647 sdhci_init(slot); 648 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 649 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 650 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 651 caps = slot->caps; 652 caps2 = slot->caps2; 653 } else { 654 caps = RD4(slot, SDHCI_CAPABILITIES); 655 if (slot->version >= SDHCI_SPEC_300) 656 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 657 else 658 caps2 = 0; 659 } 660 /* Calculate base clock frequency. */ 661 if (slot->version >= SDHCI_SPEC_300) 662 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 663 SDHCI_CLOCK_BASE_SHIFT; 664 else 665 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 666 SDHCI_CLOCK_BASE_SHIFT; 667 if (freq != 0) 668 slot->max_clk = freq * 1000000; 669 /* 670 * If the frequency wasn't in the capabilities and the hardware driver 671 * hasn't already set max_clk we're probably not going to work right 672 * with an assumption, so complain about it. 673 */ 674 if (slot->max_clk == 0) { 675 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 676 device_printf(dev, "Hardware doesn't specify base clock " 677 "frequency, using %dMHz as default.\n", 678 SDHCI_DEFAULT_MAX_FREQ); 679 } 680 /* Calculate/set timeout clock frequency. */ 681 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 682 slot->timeout_clk = slot->max_clk / 1000; 683 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 684 slot->timeout_clk = 1000; 685 } else { 686 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 687 SDHCI_TIMEOUT_CLK_SHIFT; 688 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 689 slot->timeout_clk *= 1000; 690 } 691 /* 692 * If the frequency wasn't in the capabilities and the hardware driver 693 * hasn't already set timeout_clk we'll probably work okay using the 694 * max timeout, but still mention it. 695 */ 696 if (slot->timeout_clk == 0) { 697 device_printf(dev, "Hardware doesn't specify timeout clock " 698 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 699 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 700 } 701 702 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 703 slot->host.f_max = slot->max_clk; 704 slot->host.host_ocr = 0; 705 if (caps & SDHCI_CAN_VDD_330) 706 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 707 if (caps & SDHCI_CAN_VDD_300) 708 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 709 if (caps & SDHCI_CAN_VDD_180) 710 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 711 if (slot->host.host_ocr == 0) { 712 device_printf(dev, "Hardware doesn't report any " 713 "support voltages.\n"); 714 } 715 host_caps = MMC_CAP_4_BIT_DATA; 716 if (caps & SDHCI_CAN_DO_8BITBUS) 717 host_caps |= MMC_CAP_8_BIT_DATA; 718 if (caps & SDHCI_CAN_DO_HISPD) 719 host_caps |= MMC_CAP_HSPEED; 720 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 721 host_caps |= MMC_CAP_BOOT_NOACC; 722 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 723 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 724 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 725 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 726 if (caps2 & SDHCI_CAN_SDR104) { 727 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 728 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 729 host_caps |= MMC_CAP_MMC_HS200; 730 } else if (caps2 & SDHCI_CAN_SDR50) 731 host_caps |= MMC_CAP_UHS_SDR50; 732 if (caps2 & SDHCI_CAN_DDR50 && 733 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 734 host_caps |= MMC_CAP_UHS_DDR50; 735 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 736 host_caps |= MMC_CAP_MMC_DDR52; 737 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 738 caps2 & SDHCI_CAN_MMC_HS400) 739 host_caps |= MMC_CAP_MMC_HS400; 740 host_caps |= MMC_CAP_SIGNALING_330; 741 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 742 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | 743 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 744 MMC_CAP_MMC_HS400_180)) 745 host_caps |= MMC_CAP_SIGNALING_180; 746 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 747 host_caps |= MMC_CAP_DRIVER_TYPE_A; 748 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 749 host_caps |= MMC_CAP_DRIVER_TYPE_C; 750 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 751 host_caps |= MMC_CAP_DRIVER_TYPE_D; 752 slot->host.caps = host_caps; 753 754 /* Decide if we have usable DMA. */ 755 if (caps & SDHCI_CAN_DO_DMA) 756 slot->opt |= SDHCI_HAVE_DMA; 757 758 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 759 slot->opt &= ~SDHCI_HAVE_DMA; 760 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 761 slot->opt |= SDHCI_HAVE_DMA; 762 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 763 slot->opt |= SDHCI_NON_REMOVABLE; 764 765 /* 766 * Use platform-provided transfer backend 767 * with PIO as a fallback mechanism 768 */ 769 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 770 slot->opt &= ~SDHCI_HAVE_DMA; 771 772 if (bootverbose || sdhci_debug) { 773 slot_printf(slot, 774 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s\n", 775 slot->max_clk / 1000000, 776 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 777 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 778 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 779 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 780 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 781 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 782 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 783 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 784 (caps2 & SDHCI_CAN_DRIVE_TYPE_A) ? "A" : "", 785 (caps2 & SDHCI_CAN_DRIVE_TYPE_C) ? "C" : "", 786 (caps2 & SDHCI_CAN_DRIVE_TYPE_D) ? "D" : "", 787 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 788 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 789 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 790 slot_printf(slot, "eMMC:%s%s%s%s\n", 791 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 792 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 793 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 794 ((host_caps & 795 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 796 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 797 " HS400ES" : ""); 798 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 799 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 800 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 801 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 802 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 803 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 804 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 805 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 806 sdhci_dumpregs(slot); 807 } 808 809 slot->timeout = 10; 810 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 812 "timeout", CTLFLAG_RW, &slot->timeout, 0, 813 "Maximum timeout for SDHCI transfers (in secs)"); 814 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 815 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 816 sdhci_card_task, slot); 817 callout_init(&slot->card_poll_callout, 1); 818 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 819 820 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 821 !(slot->opt & SDHCI_NON_REMOVABLE)) { 822 callout_reset(&slot->card_poll_callout, 823 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 824 } 825 826 return (0); 827 } 828 829 void 830 sdhci_start_slot(struct sdhci_slot *slot) 831 { 832 833 sdhci_card_task(slot, 0); 834 } 835 836 int 837 sdhci_cleanup_slot(struct sdhci_slot *slot) 838 { 839 device_t d; 840 841 callout_drain(&slot->timeout_callout); 842 callout_drain(&slot->card_poll_callout); 843 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 844 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 845 846 SDHCI_LOCK(slot); 847 d = slot->dev; 848 slot->dev = NULL; 849 SDHCI_UNLOCK(slot); 850 if (d != NULL) 851 device_delete_child(slot->bus, d); 852 853 SDHCI_LOCK(slot); 854 sdhci_reset(slot, SDHCI_RESET_ALL); 855 SDHCI_UNLOCK(slot); 856 bus_dmamap_unload(slot->dmatag, slot->dmamap); 857 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 858 bus_dma_tag_destroy(slot->dmatag); 859 860 SDHCI_LOCK_DESTROY(slot); 861 862 return (0); 863 } 864 865 int 866 sdhci_generic_suspend(struct sdhci_slot *slot) 867 { 868 869 sdhci_reset(slot, SDHCI_RESET_ALL); 870 871 return (0); 872 } 873 874 int 875 sdhci_generic_resume(struct sdhci_slot *slot) 876 { 877 878 sdhci_init(slot); 879 880 return (0); 881 } 882 883 uint32_t 884 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 885 { 886 887 if (slot->version >= SDHCI_SPEC_300) 888 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 889 else 890 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 891 } 892 893 bool 894 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 895 { 896 897 if (slot->opt & SDHCI_NON_REMOVABLE) 898 return true; 899 900 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 901 } 902 903 void 904 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 905 { 906 struct mmc_ios *ios; 907 uint16_t hostctrl2; 908 909 if (slot->version < SDHCI_SPEC_300) 910 return; 911 912 ios = &slot->host.ios; 913 sdhci_set_clock(slot, 0); 914 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 915 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 916 if (ios->timing == bus_timing_mmc_hs400 || 917 ios->timing == bus_timing_mmc_hs400es) 918 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 919 else if (ios->clock > SD_SDR50_MAX) 920 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 921 else if (ios->clock > SD_SDR25_MAX) 922 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 923 else if (ios->clock > SD_SDR12_MAX) { 924 if (ios->timing == bus_timing_uhs_ddr50 || 925 ios->timing == bus_timing_mmc_ddr52) 926 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 927 else 928 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 929 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 930 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 931 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 932 sdhci_set_clock(slot, ios->clock); 933 } 934 935 int 936 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 937 { 938 struct sdhci_slot *slot = device_get_ivars(reqdev); 939 struct mmc_ios *ios = &slot->host.ios; 940 941 SDHCI_LOCK(slot); 942 /* Do full reset on bus power down to clear from any state. */ 943 if (ios->power_mode == power_off) { 944 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 945 sdhci_init(slot); 946 } 947 /* Configure the bus. */ 948 sdhci_set_clock(slot, ios->clock); 949 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 950 if (ios->bus_width == bus_width_8) { 951 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 952 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 953 } else if (ios->bus_width == bus_width_4) { 954 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 955 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 956 } else if (ios->bus_width == bus_width_1) { 957 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 958 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 959 } else { 960 panic("Invalid bus width: %d", ios->bus_width); 961 } 962 if (ios->clock > SD_SDR12_MAX && 963 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 964 slot->hostctrl |= SDHCI_CTRL_HISPD; 965 else 966 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 967 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 968 SDHCI_SET_UHS_TIMING(brdev, slot); 969 /* Some controllers like reset after bus changes. */ 970 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 971 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 972 973 SDHCI_UNLOCK(slot); 974 return (0); 975 } 976 977 int 978 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 979 { 980 struct sdhci_slot *slot = device_get_ivars(reqdev); 981 enum mmc_vccq vccq; 982 int err; 983 uint16_t hostctrl2; 984 985 if (slot->version < SDHCI_SPEC_300) 986 return (0); 987 988 err = 0; 989 vccq = slot->host.ios.vccq; 990 SDHCI_LOCK(slot); 991 sdhci_set_clock(slot, 0); 992 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 993 switch (vccq) { 994 case vccq_330: 995 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 996 goto done; 997 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 998 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 999 DELAY(5000); 1000 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1001 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1002 goto done; 1003 err = EAGAIN; 1004 break; 1005 case vccq_180: 1006 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1007 err = EINVAL; 1008 goto done; 1009 } 1010 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1011 goto done; 1012 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1013 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1014 DELAY(5000); 1015 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1016 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1017 goto done; 1018 err = EAGAIN; 1019 break; 1020 default: 1021 slot_printf(slot, 1022 "Attempt to set unsupported signaling voltage\n"); 1023 err = EINVAL; 1024 break; 1025 } 1026 done: 1027 sdhci_set_clock(slot, slot->host.ios.clock); 1028 SDHCI_UNLOCK(slot); 1029 return (err); 1030 } 1031 1032 static void 1033 sdhci_req_done(struct sdhci_slot *slot) 1034 { 1035 struct mmc_request *req; 1036 1037 if (slot->req != NULL && slot->curcmd != NULL) { 1038 callout_stop(&slot->timeout_callout); 1039 req = slot->req; 1040 slot->req = NULL; 1041 slot->curcmd = NULL; 1042 req->done(req); 1043 } 1044 } 1045 1046 static void 1047 sdhci_timeout(void *arg) 1048 { 1049 struct sdhci_slot *slot = arg; 1050 1051 if (slot->curcmd != NULL) { 1052 slot_printf(slot, " Controller timeout\n"); 1053 sdhci_dumpregs(slot); 1054 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1055 slot->curcmd->error = MMC_ERR_TIMEOUT; 1056 sdhci_req_done(slot); 1057 } else { 1058 slot_printf(slot, " Spurious timeout - no active command\n"); 1059 } 1060 } 1061 1062 static void 1063 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1064 { 1065 uint16_t mode; 1066 1067 if (data == NULL) 1068 return; 1069 1070 mode = SDHCI_TRNS_BLK_CNT_EN; 1071 if (data->len > 512) 1072 mode |= SDHCI_TRNS_MULTI; 1073 if (data->flags & MMC_DATA_READ) 1074 mode |= SDHCI_TRNS_READ; 1075 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1076 mode |= SDHCI_TRNS_ACMD12; 1077 if (slot->flags & SDHCI_USE_DMA) 1078 mode |= SDHCI_TRNS_DMA; 1079 1080 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1081 } 1082 1083 static void 1084 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1085 { 1086 int flags, timeout; 1087 uint32_t mask; 1088 1089 slot->curcmd = cmd; 1090 slot->cmd_done = 0; 1091 1092 cmd->error = MMC_ERR_NONE; 1093 1094 /* This flags combination is not supported by controller. */ 1095 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1096 slot_printf(slot, "Unsupported response type!\n"); 1097 cmd->error = MMC_ERR_FAILED; 1098 sdhci_req_done(slot); 1099 return; 1100 } 1101 1102 /* 1103 * Do not issue command if there is no card, clock or power. 1104 * Controller will not detect timeout without clock active. 1105 */ 1106 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1107 slot->power == 0 || 1108 slot->clock == 0) { 1109 cmd->error = MMC_ERR_FAILED; 1110 sdhci_req_done(slot); 1111 return; 1112 } 1113 /* Always wait for free CMD bus. */ 1114 mask = SDHCI_CMD_INHIBIT; 1115 /* Wait for free DAT if we have data or busy signal. */ 1116 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 1117 mask |= SDHCI_DAT_INHIBIT; 1118 /* We shouldn't wait for DAT for stop commands. */ 1119 if (cmd == slot->req->stop) 1120 mask &= ~SDHCI_DAT_INHIBIT; 1121 /* 1122 * Wait for bus no more then 250 ms. Typically there will be no wait 1123 * here at all, but when writing a crash dump we may be bypassing the 1124 * host platform's interrupt handler, and in some cases that handler 1125 * may be working around hardware quirks such as not respecting r1b 1126 * busy indications. In those cases, this wait-loop serves the purpose 1127 * of waiting for the prior command and data transfers to be done, and 1128 * SD cards are allowed to take up to 250ms for write and erase ops. 1129 * (It's usually more like 20-30ms in the real world.) 1130 */ 1131 timeout = 250; 1132 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1133 if (timeout == 0) { 1134 slot_printf(slot, "Controller never released " 1135 "inhibit bit(s).\n"); 1136 sdhci_dumpregs(slot); 1137 cmd->error = MMC_ERR_FAILED; 1138 sdhci_req_done(slot); 1139 return; 1140 } 1141 timeout--; 1142 DELAY(1000); 1143 } 1144 1145 /* Prepare command flags. */ 1146 if (!(cmd->flags & MMC_RSP_PRESENT)) 1147 flags = SDHCI_CMD_RESP_NONE; 1148 else if (cmd->flags & MMC_RSP_136) 1149 flags = SDHCI_CMD_RESP_LONG; 1150 else if (cmd->flags & MMC_RSP_BUSY) 1151 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1152 else 1153 flags = SDHCI_CMD_RESP_SHORT; 1154 if (cmd->flags & MMC_RSP_CRC) 1155 flags |= SDHCI_CMD_CRC; 1156 if (cmd->flags & MMC_RSP_OPCODE) 1157 flags |= SDHCI_CMD_INDEX; 1158 if (cmd->data) 1159 flags |= SDHCI_CMD_DATA; 1160 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1161 flags |= SDHCI_CMD_TYPE_ABORT; 1162 /* Prepare data. */ 1163 sdhci_start_data(slot, cmd->data); 1164 /* 1165 * Interrupt aggregation: To reduce total number of interrupts 1166 * group response interrupt with data interrupt when possible. 1167 * If there going to be data interrupt, mask response one. 1168 */ 1169 if (slot->data_done == 0) { 1170 WR4(slot, SDHCI_SIGNAL_ENABLE, 1171 slot->intmask &= ~SDHCI_INT_RESPONSE); 1172 } 1173 /* Set command argument. */ 1174 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1175 /* Set data transfer mode. */ 1176 sdhci_set_transfer_mode(slot, cmd->data); 1177 /* Start command. */ 1178 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1179 /* Start timeout callout. */ 1180 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1181 sdhci_timeout, slot); 1182 } 1183 1184 static void 1185 sdhci_finish_command(struct sdhci_slot *slot) 1186 { 1187 int i; 1188 uint32_t val; 1189 uint8_t extra; 1190 1191 slot->cmd_done = 1; 1192 /* 1193 * Interrupt aggregation: Restore command interrupt. 1194 * Main restore point for the case when command interrupt 1195 * happened first. 1196 */ 1197 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1198 /* In case of error - reset host and return. */ 1199 if (slot->curcmd->error) { 1200 sdhci_reset(slot, SDHCI_RESET_CMD); 1201 sdhci_reset(slot, SDHCI_RESET_DATA); 1202 sdhci_start(slot); 1203 return; 1204 } 1205 /* If command has response - fetch it. */ 1206 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1207 if (slot->curcmd->flags & MMC_RSP_136) { 1208 /* CRC is stripped so we need one byte shift. */ 1209 extra = 0; 1210 for (i = 0; i < 4; i++) { 1211 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1212 if (slot->quirks & 1213 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1214 slot->curcmd->resp[3 - i] = val; 1215 else { 1216 slot->curcmd->resp[3 - i] = 1217 (val << 8) | extra; 1218 extra = val >> 24; 1219 } 1220 } 1221 } else 1222 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1223 } 1224 /* If data ready - finish. */ 1225 if (slot->data_done) 1226 sdhci_start(slot); 1227 } 1228 1229 static void 1230 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1231 { 1232 uint32_t target_timeout, current_timeout; 1233 uint8_t div; 1234 1235 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1236 slot->data_done = 1; 1237 return; 1238 } 1239 1240 slot->data_done = 0; 1241 1242 /* Calculate and set data timeout.*/ 1243 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1244 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1245 div = 0xE; 1246 } else { 1247 target_timeout = 1000000; 1248 div = 0; 1249 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1250 while (current_timeout < target_timeout && div < 0xE) { 1251 ++div; 1252 current_timeout <<= 1; 1253 } 1254 /* Compensate for an off-by-one error in the CaFe chip.*/ 1255 if (div < 0xE && 1256 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1257 ++div; 1258 } 1259 } 1260 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1261 1262 if (data == NULL) 1263 return; 1264 1265 /* Use DMA if possible. */ 1266 if ((slot->opt & SDHCI_HAVE_DMA)) 1267 slot->flags |= SDHCI_USE_DMA; 1268 /* If data is small, broken DMA may return zeroes instead of data, */ 1269 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1270 (data->len <= 512)) 1271 slot->flags &= ~SDHCI_USE_DMA; 1272 /* Some controllers require even block sizes. */ 1273 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1274 ((data->len) & 0x3)) 1275 slot->flags &= ~SDHCI_USE_DMA; 1276 /* Load DMA buffer. */ 1277 if (slot->flags & SDHCI_USE_DMA) { 1278 if (data->flags & MMC_DATA_READ) 1279 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1280 BUS_DMASYNC_PREREAD); 1281 else { 1282 memcpy(slot->dmamem, data->data, 1283 (data->len < DMA_BLOCK_SIZE) ? 1284 data->len : DMA_BLOCK_SIZE); 1285 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1286 BUS_DMASYNC_PREWRITE); 1287 } 1288 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1289 /* Interrupt aggregation: Mask border interrupt 1290 * for the last page and unmask else. */ 1291 if (data->len == DMA_BLOCK_SIZE) 1292 slot->intmask &= ~SDHCI_INT_DMA_END; 1293 else 1294 slot->intmask |= SDHCI_INT_DMA_END; 1295 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1296 } 1297 /* Current data offset for both PIO and DMA. */ 1298 slot->offset = 0; 1299 /* Set block size and request IRQ on 4K border. */ 1300 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1301 (data->len < 512) ? data->len : 512)); 1302 /* Set block count. */ 1303 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1304 } 1305 1306 void 1307 sdhci_finish_data(struct sdhci_slot *slot) 1308 { 1309 struct mmc_data *data = slot->curcmd->data; 1310 size_t left; 1311 1312 /* Interrupt aggregation: Restore command interrupt. 1313 * Auxiliary restore point for the case when data interrupt 1314 * happened first. */ 1315 if (!slot->cmd_done) { 1316 WR4(slot, SDHCI_SIGNAL_ENABLE, 1317 slot->intmask |= SDHCI_INT_RESPONSE); 1318 } 1319 /* Unload rest of data from DMA buffer. */ 1320 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1321 slot->curcmd->data != NULL) { 1322 if (data->flags & MMC_DATA_READ) { 1323 left = data->len - slot->offset; 1324 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1325 BUS_DMASYNC_POSTREAD); 1326 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1327 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1328 } else 1329 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1330 BUS_DMASYNC_POSTWRITE); 1331 } 1332 slot->data_done = 1; 1333 /* If there was error - reset the host. */ 1334 if (slot->curcmd->error) { 1335 sdhci_reset(slot, SDHCI_RESET_CMD); 1336 sdhci_reset(slot, SDHCI_RESET_DATA); 1337 sdhci_start(slot); 1338 return; 1339 } 1340 /* If we already have command response - finish. */ 1341 if (slot->cmd_done) 1342 sdhci_start(slot); 1343 } 1344 1345 static void 1346 sdhci_start(struct sdhci_slot *slot) 1347 { 1348 struct mmc_request *req; 1349 1350 req = slot->req; 1351 if (req == NULL) 1352 return; 1353 1354 if (!(slot->flags & CMD_STARTED)) { 1355 slot->flags |= CMD_STARTED; 1356 sdhci_start_command(slot, req->cmd); 1357 return; 1358 } 1359 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1360 !(slot->flags & STOP_STARTED) && req->stop) { 1361 slot->flags |= STOP_STARTED; 1362 sdhci_start_command(slot, req->stop); 1363 return; 1364 } 1365 if (sdhci_debug > 1) 1366 slot_printf(slot, "result: %d\n", req->cmd->error); 1367 if (!req->cmd->error && 1368 ((slot->curcmd == req->stop && 1369 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1370 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1371 sdhci_reset(slot, SDHCI_RESET_CMD); 1372 sdhci_reset(slot, SDHCI_RESET_DATA); 1373 } 1374 1375 sdhci_req_done(slot); 1376 } 1377 1378 int 1379 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1380 struct mmc_request *req) 1381 { 1382 struct sdhci_slot *slot = device_get_ivars(reqdev); 1383 1384 SDHCI_LOCK(slot); 1385 if (slot->req != NULL) { 1386 SDHCI_UNLOCK(slot); 1387 return (EBUSY); 1388 } 1389 if (sdhci_debug > 1) { 1390 slot_printf(slot, 1391 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1392 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1393 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1394 (req->cmd->data)?req->cmd->data->flags:0); 1395 } 1396 slot->req = req; 1397 slot->flags = 0; 1398 sdhci_start(slot); 1399 SDHCI_UNLOCK(slot); 1400 if (dumping) { 1401 while (slot->req != NULL) { 1402 sdhci_generic_intr(slot); 1403 DELAY(10); 1404 } 1405 } 1406 return (0); 1407 } 1408 1409 int 1410 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1411 { 1412 struct sdhci_slot *slot = device_get_ivars(reqdev); 1413 uint32_t val; 1414 1415 SDHCI_LOCK(slot); 1416 val = RD4(slot, SDHCI_PRESENT_STATE); 1417 SDHCI_UNLOCK(slot); 1418 return (!(val & SDHCI_WRITE_PROTECT)); 1419 } 1420 1421 int 1422 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1423 { 1424 struct sdhci_slot *slot = device_get_ivars(reqdev); 1425 int err = 0; 1426 1427 SDHCI_LOCK(slot); 1428 while (slot->bus_busy) 1429 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1430 slot->bus_busy++; 1431 /* Activate led. */ 1432 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1433 SDHCI_UNLOCK(slot); 1434 return (err); 1435 } 1436 1437 int 1438 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1439 { 1440 struct sdhci_slot *slot = device_get_ivars(reqdev); 1441 1442 SDHCI_LOCK(slot); 1443 /* Deactivate led. */ 1444 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1445 slot->bus_busy--; 1446 SDHCI_UNLOCK(slot); 1447 wakeup(slot); 1448 return (0); 1449 } 1450 1451 static void 1452 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1453 { 1454 1455 if (!slot->curcmd) { 1456 slot_printf(slot, "Got command interrupt 0x%08x, but " 1457 "there is no active command.\n", intmask); 1458 sdhci_dumpregs(slot); 1459 return; 1460 } 1461 if (intmask & SDHCI_INT_TIMEOUT) 1462 slot->curcmd->error = MMC_ERR_TIMEOUT; 1463 else if (intmask & SDHCI_INT_CRC) 1464 slot->curcmd->error = MMC_ERR_BADCRC; 1465 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1466 slot->curcmd->error = MMC_ERR_FIFO; 1467 1468 sdhci_finish_command(slot); 1469 } 1470 1471 static void 1472 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1473 { 1474 struct mmc_data *data; 1475 size_t left; 1476 1477 if (!slot->curcmd) { 1478 slot_printf(slot, "Got data interrupt 0x%08x, but " 1479 "there is no active command.\n", intmask); 1480 sdhci_dumpregs(slot); 1481 return; 1482 } 1483 if (slot->curcmd->data == NULL && 1484 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1485 slot_printf(slot, "Got data interrupt 0x%08x, but " 1486 "there is no active data operation.\n", 1487 intmask); 1488 sdhci_dumpregs(slot); 1489 return; 1490 } 1491 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1492 slot->curcmd->error = MMC_ERR_TIMEOUT; 1493 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1494 slot->curcmd->error = MMC_ERR_BADCRC; 1495 if (slot->curcmd->data == NULL && 1496 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1497 SDHCI_INT_DMA_END))) { 1498 slot_printf(slot, "Got data interrupt 0x%08x, but " 1499 "there is busy-only command.\n", intmask); 1500 sdhci_dumpregs(slot); 1501 slot->curcmd->error = MMC_ERR_INVALID; 1502 } 1503 if (slot->curcmd->error) { 1504 /* No need to continue after any error. */ 1505 goto done; 1506 } 1507 1508 /* Handle PIO interrupt. */ 1509 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1510 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1511 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1512 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1513 &intmask); 1514 slot->flags |= PLATFORM_DATA_STARTED; 1515 } else 1516 sdhci_transfer_pio(slot); 1517 } 1518 /* Handle DMA border. */ 1519 if (intmask & SDHCI_INT_DMA_END) { 1520 data = slot->curcmd->data; 1521 1522 /* Unload DMA buffer ... */ 1523 left = data->len - slot->offset; 1524 if (data->flags & MMC_DATA_READ) { 1525 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1526 BUS_DMASYNC_POSTREAD); 1527 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1528 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1529 } else { 1530 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1531 BUS_DMASYNC_POSTWRITE); 1532 } 1533 /* ... and reload it again. */ 1534 slot->offset += DMA_BLOCK_SIZE; 1535 left = data->len - slot->offset; 1536 if (data->flags & MMC_DATA_READ) { 1537 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1538 BUS_DMASYNC_PREREAD); 1539 } else { 1540 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1541 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1542 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1543 BUS_DMASYNC_PREWRITE); 1544 } 1545 /* Interrupt aggregation: Mask border interrupt 1546 * for the last page. */ 1547 if (left == DMA_BLOCK_SIZE) { 1548 slot->intmask &= ~SDHCI_INT_DMA_END; 1549 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1550 } 1551 /* Restart DMA. */ 1552 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1553 } 1554 /* We have got all data. */ 1555 if (intmask & SDHCI_INT_DATA_END) { 1556 if (slot->flags & PLATFORM_DATA_STARTED) { 1557 slot->flags &= ~PLATFORM_DATA_STARTED; 1558 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1559 } else 1560 sdhci_finish_data(slot); 1561 } 1562 done: 1563 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1564 if (slot->flags & PLATFORM_DATA_STARTED) { 1565 slot->flags &= ~PLATFORM_DATA_STARTED; 1566 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1567 } else 1568 sdhci_finish_data(slot); 1569 } 1570 } 1571 1572 static void 1573 sdhci_acmd_irq(struct sdhci_slot *slot) 1574 { 1575 uint16_t err; 1576 1577 err = RD4(slot, SDHCI_ACMD12_ERR); 1578 if (!slot->curcmd) { 1579 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1580 "there is no active command.\n", err); 1581 sdhci_dumpregs(slot); 1582 return; 1583 } 1584 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1585 sdhci_reset(slot, SDHCI_RESET_CMD); 1586 } 1587 1588 void 1589 sdhci_generic_intr(struct sdhci_slot *slot) 1590 { 1591 uint32_t intmask, present; 1592 1593 SDHCI_LOCK(slot); 1594 /* Read slot interrupt status. */ 1595 intmask = RD4(slot, SDHCI_INT_STATUS); 1596 if (intmask == 0 || intmask == 0xffffffff) { 1597 SDHCI_UNLOCK(slot); 1598 return; 1599 } 1600 if (sdhci_debug > 2) 1601 slot_printf(slot, "Interrupt %#x\n", intmask); 1602 1603 /* Handle card presence interrupts. */ 1604 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1605 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1606 slot->intmask &= 1607 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1608 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1609 SDHCI_INT_CARD_INSERT; 1610 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1611 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1612 WR4(slot, SDHCI_INT_STATUS, intmask & 1613 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1614 sdhci_handle_card_present_locked(slot, present); 1615 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1616 } 1617 /* Handle command interrupts. */ 1618 if (intmask & SDHCI_INT_CMD_MASK) { 1619 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1620 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1621 } 1622 /* Handle data interrupts. */ 1623 if (intmask & SDHCI_INT_DATA_MASK) { 1624 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1625 /* Don't call data_irq in case of errored command. */ 1626 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1627 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1628 } 1629 /* Handle AutoCMD12 error interrupt. */ 1630 if (intmask & SDHCI_INT_ACMD12ERR) { 1631 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1632 sdhci_acmd_irq(slot); 1633 } 1634 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1635 intmask &= ~SDHCI_INT_ACMD12ERR; 1636 intmask &= ~SDHCI_INT_ERROR; 1637 /* Handle bus power interrupt. */ 1638 if (intmask & SDHCI_INT_BUS_POWER) { 1639 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1640 slot_printf(slot, 1641 "Card is consuming too much power!\n"); 1642 intmask &= ~SDHCI_INT_BUS_POWER; 1643 } 1644 /* The rest is unknown. */ 1645 if (intmask) { 1646 WR4(slot, SDHCI_INT_STATUS, intmask); 1647 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1648 intmask); 1649 sdhci_dumpregs(slot); 1650 } 1651 1652 SDHCI_UNLOCK(slot); 1653 } 1654 1655 int 1656 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1657 uintptr_t *result) 1658 { 1659 struct sdhci_slot *slot = device_get_ivars(child); 1660 1661 switch (which) { 1662 default: 1663 return (EINVAL); 1664 case MMCBR_IVAR_BUS_MODE: 1665 *result = slot->host.ios.bus_mode; 1666 break; 1667 case MMCBR_IVAR_BUS_WIDTH: 1668 *result = slot->host.ios.bus_width; 1669 break; 1670 case MMCBR_IVAR_CHIP_SELECT: 1671 *result = slot->host.ios.chip_select; 1672 break; 1673 case MMCBR_IVAR_CLOCK: 1674 *result = slot->host.ios.clock; 1675 break; 1676 case MMCBR_IVAR_F_MIN: 1677 *result = slot->host.f_min; 1678 break; 1679 case MMCBR_IVAR_F_MAX: 1680 *result = slot->host.f_max; 1681 break; 1682 case MMCBR_IVAR_HOST_OCR: 1683 *result = slot->host.host_ocr; 1684 break; 1685 case MMCBR_IVAR_MODE: 1686 *result = slot->host.mode; 1687 break; 1688 case MMCBR_IVAR_OCR: 1689 *result = slot->host.ocr; 1690 break; 1691 case MMCBR_IVAR_POWER_MODE: 1692 *result = slot->host.ios.power_mode; 1693 break; 1694 case MMCBR_IVAR_VDD: 1695 *result = slot->host.ios.vdd; 1696 break; 1697 case MMCBR_IVAR_VCCQ: 1698 *result = slot->host.ios.vccq; 1699 break; 1700 case MMCBR_IVAR_CAPS: 1701 *result = slot->host.caps; 1702 break; 1703 case MMCBR_IVAR_TIMING: 1704 *result = slot->host.ios.timing; 1705 break; 1706 case MMCBR_IVAR_MAX_DATA: 1707 *result = 65535; 1708 break; 1709 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1710 /* 1711 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1712 */ 1713 *result = 1000000; 1714 break; 1715 } 1716 return (0); 1717 } 1718 1719 int 1720 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1721 uintptr_t value) 1722 { 1723 struct sdhci_slot *slot = device_get_ivars(child); 1724 uint32_t clock, max_clock; 1725 int i; 1726 1727 switch (which) { 1728 default: 1729 return (EINVAL); 1730 case MMCBR_IVAR_BUS_MODE: 1731 slot->host.ios.bus_mode = value; 1732 break; 1733 case MMCBR_IVAR_BUS_WIDTH: 1734 slot->host.ios.bus_width = value; 1735 break; 1736 case MMCBR_IVAR_CHIP_SELECT: 1737 slot->host.ios.chip_select = value; 1738 break; 1739 case MMCBR_IVAR_CLOCK: 1740 if (value > 0) { 1741 max_clock = slot->max_clk; 1742 clock = max_clock; 1743 1744 if (slot->version < SDHCI_SPEC_300) { 1745 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1746 i <<= 1) { 1747 if (clock <= value) 1748 break; 1749 clock >>= 1; 1750 } 1751 } else { 1752 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1753 i += 2) { 1754 if (clock <= value) 1755 break; 1756 clock = max_clock / (i + 2); 1757 } 1758 } 1759 1760 slot->host.ios.clock = clock; 1761 } else 1762 slot->host.ios.clock = 0; 1763 break; 1764 case MMCBR_IVAR_MODE: 1765 slot->host.mode = value; 1766 break; 1767 case MMCBR_IVAR_OCR: 1768 slot->host.ocr = value; 1769 break; 1770 case MMCBR_IVAR_POWER_MODE: 1771 slot->host.ios.power_mode = value; 1772 break; 1773 case MMCBR_IVAR_VDD: 1774 slot->host.ios.vdd = value; 1775 break; 1776 case MMCBR_IVAR_VCCQ: 1777 slot->host.ios.vccq = value; 1778 break; 1779 case MMCBR_IVAR_TIMING: 1780 slot->host.ios.timing = value; 1781 break; 1782 case MMCBR_IVAR_CAPS: 1783 case MMCBR_IVAR_HOST_OCR: 1784 case MMCBR_IVAR_F_MIN: 1785 case MMCBR_IVAR_F_MAX: 1786 case MMCBR_IVAR_MAX_DATA: 1787 return (EINVAL); 1788 } 1789 return (0); 1790 } 1791 1792 MODULE_VERSION(sdhci, 1); 1793