1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <machine/stdarg.h> 45 46 #include <dev/mmc/bridge.h> 47 #include <dev/mmc/mmcreg.h> 48 #include <dev/mmc/mmcbrvar.h> 49 50 #include "mmcbr_if.h" 51 #include "sdhci.h" 52 #include "sdhci_if.h" 53 54 struct sdhci_softc; 55 56 struct sdhci_softc { 57 device_t dev; /* Controller device */ 58 struct resource *irq_res; /* IRQ resource */ 59 int irq_rid; 60 void *intrhand; /* Interrupt handle */ 61 62 int num_slots; /* Number of slots on this controller */ 63 struct sdhci_slot slots[6]; 64 }; 65 66 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 67 68 int sdhci_debug = 0; 69 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 70 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 71 72 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 73 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 74 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 75 #define RD_MULTI_4(slot, off, ptr, count) \ 76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 77 78 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 79 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 80 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 81 #define WR_MULTI_4(slot, off, ptr, count) \ 82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 83 84 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 85 static void sdhci_start(struct sdhci_slot *slot); 86 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 87 88 static void sdhci_card_task(void *, int); 89 90 /* helper routines */ 91 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93 #define SDHCI_LOCK_INIT(_slot) \ 94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98 99 #define SDHCI_DEFAULT_MAX_FREQ 50 100 101 #define SDHCI_200_MAX_DIVIDER 256 102 #define SDHCI_300_MAX_DIVIDER 2046 103 104 static void 105 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 106 { 107 if (error != 0) { 108 printf("getaddr: error %d\n", error); 109 return; 110 } 111 *(bus_addr_t *)arg = segs[0].ds_addr; 112 } 113 114 static int 115 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 116 { 117 va_list ap; 118 int retval; 119 120 retval = printf("%s-slot%d: ", 121 device_get_nameunit(slot->bus), slot->num); 122 123 va_start(ap, fmt); 124 retval += vprintf(fmt, ap); 125 va_end(ap); 126 return (retval); 127 } 128 129 static void 130 sdhci_dumpregs(struct sdhci_slot *slot) 131 { 132 slot_printf(slot, 133 "============== REGISTER DUMP ==============\n"); 134 135 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 136 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 137 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 138 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 139 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 140 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 141 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 142 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 143 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 144 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 145 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 146 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 147 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 148 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 149 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 150 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 151 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 152 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 153 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 154 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 155 156 slot_printf(slot, 157 "===========================================\n"); 158 } 159 160 static void 161 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 162 { 163 int timeout; 164 uint8_t res; 165 166 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 167 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 168 SDHCI_CARD_PRESENT)) 169 return; 170 } 171 172 /* Some controllers need this kick or reset won't work. */ 173 if ((mask & SDHCI_RESET_ALL) == 0 && 174 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 175 uint32_t clock; 176 177 /* This is to force an update */ 178 clock = slot->clock; 179 slot->clock = 0; 180 sdhci_set_clock(slot, clock); 181 } 182 183 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 184 185 if (mask & SDHCI_RESET_ALL) { 186 slot->clock = 0; 187 slot->power = 0; 188 } 189 190 /* Wait max 100 ms */ 191 timeout = 100; 192 /* Controller clears the bits when it's done */ 193 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 194 if (timeout == 0) { 195 slot_printf(slot, 196 "Reset 0x%x never completed - 0x%x.\n", 197 (int)mask, (int)res); 198 sdhci_dumpregs(slot); 199 return; 200 } 201 timeout--; 202 DELAY(1000); 203 } 204 } 205 206 static void 207 sdhci_init(struct sdhci_slot *slot) 208 { 209 210 sdhci_reset(slot, SDHCI_RESET_ALL); 211 212 /* Enable interrupts. */ 213 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 214 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 215 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 216 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 217 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 218 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 219 SDHCI_INT_ACMD12ERR; 220 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 221 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 222 } 223 224 static void 225 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 226 { 227 uint32_t res; 228 uint16_t clk; 229 uint16_t div; 230 int timeout; 231 232 if (clock == slot->clock) 233 return; 234 slot->clock = clock; 235 236 /* Turn off the clock. */ 237 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 238 /* If no clock requested - left it so. */ 239 if (clock == 0) 240 return; 241 if (slot->version < SDHCI_SPEC_300) { 242 /* Looking for highest freq <= clock. */ 243 res = slot->max_clk; 244 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 245 if (res <= clock) 246 break; 247 res >>= 1; 248 } 249 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 250 div >>= 1; 251 } 252 else { 253 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 254 if (clock >= slot->max_clk) 255 div = 0; 256 else { 257 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 258 if ((slot->max_clk / div) <= clock) 259 break; 260 } 261 } 262 div >>= 1; 263 } 264 265 if (bootverbose || sdhci_debug) 266 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 267 div, clock, slot->max_clk); 268 269 /* Now we have got divider, set it. */ 270 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 271 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 272 << SDHCI_DIVIDER_HI_SHIFT; 273 274 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 275 /* Enable clock. */ 276 clk |= SDHCI_CLOCK_INT_EN; 277 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 278 /* Wait up to 10 ms until it stabilize. */ 279 timeout = 10; 280 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 281 & SDHCI_CLOCK_INT_STABLE)) { 282 if (timeout == 0) { 283 slot_printf(slot, 284 "Internal clock never stabilised.\n"); 285 sdhci_dumpregs(slot); 286 return; 287 } 288 timeout--; 289 DELAY(1000); 290 } 291 /* Pass clock signal to the bus. */ 292 clk |= SDHCI_CLOCK_CARD_EN; 293 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 294 } 295 296 static void 297 sdhci_set_power(struct sdhci_slot *slot, u_char power) 298 { 299 uint8_t pwr; 300 301 if (slot->power == power) 302 return; 303 304 slot->power = power; 305 306 /* Turn off the power. */ 307 pwr = 0; 308 WR1(slot, SDHCI_POWER_CONTROL, pwr); 309 /* If power down requested - left it so. */ 310 if (power == 0) 311 return; 312 /* Set voltage. */ 313 switch (1 << power) { 314 case MMC_OCR_LOW_VOLTAGE: 315 pwr |= SDHCI_POWER_180; 316 break; 317 case MMC_OCR_290_300: 318 case MMC_OCR_300_310: 319 pwr |= SDHCI_POWER_300; 320 break; 321 case MMC_OCR_320_330: 322 case MMC_OCR_330_340: 323 pwr |= SDHCI_POWER_330; 324 break; 325 } 326 WR1(slot, SDHCI_POWER_CONTROL, pwr); 327 /* Turn on the power. */ 328 pwr |= SDHCI_POWER_ON; 329 WR1(slot, SDHCI_POWER_CONTROL, pwr); 330 } 331 332 static void 333 sdhci_read_block_pio(struct sdhci_slot *slot) 334 { 335 uint32_t data; 336 char *buffer; 337 size_t left; 338 339 buffer = slot->curcmd->data->data; 340 buffer += slot->offset; 341 /* Transfer one block at a time. */ 342 left = min(512, slot->curcmd->data->len - slot->offset); 343 slot->offset += left; 344 345 /* If we are too fast, broken controllers return zeroes. */ 346 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 347 DELAY(10); 348 /* Handle unalligned and alligned buffer cases. */ 349 if ((intptr_t)buffer & 3) { 350 while (left > 3) { 351 data = RD4(slot, SDHCI_BUFFER); 352 buffer[0] = data; 353 buffer[1] = (data >> 8); 354 buffer[2] = (data >> 16); 355 buffer[3] = (data >> 24); 356 buffer += 4; 357 left -= 4; 358 } 359 } else { 360 RD_MULTI_4(slot, SDHCI_BUFFER, 361 (uint32_t *)buffer, left >> 2); 362 left &= 3; 363 } 364 /* Handle uneven size case. */ 365 if (left > 0) { 366 data = RD4(slot, SDHCI_BUFFER); 367 while (left > 0) { 368 *(buffer++) = data; 369 data >>= 8; 370 left--; 371 } 372 } 373 } 374 375 static void 376 sdhci_write_block_pio(struct sdhci_slot *slot) 377 { 378 uint32_t data = 0; 379 char *buffer; 380 size_t left; 381 382 buffer = slot->curcmd->data->data; 383 buffer += slot->offset; 384 /* Transfer one block at a time. */ 385 left = min(512, slot->curcmd->data->len - slot->offset); 386 slot->offset += left; 387 388 /* Handle unalligned and alligned buffer cases. */ 389 if ((intptr_t)buffer & 3) { 390 while (left > 3) { 391 data = buffer[0] + 392 (buffer[1] << 8) + 393 (buffer[2] << 16) + 394 (buffer[3] << 24); 395 left -= 4; 396 buffer += 4; 397 WR4(slot, SDHCI_BUFFER, data); 398 } 399 } else { 400 WR_MULTI_4(slot, SDHCI_BUFFER, 401 (uint32_t *)buffer, left >> 2); 402 left &= 3; 403 } 404 /* Handle uneven size case. */ 405 if (left > 0) { 406 while (left > 0) { 407 data <<= 8; 408 data += *(buffer++); 409 left--; 410 } 411 WR4(slot, SDHCI_BUFFER, data); 412 } 413 } 414 415 static void 416 sdhci_transfer_pio(struct sdhci_slot *slot) 417 { 418 419 /* Read as many blocks as possible. */ 420 if (slot->curcmd->data->flags & MMC_DATA_READ) { 421 while (RD4(slot, SDHCI_PRESENT_STATE) & 422 SDHCI_DATA_AVAILABLE) { 423 sdhci_read_block_pio(slot); 424 if (slot->offset >= slot->curcmd->data->len) 425 break; 426 } 427 } else { 428 while (RD4(slot, SDHCI_PRESENT_STATE) & 429 SDHCI_SPACE_AVAILABLE) { 430 sdhci_write_block_pio(slot); 431 if (slot->offset >= slot->curcmd->data->len) 432 break; 433 } 434 } 435 } 436 437 static void 438 sdhci_card_delay(void *arg) 439 { 440 struct sdhci_slot *slot = arg; 441 442 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 443 } 444 445 static void 446 sdhci_card_task(void *arg, int pending) 447 { 448 struct sdhci_slot *slot = arg; 449 450 SDHCI_LOCK(slot); 451 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 452 if (slot->dev == NULL) { 453 /* If card is present - attach mmc bus. */ 454 slot->dev = device_add_child(slot->bus, "mmc", -1); 455 device_set_ivars(slot->dev, slot); 456 SDHCI_UNLOCK(slot); 457 device_probe_and_attach(slot->dev); 458 } else 459 SDHCI_UNLOCK(slot); 460 } else { 461 if (slot->dev != NULL) { 462 /* If no card present - detach mmc bus. */ 463 device_t d = slot->dev; 464 slot->dev = NULL; 465 SDHCI_UNLOCK(slot); 466 device_delete_child(slot->bus, d); 467 } else 468 SDHCI_UNLOCK(slot); 469 } 470 } 471 472 int 473 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 474 { 475 uint32_t caps; 476 int err; 477 478 SDHCI_LOCK_INIT(slot); 479 slot->num = num; 480 slot->bus = dev; 481 482 /* Allocate DMA tag. */ 483 err = bus_dma_tag_create(bus_get_dma_tag(dev), 484 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 485 BUS_SPACE_MAXADDR, NULL, NULL, 486 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 487 BUS_DMA_ALLOCNOW, NULL, NULL, 488 &slot->dmatag); 489 if (err != 0) { 490 device_printf(dev, "Can't create DMA tag\n"); 491 SDHCI_LOCK_DESTROY(slot); 492 return (err); 493 } 494 /* Allocate DMA memory. */ 495 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 496 BUS_DMA_NOWAIT, &slot->dmamap); 497 if (err != 0) { 498 device_printf(dev, "Can't alloc DMA memory\n"); 499 SDHCI_LOCK_DESTROY(slot); 500 return (err); 501 } 502 /* Map the memory. */ 503 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 504 (void *)slot->dmamem, DMA_BLOCK_SIZE, 505 sdhci_getaddr, &slot->paddr, 0); 506 if (err != 0 || slot->paddr == 0) { 507 device_printf(dev, "Can't load DMA memory\n"); 508 SDHCI_LOCK_DESTROY(slot); 509 if(err) 510 return (err); 511 else 512 return (EFAULT); 513 } 514 515 /* Initialize slot. */ 516 sdhci_init(slot); 517 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 518 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 519 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 520 caps = slot->caps; 521 else 522 caps = RD4(slot, SDHCI_CAPABILITIES); 523 /* Calculate base clock frequency. */ 524 if (slot->version >= SDHCI_SPEC_300) 525 slot->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) 526 >> SDHCI_CLOCK_BASE_SHIFT; 527 else 528 slot->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) 529 >> SDHCI_CLOCK_BASE_SHIFT; 530 if (slot->max_clk == 0) { 531 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ; 532 device_printf(dev, "Hardware doesn't specify base clock " 533 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 534 } 535 slot->max_clk *= 1000000; 536 /* Calculate timeout clock frequency. */ 537 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 538 slot->timeout_clk = slot->max_clk / 1000; 539 } else { 540 slot->timeout_clk = 541 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 542 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 543 slot->timeout_clk *= 1000; 544 } 545 546 if (slot->timeout_clk == 0) { 547 device_printf(dev, "Hardware doesn't specify timeout clock " 548 "frequency.\n"); 549 } 550 551 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 552 slot->host.f_max = slot->max_clk; 553 slot->host.host_ocr = 0; 554 if (caps & SDHCI_CAN_VDD_330) 555 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 556 if (caps & SDHCI_CAN_VDD_300) 557 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 558 if (caps & SDHCI_CAN_VDD_180) 559 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 560 if (slot->host.host_ocr == 0) { 561 device_printf(dev, "Hardware doesn't report any " 562 "support voltages.\n"); 563 } 564 slot->host.caps = MMC_CAP_4_BIT_DATA; 565 if (caps & SDHCI_CAN_DO_HISPD) 566 slot->host.caps |= MMC_CAP_HSPEED; 567 /* Decide if we have usable DMA. */ 568 if (caps & SDHCI_CAN_DO_DMA) 569 slot->opt |= SDHCI_HAVE_DMA; 570 571 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 572 slot->opt &= ~SDHCI_HAVE_DMA; 573 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 574 slot->opt |= SDHCI_HAVE_DMA; 575 576 if (bootverbose || sdhci_debug) { 577 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 578 slot->max_clk / 1000000, 579 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 580 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 581 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 582 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 583 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 584 sdhci_dumpregs(slot); 585 } 586 587 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 588 callout_init(&slot->card_callout, 1); 589 return (0); 590 } 591 592 void 593 sdhci_start_slot(struct sdhci_slot *slot) 594 { 595 sdhci_card_task(slot, 0); 596 } 597 598 int 599 sdhci_cleanup_slot(struct sdhci_slot *slot) 600 { 601 device_t d; 602 603 callout_drain(&slot->card_callout); 604 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 605 606 SDHCI_LOCK(slot); 607 d = slot->dev; 608 slot->dev = NULL; 609 SDHCI_UNLOCK(slot); 610 if (d != NULL) 611 device_delete_child(slot->bus, d); 612 613 SDHCI_LOCK(slot); 614 sdhci_reset(slot, SDHCI_RESET_ALL); 615 SDHCI_UNLOCK(slot); 616 bus_dmamap_unload(slot->dmatag, slot->dmamap); 617 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 618 bus_dma_tag_destroy(slot->dmatag); 619 620 SDHCI_LOCK_DESTROY(slot); 621 622 return (0); 623 } 624 625 int 626 sdhci_generic_suspend(struct sdhci_slot *slot) 627 { 628 sdhci_reset(slot, SDHCI_RESET_ALL); 629 630 return (0); 631 } 632 633 int 634 sdhci_generic_resume(struct sdhci_slot *slot) 635 { 636 sdhci_init(slot); 637 638 return (0); 639 } 640 641 uint32_t 642 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 643 { 644 if (slot->version >= SDHCI_SPEC_300) 645 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 646 else 647 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 648 } 649 650 int 651 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 652 { 653 struct sdhci_slot *slot = device_get_ivars(reqdev); 654 struct mmc_ios *ios = &slot->host.ios; 655 656 SDHCI_LOCK(slot); 657 /* Do full reset on bus power down to clear from any state. */ 658 if (ios->power_mode == power_off) { 659 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 660 sdhci_init(slot); 661 } 662 /* Configure the bus. */ 663 sdhci_set_clock(slot, ios->clock); 664 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 665 if (ios->bus_width == bus_width_4) 666 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 667 else 668 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 669 if (ios->timing == bus_timing_hs) 670 slot->hostctrl |= SDHCI_CTRL_HISPD; 671 else 672 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 673 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 674 /* Some controllers like reset after bus changes. */ 675 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 676 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 677 678 SDHCI_UNLOCK(slot); 679 return (0); 680 } 681 682 static void 683 sdhci_set_transfer_mode(struct sdhci_slot *slot, 684 struct mmc_data *data) 685 { 686 uint16_t mode; 687 688 if (data == NULL) 689 return; 690 691 mode = SDHCI_TRNS_BLK_CNT_EN; 692 if (data->len > 512) 693 mode |= SDHCI_TRNS_MULTI; 694 if (data->flags & MMC_DATA_READ) 695 mode |= SDHCI_TRNS_READ; 696 if (slot->req->stop) 697 mode |= SDHCI_TRNS_ACMD12; 698 if (slot->flags & SDHCI_USE_DMA) 699 mode |= SDHCI_TRNS_DMA; 700 701 WR2(slot, SDHCI_TRANSFER_MODE, mode); 702 } 703 704 static void 705 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 706 { 707 struct mmc_request *req = slot->req; 708 int flags, timeout; 709 uint32_t mask, state; 710 711 slot->curcmd = cmd; 712 slot->cmd_done = 0; 713 714 cmd->error = MMC_ERR_NONE; 715 716 /* This flags combination is not supported by controller. */ 717 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 718 slot_printf(slot, "Unsupported response type!\n"); 719 cmd->error = MMC_ERR_FAILED; 720 slot->req = NULL; 721 slot->curcmd = NULL; 722 req->done(req); 723 return; 724 } 725 726 /* Read controller present state. */ 727 state = RD4(slot, SDHCI_PRESENT_STATE); 728 /* Do not issue command if there is no card, clock or power. 729 * Controller will not detect timeout without clock active. */ 730 if ((state & SDHCI_CARD_PRESENT) == 0 || 731 slot->power == 0 || 732 slot->clock == 0) { 733 cmd->error = MMC_ERR_FAILED; 734 slot->req = NULL; 735 slot->curcmd = NULL; 736 req->done(req); 737 return; 738 } 739 /* Always wait for free CMD bus. */ 740 mask = SDHCI_CMD_INHIBIT; 741 /* Wait for free DAT if we have data or busy signal. */ 742 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 743 mask |= SDHCI_DAT_INHIBIT; 744 /* We shouldn't wait for DAT for stop commands. */ 745 if (cmd == slot->req->stop) 746 mask &= ~SDHCI_DAT_INHIBIT; 747 /* Wait for bus no more then 10 ms. */ 748 timeout = 10; 749 while (state & mask) { 750 if (timeout == 0) { 751 slot_printf(slot, "Controller never released " 752 "inhibit bit(s).\n"); 753 sdhci_dumpregs(slot); 754 cmd->error = MMC_ERR_FAILED; 755 slot->req = NULL; 756 slot->curcmd = NULL; 757 req->done(req); 758 return; 759 } 760 timeout--; 761 DELAY(1000); 762 state = RD4(slot, SDHCI_PRESENT_STATE); 763 } 764 765 /* Prepare command flags. */ 766 if (!(cmd->flags & MMC_RSP_PRESENT)) 767 flags = SDHCI_CMD_RESP_NONE; 768 else if (cmd->flags & MMC_RSP_136) 769 flags = SDHCI_CMD_RESP_LONG; 770 else if (cmd->flags & MMC_RSP_BUSY) 771 flags = SDHCI_CMD_RESP_SHORT_BUSY; 772 else 773 flags = SDHCI_CMD_RESP_SHORT; 774 if (cmd->flags & MMC_RSP_CRC) 775 flags |= SDHCI_CMD_CRC; 776 if (cmd->flags & MMC_RSP_OPCODE) 777 flags |= SDHCI_CMD_INDEX; 778 if (cmd->data) 779 flags |= SDHCI_CMD_DATA; 780 if (cmd->opcode == MMC_STOP_TRANSMISSION) 781 flags |= SDHCI_CMD_TYPE_ABORT; 782 /* Prepare data. */ 783 sdhci_start_data(slot, cmd->data); 784 /* 785 * Interrupt aggregation: To reduce total number of interrupts 786 * group response interrupt with data interrupt when possible. 787 * If there going to be data interrupt, mask response one. 788 */ 789 if (slot->data_done == 0) { 790 WR4(slot, SDHCI_SIGNAL_ENABLE, 791 slot->intmask &= ~SDHCI_INT_RESPONSE); 792 } 793 /* Set command argument. */ 794 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 795 /* Set data transfer mode. */ 796 sdhci_set_transfer_mode(slot, cmd->data); 797 /* Start command. */ 798 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 799 } 800 801 static void 802 sdhci_finish_command(struct sdhci_slot *slot) 803 { 804 int i; 805 806 slot->cmd_done = 1; 807 /* Interrupt aggregation: Restore command interrupt. 808 * Main restore point for the case when command interrupt 809 * happened first. */ 810 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 811 /* In case of error - reset host and return. */ 812 if (slot->curcmd->error) { 813 sdhci_reset(slot, SDHCI_RESET_CMD); 814 sdhci_reset(slot, SDHCI_RESET_DATA); 815 sdhci_start(slot); 816 return; 817 } 818 /* If command has response - fetch it. */ 819 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 820 if (slot->curcmd->flags & MMC_RSP_136) { 821 /* CRC is stripped so we need one byte shift. */ 822 uint8_t extra = 0; 823 for (i = 0; i < 4; i++) { 824 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 825 slot->curcmd->resp[3 - i] = (val << 8) + extra; 826 extra = val >> 24; 827 } 828 } else 829 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 830 } 831 /* If data ready - finish. */ 832 if (slot->data_done) 833 sdhci_start(slot); 834 } 835 836 static void 837 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 838 { 839 uint32_t target_timeout, current_timeout; 840 uint8_t div; 841 842 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 843 slot->data_done = 1; 844 return; 845 } 846 847 slot->data_done = 0; 848 849 /* Calculate and set data timeout.*/ 850 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 851 target_timeout = 1000000; 852 div = 0; 853 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 854 while (current_timeout < target_timeout) { 855 div++; 856 current_timeout <<= 1; 857 if (div >= 0xF) 858 break; 859 } 860 /* Compensate for an off-by-one error in the CaFe chip.*/ 861 if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 862 div++; 863 if (div >= 0xF) { 864 slot_printf(slot, "Timeout too large!\n"); 865 div = 0xE; 866 } 867 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 868 div = 0xE; 869 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 870 871 if (data == NULL) 872 return; 873 874 /* Use DMA if possible. */ 875 if ((slot->opt & SDHCI_HAVE_DMA)) 876 slot->flags |= SDHCI_USE_DMA; 877 /* If data is small, broken DMA may return zeroes instead of data, */ 878 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 879 (data->len <= 512)) 880 slot->flags &= ~SDHCI_USE_DMA; 881 /* Some controllers require even block sizes. */ 882 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 883 ((data->len) & 0x3)) 884 slot->flags &= ~SDHCI_USE_DMA; 885 /* Load DMA buffer. */ 886 if (slot->flags & SDHCI_USE_DMA) { 887 if (data->flags & MMC_DATA_READ) 888 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 889 else { 890 memcpy(slot->dmamem, data->data, 891 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 892 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 893 } 894 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 895 /* Interrupt aggregation: Mask border interrupt 896 * for the last page and unmask else. */ 897 if (data->len == DMA_BLOCK_SIZE) 898 slot->intmask &= ~SDHCI_INT_DMA_END; 899 else 900 slot->intmask |= SDHCI_INT_DMA_END; 901 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 902 } 903 /* Current data offset for both PIO and DMA. */ 904 slot->offset = 0; 905 /* Set block size and request IRQ on 4K border. */ 906 WR2(slot, SDHCI_BLOCK_SIZE, 907 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 908 /* Set block count. */ 909 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 910 } 911 912 static void 913 sdhci_finish_data(struct sdhci_slot *slot) 914 { 915 struct mmc_data *data = slot->curcmd->data; 916 917 slot->data_done = 1; 918 /* Interrupt aggregation: Restore command interrupt. 919 * Auxillary restore point for the case when data interrupt 920 * happened first. */ 921 if (!slot->cmd_done) { 922 WR4(slot, SDHCI_SIGNAL_ENABLE, 923 slot->intmask |= SDHCI_INT_RESPONSE); 924 } 925 /* Unload rest of data from DMA buffer. */ 926 if (slot->flags & SDHCI_USE_DMA) { 927 if (data->flags & MMC_DATA_READ) { 928 size_t left = data->len - slot->offset; 929 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 930 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 931 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 932 } else 933 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 934 } 935 /* If there was error - reset the host. */ 936 if (slot->curcmd->error) { 937 sdhci_reset(slot, SDHCI_RESET_CMD); 938 sdhci_reset(slot, SDHCI_RESET_DATA); 939 sdhci_start(slot); 940 return; 941 } 942 /* If we already have command response - finish. */ 943 if (slot->cmd_done) 944 sdhci_start(slot); 945 } 946 947 static void 948 sdhci_start(struct sdhci_slot *slot) 949 { 950 struct mmc_request *req; 951 952 req = slot->req; 953 if (req == NULL) 954 return; 955 956 if (!(slot->flags & CMD_STARTED)) { 957 slot->flags |= CMD_STARTED; 958 sdhci_start_command(slot, req->cmd); 959 return; 960 } 961 /* We don't need this until using Auto-CMD12 feature 962 if (!(slot->flags & STOP_STARTED) && req->stop) { 963 slot->flags |= STOP_STARTED; 964 sdhci_start_command(slot, req->stop); 965 return; 966 } 967 */ 968 if (sdhci_debug > 1) 969 slot_printf(slot, "result: %d\n", req->cmd->error); 970 if (!req->cmd->error && 971 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 972 sdhci_reset(slot, SDHCI_RESET_CMD); 973 sdhci_reset(slot, SDHCI_RESET_DATA); 974 } 975 976 /* We must be done -- bad idea to do this while locked? */ 977 slot->req = NULL; 978 slot->curcmd = NULL; 979 req->done(req); 980 } 981 982 int 983 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 984 { 985 struct sdhci_slot *slot = device_get_ivars(reqdev); 986 987 SDHCI_LOCK(slot); 988 if (slot->req != NULL) { 989 SDHCI_UNLOCK(slot); 990 return (EBUSY); 991 } 992 if (sdhci_debug > 1) { 993 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 994 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 995 (req->cmd->data)?(u_int)req->cmd->data->len:0, 996 (req->cmd->data)?req->cmd->data->flags:0); 997 } 998 slot->req = req; 999 slot->flags = 0; 1000 sdhci_start(slot); 1001 SDHCI_UNLOCK(slot); 1002 if (dumping) { 1003 while (slot->req != NULL) { 1004 sdhci_generic_intr(slot); 1005 DELAY(10); 1006 } 1007 } 1008 return (0); 1009 } 1010 1011 int 1012 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1013 { 1014 struct sdhci_slot *slot = device_get_ivars(reqdev); 1015 uint32_t val; 1016 1017 SDHCI_LOCK(slot); 1018 val = RD4(slot, SDHCI_PRESENT_STATE); 1019 SDHCI_UNLOCK(slot); 1020 return (!(val & SDHCI_WRITE_PROTECT)); 1021 } 1022 1023 int 1024 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1025 { 1026 struct sdhci_slot *slot = device_get_ivars(reqdev); 1027 int err = 0; 1028 1029 SDHCI_LOCK(slot); 1030 while (slot->bus_busy) 1031 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1032 slot->bus_busy++; 1033 /* Activate led. */ 1034 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1035 SDHCI_UNLOCK(slot); 1036 return (err); 1037 } 1038 1039 int 1040 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1041 { 1042 struct sdhci_slot *slot = device_get_ivars(reqdev); 1043 1044 SDHCI_LOCK(slot); 1045 /* Deactivate led. */ 1046 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1047 slot->bus_busy--; 1048 SDHCI_UNLOCK(slot); 1049 wakeup(slot); 1050 return (0); 1051 } 1052 1053 static void 1054 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1055 { 1056 1057 if (!slot->curcmd) { 1058 slot_printf(slot, "Got command interrupt 0x%08x, but " 1059 "there is no active command.\n", intmask); 1060 sdhci_dumpregs(slot); 1061 return; 1062 } 1063 if (intmask & SDHCI_INT_TIMEOUT) 1064 slot->curcmd->error = MMC_ERR_TIMEOUT; 1065 else if (intmask & SDHCI_INT_CRC) 1066 slot->curcmd->error = MMC_ERR_BADCRC; 1067 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1068 slot->curcmd->error = MMC_ERR_FIFO; 1069 1070 sdhci_finish_command(slot); 1071 } 1072 1073 static void 1074 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1075 { 1076 1077 if (!slot->curcmd) { 1078 slot_printf(slot, "Got data interrupt 0x%08x, but " 1079 "there is no active command.\n", intmask); 1080 sdhci_dumpregs(slot); 1081 return; 1082 } 1083 if (slot->curcmd->data == NULL && 1084 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1085 slot_printf(slot, "Got data interrupt 0x%08x, but " 1086 "there is no active data operation.\n", 1087 intmask); 1088 sdhci_dumpregs(slot); 1089 return; 1090 } 1091 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1092 slot->curcmd->error = MMC_ERR_TIMEOUT; 1093 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1094 slot->curcmd->error = MMC_ERR_BADCRC; 1095 if (slot->curcmd->data == NULL && 1096 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1097 SDHCI_INT_DMA_END))) { 1098 slot_printf(slot, "Got data interrupt 0x%08x, but " 1099 "there is busy-only command.\n", intmask); 1100 sdhci_dumpregs(slot); 1101 slot->curcmd->error = MMC_ERR_INVALID; 1102 } 1103 if (slot->curcmd->error) { 1104 /* No need to continue after any error. */ 1105 sdhci_finish_data(slot); 1106 return; 1107 } 1108 1109 /* Handle PIO interrupt. */ 1110 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1111 sdhci_transfer_pio(slot); 1112 /* Handle DMA border. */ 1113 if (intmask & SDHCI_INT_DMA_END) { 1114 struct mmc_data *data = slot->curcmd->data; 1115 size_t left; 1116 1117 /* Unload DMA buffer... */ 1118 left = data->len - slot->offset; 1119 if (data->flags & MMC_DATA_READ) { 1120 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1121 BUS_DMASYNC_POSTREAD); 1122 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1123 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1124 } else { 1125 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1126 BUS_DMASYNC_POSTWRITE); 1127 } 1128 /* ... and reload it again. */ 1129 slot->offset += DMA_BLOCK_SIZE; 1130 left = data->len - slot->offset; 1131 if (data->flags & MMC_DATA_READ) { 1132 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1133 BUS_DMASYNC_PREREAD); 1134 } else { 1135 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1136 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1137 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1138 BUS_DMASYNC_PREWRITE); 1139 } 1140 /* Interrupt aggregation: Mask border interrupt 1141 * for the last page. */ 1142 if (left == DMA_BLOCK_SIZE) { 1143 slot->intmask &= ~SDHCI_INT_DMA_END; 1144 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1145 } 1146 /* Restart DMA. */ 1147 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1148 } 1149 /* We have got all data. */ 1150 if (intmask & SDHCI_INT_DATA_END) 1151 sdhci_finish_data(slot); 1152 } 1153 1154 static void 1155 sdhci_acmd_irq(struct sdhci_slot *slot) 1156 { 1157 uint16_t err; 1158 1159 err = RD4(slot, SDHCI_ACMD12_ERR); 1160 if (!slot->curcmd) { 1161 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1162 "there is no active command.\n", err); 1163 sdhci_dumpregs(slot); 1164 return; 1165 } 1166 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1167 sdhci_reset(slot, SDHCI_RESET_CMD); 1168 } 1169 1170 void 1171 sdhci_generic_intr(struct sdhci_slot *slot) 1172 { 1173 uint32_t intmask; 1174 1175 SDHCI_LOCK(slot); 1176 /* Read slot interrupt status. */ 1177 intmask = RD4(slot, SDHCI_INT_STATUS); 1178 if (intmask == 0 || intmask == 0xffffffff) { 1179 SDHCI_UNLOCK(slot); 1180 return; 1181 } 1182 if (sdhci_debug > 2) 1183 slot_printf(slot, "Interrupt %#x\n", intmask); 1184 1185 /* Handle card presence interrupts. */ 1186 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1187 WR4(slot, SDHCI_INT_STATUS, intmask & 1188 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1189 1190 if (intmask & SDHCI_INT_CARD_REMOVE) { 1191 if (bootverbose || sdhci_debug) 1192 slot_printf(slot, "Card removed\n"); 1193 callout_stop(&slot->card_callout); 1194 taskqueue_enqueue(taskqueue_swi_giant, 1195 &slot->card_task); 1196 } 1197 if (intmask & SDHCI_INT_CARD_INSERT) { 1198 if (bootverbose || sdhci_debug) 1199 slot_printf(slot, "Card inserted\n"); 1200 callout_reset(&slot->card_callout, hz / 2, 1201 sdhci_card_delay, slot); 1202 } 1203 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1204 } 1205 /* Handle command interrupts. */ 1206 if (intmask & SDHCI_INT_CMD_MASK) { 1207 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1208 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1209 } 1210 /* Handle data interrupts. */ 1211 if (intmask & SDHCI_INT_DATA_MASK) { 1212 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1213 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1214 } 1215 /* Handle AutoCMD12 error interrupt. */ 1216 if (intmask & SDHCI_INT_ACMD12ERR) { 1217 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1218 sdhci_acmd_irq(slot); 1219 } 1220 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1221 intmask &= ~SDHCI_INT_ACMD12ERR; 1222 intmask &= ~SDHCI_INT_ERROR; 1223 /* Handle bus power interrupt. */ 1224 if (intmask & SDHCI_INT_BUS_POWER) { 1225 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1226 slot_printf(slot, 1227 "Card is consuming too much power!\n"); 1228 intmask &= ~SDHCI_INT_BUS_POWER; 1229 } 1230 /* The rest is unknown. */ 1231 if (intmask) { 1232 WR4(slot, SDHCI_INT_STATUS, intmask); 1233 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1234 intmask); 1235 sdhci_dumpregs(slot); 1236 } 1237 1238 SDHCI_UNLOCK(slot); 1239 } 1240 1241 int 1242 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1243 { 1244 struct sdhci_slot *slot = device_get_ivars(child); 1245 1246 switch (which) { 1247 default: 1248 return (EINVAL); 1249 case MMCBR_IVAR_BUS_MODE: 1250 *result = slot->host.ios.bus_mode; 1251 break; 1252 case MMCBR_IVAR_BUS_WIDTH: 1253 *result = slot->host.ios.bus_width; 1254 break; 1255 case MMCBR_IVAR_CHIP_SELECT: 1256 *result = slot->host.ios.chip_select; 1257 break; 1258 case MMCBR_IVAR_CLOCK: 1259 *result = slot->host.ios.clock; 1260 break; 1261 case MMCBR_IVAR_F_MIN: 1262 *result = slot->host.f_min; 1263 break; 1264 case MMCBR_IVAR_F_MAX: 1265 *result = slot->host.f_max; 1266 break; 1267 case MMCBR_IVAR_HOST_OCR: 1268 *result = slot->host.host_ocr; 1269 break; 1270 case MMCBR_IVAR_MODE: 1271 *result = slot->host.mode; 1272 break; 1273 case MMCBR_IVAR_OCR: 1274 *result = slot->host.ocr; 1275 break; 1276 case MMCBR_IVAR_POWER_MODE: 1277 *result = slot->host.ios.power_mode; 1278 break; 1279 case MMCBR_IVAR_VDD: 1280 *result = slot->host.ios.vdd; 1281 break; 1282 case MMCBR_IVAR_CAPS: 1283 *result = slot->host.caps; 1284 break; 1285 case MMCBR_IVAR_TIMING: 1286 *result = slot->host.ios.timing; 1287 break; 1288 case MMCBR_IVAR_MAX_DATA: 1289 *result = 65535; 1290 break; 1291 } 1292 return (0); 1293 } 1294 1295 int 1296 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1297 { 1298 struct sdhci_slot *slot = device_get_ivars(child); 1299 1300 switch (which) { 1301 default: 1302 return (EINVAL); 1303 case MMCBR_IVAR_BUS_MODE: 1304 slot->host.ios.bus_mode = value; 1305 break; 1306 case MMCBR_IVAR_BUS_WIDTH: 1307 slot->host.ios.bus_width = value; 1308 break; 1309 case MMCBR_IVAR_CHIP_SELECT: 1310 slot->host.ios.chip_select = value; 1311 break; 1312 case MMCBR_IVAR_CLOCK: 1313 if (value > 0) { 1314 uint32_t max_clock; 1315 uint32_t clock; 1316 int i; 1317 1318 max_clock = slot->max_clk; 1319 clock = max_clock; 1320 1321 if (slot->version < SDHCI_SPEC_300) { 1322 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1323 i <<= 1) { 1324 if (clock <= value) 1325 break; 1326 clock >>= 1; 1327 } 1328 } 1329 else { 1330 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1331 i += 2) { 1332 if (clock <= value) 1333 break; 1334 clock = max_clock / (i + 2); 1335 } 1336 } 1337 1338 slot->host.ios.clock = clock; 1339 } else 1340 slot->host.ios.clock = 0; 1341 break; 1342 case MMCBR_IVAR_MODE: 1343 slot->host.mode = value; 1344 break; 1345 case MMCBR_IVAR_OCR: 1346 slot->host.ocr = value; 1347 break; 1348 case MMCBR_IVAR_POWER_MODE: 1349 slot->host.ios.power_mode = value; 1350 break; 1351 case MMCBR_IVAR_VDD: 1352 slot->host.ios.vdd = value; 1353 break; 1354 case MMCBR_IVAR_TIMING: 1355 slot->host.ios.timing = value; 1356 break; 1357 case MMCBR_IVAR_CAPS: 1358 case MMCBR_IVAR_HOST_OCR: 1359 case MMCBR_IVAR_F_MIN: 1360 case MMCBR_IVAR_F_MAX: 1361 case MMCBR_IVAR_MAX_DATA: 1362 return (EINVAL); 1363 } 1364 return (0); 1365 } 1366 1367 MODULE_VERSION(sdhci, 1); 1368