1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level"); 59 60 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 61 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 62 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 63 #define RD_MULTI_4(slot, off, ptr, count) \ 64 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 65 66 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 67 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 68 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 69 #define WR_MULTI_4(slot, off, ptr, count) \ 70 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 71 72 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 73 static void sdhci_start(struct sdhci_slot *slot); 74 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 75 76 static void sdhci_card_task(void *, int); 77 78 /* helper routines */ 79 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 80 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 81 #define SDHCI_LOCK_INIT(_slot) \ 82 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 83 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 84 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 85 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 86 87 #define SDHCI_DEFAULT_MAX_FREQ 50 88 89 #define SDHCI_200_MAX_DIVIDER 256 90 #define SDHCI_300_MAX_DIVIDER 2046 91 92 static void 93 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 94 { 95 if (error != 0) { 96 printf("getaddr: error %d\n", error); 97 return; 98 } 99 *(bus_addr_t *)arg = segs[0].ds_addr; 100 } 101 102 static int 103 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 104 { 105 va_list ap; 106 int retval; 107 108 retval = printf("%s-slot%d: ", 109 device_get_nameunit(slot->bus), slot->num); 110 111 va_start(ap, fmt); 112 retval += vprintf(fmt, ap); 113 va_end(ap); 114 return (retval); 115 } 116 117 static void 118 sdhci_dumpregs(struct sdhci_slot *slot) 119 { 120 slot_printf(slot, 121 "============== REGISTER DUMP ==============\n"); 122 123 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 124 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 125 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 126 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 127 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 128 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 129 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 130 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 131 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 132 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 133 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 134 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 135 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 136 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 137 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 138 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 139 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 140 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 141 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 142 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 143 144 slot_printf(slot, 145 "===========================================\n"); 146 } 147 148 static void 149 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 150 { 151 int timeout; 152 153 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 154 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 155 SDHCI_CARD_PRESENT)) 156 return; 157 } 158 159 /* Some controllers need this kick or reset won't work. */ 160 if ((mask & SDHCI_RESET_ALL) == 0 && 161 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 162 uint32_t clock; 163 164 /* This is to force an update */ 165 clock = slot->clock; 166 slot->clock = 0; 167 sdhci_set_clock(slot, clock); 168 } 169 170 if (mask & SDHCI_RESET_ALL) { 171 slot->clock = 0; 172 slot->power = 0; 173 } 174 175 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 176 177 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 178 /* 179 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 180 * specification. The reset bit has internal propagation delay, 181 * so a fast read after write returns 0 even if reset process is 182 * in progress. The workaround is to poll for 1 before polling 183 * for 0. In the worst case, if we miss seeing it asserted the 184 * time we spent waiting is enough to ensure the reset finishes. 185 */ 186 timeout = 10000; 187 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 188 if (timeout <= 0) 189 break; 190 timeout--; 191 DELAY(1); 192 } 193 } 194 195 /* Wait max 100 ms */ 196 timeout = 10000; 197 /* Controller clears the bits when it's done */ 198 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 199 if (timeout <= 0) { 200 slot_printf(slot, "Reset 0x%x never completed.\n", 201 mask); 202 sdhci_dumpregs(slot); 203 return; 204 } 205 timeout--; 206 DELAY(10); 207 } 208 } 209 210 static void 211 sdhci_init(struct sdhci_slot *slot) 212 { 213 214 sdhci_reset(slot, SDHCI_RESET_ALL); 215 216 /* Enable interrupts. */ 217 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 218 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 219 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 220 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 221 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 222 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 223 SDHCI_INT_ACMD12ERR; 224 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 225 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 226 } 227 228 static void 229 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 230 { 231 uint32_t res; 232 uint16_t clk; 233 uint16_t div; 234 int timeout; 235 236 if (clock == slot->clock) 237 return; 238 slot->clock = clock; 239 240 /* Turn off the clock. */ 241 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 242 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 243 /* If no clock requested - left it so. */ 244 if (clock == 0) 245 return; 246 247 /* Recalculate timeout clock frequency based on the new sd clock. */ 248 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 249 slot->timeout_clk = slot->clock / 1000; 250 251 if (slot->version < SDHCI_SPEC_300) { 252 /* Looking for highest freq <= clock. */ 253 res = slot->max_clk; 254 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 255 if (res <= clock) 256 break; 257 res >>= 1; 258 } 259 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 260 div >>= 1; 261 } 262 else { 263 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 264 if (clock >= slot->max_clk) 265 div = 0; 266 else { 267 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 268 if ((slot->max_clk / div) <= clock) 269 break; 270 } 271 } 272 div >>= 1; 273 } 274 275 if (bootverbose || sdhci_debug) 276 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 277 div, clock, slot->max_clk); 278 279 /* Now we have got divider, set it. */ 280 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 281 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 282 << SDHCI_DIVIDER_HI_SHIFT; 283 284 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 285 /* Enable clock. */ 286 clk |= SDHCI_CLOCK_INT_EN; 287 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 288 /* Wait up to 10 ms until it stabilize. */ 289 timeout = 10; 290 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 291 & SDHCI_CLOCK_INT_STABLE)) { 292 if (timeout == 0) { 293 slot_printf(slot, 294 "Internal clock never stabilised.\n"); 295 sdhci_dumpregs(slot); 296 return; 297 } 298 timeout--; 299 DELAY(1000); 300 } 301 /* Pass clock signal to the bus. */ 302 clk |= SDHCI_CLOCK_CARD_EN; 303 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 304 } 305 306 static void 307 sdhci_set_power(struct sdhci_slot *slot, u_char power) 308 { 309 uint8_t pwr; 310 311 if (slot->power == power) 312 return; 313 314 slot->power = power; 315 316 /* Turn off the power. */ 317 pwr = 0; 318 WR1(slot, SDHCI_POWER_CONTROL, pwr); 319 /* If power down requested - left it so. */ 320 if (power == 0) 321 return; 322 /* Set voltage. */ 323 switch (1 << power) { 324 case MMC_OCR_LOW_VOLTAGE: 325 pwr |= SDHCI_POWER_180; 326 break; 327 case MMC_OCR_290_300: 328 case MMC_OCR_300_310: 329 pwr |= SDHCI_POWER_300; 330 break; 331 case MMC_OCR_320_330: 332 case MMC_OCR_330_340: 333 pwr |= SDHCI_POWER_330; 334 break; 335 } 336 WR1(slot, SDHCI_POWER_CONTROL, pwr); 337 /* Turn on the power. */ 338 pwr |= SDHCI_POWER_ON; 339 WR1(slot, SDHCI_POWER_CONTROL, pwr); 340 } 341 342 static void 343 sdhci_read_block_pio(struct sdhci_slot *slot) 344 { 345 uint32_t data; 346 char *buffer; 347 size_t left; 348 349 buffer = slot->curcmd->data->data; 350 buffer += slot->offset; 351 /* Transfer one block at a time. */ 352 left = min(512, slot->curcmd->data->len - slot->offset); 353 slot->offset += left; 354 355 /* If we are too fast, broken controllers return zeroes. */ 356 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 357 DELAY(10); 358 /* Handle unaligned and aligned buffer cases. */ 359 if ((intptr_t)buffer & 3) { 360 while (left > 3) { 361 data = RD4(slot, SDHCI_BUFFER); 362 buffer[0] = data; 363 buffer[1] = (data >> 8); 364 buffer[2] = (data >> 16); 365 buffer[3] = (data >> 24); 366 buffer += 4; 367 left -= 4; 368 } 369 } else { 370 RD_MULTI_4(slot, SDHCI_BUFFER, 371 (uint32_t *)buffer, left >> 2); 372 left &= 3; 373 } 374 /* Handle uneven size case. */ 375 if (left > 0) { 376 data = RD4(slot, SDHCI_BUFFER); 377 while (left > 0) { 378 *(buffer++) = data; 379 data >>= 8; 380 left--; 381 } 382 } 383 } 384 385 static void 386 sdhci_write_block_pio(struct sdhci_slot *slot) 387 { 388 uint32_t data = 0; 389 char *buffer; 390 size_t left; 391 392 buffer = slot->curcmd->data->data; 393 buffer += slot->offset; 394 /* Transfer one block at a time. */ 395 left = min(512, slot->curcmd->data->len - slot->offset); 396 slot->offset += left; 397 398 /* Handle unaligned and aligned buffer cases. */ 399 if ((intptr_t)buffer & 3) { 400 while (left > 3) { 401 data = buffer[0] + 402 (buffer[1] << 8) + 403 (buffer[2] << 16) + 404 (buffer[3] << 24); 405 left -= 4; 406 buffer += 4; 407 WR4(slot, SDHCI_BUFFER, data); 408 } 409 } else { 410 WR_MULTI_4(slot, SDHCI_BUFFER, 411 (uint32_t *)buffer, left >> 2); 412 left &= 3; 413 } 414 /* Handle uneven size case. */ 415 if (left > 0) { 416 while (left > 0) { 417 data <<= 8; 418 data += *(buffer++); 419 left--; 420 } 421 WR4(slot, SDHCI_BUFFER, data); 422 } 423 } 424 425 static void 426 sdhci_transfer_pio(struct sdhci_slot *slot) 427 { 428 429 /* Read as many blocks as possible. */ 430 if (slot->curcmd->data->flags & MMC_DATA_READ) { 431 while (RD4(slot, SDHCI_PRESENT_STATE) & 432 SDHCI_DATA_AVAILABLE) { 433 sdhci_read_block_pio(slot); 434 if (slot->offset >= slot->curcmd->data->len) 435 break; 436 } 437 } else { 438 while (RD4(slot, SDHCI_PRESENT_STATE) & 439 SDHCI_SPACE_AVAILABLE) { 440 sdhci_write_block_pio(slot); 441 if (slot->offset >= slot->curcmd->data->len) 442 break; 443 } 444 } 445 } 446 447 static void 448 sdhci_card_delay(void *arg) 449 { 450 struct sdhci_slot *slot = arg; 451 452 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 453 } 454 455 static void 456 sdhci_card_task(void *arg, int pending) 457 { 458 struct sdhci_slot *slot = arg; 459 460 SDHCI_LOCK(slot); 461 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 462 if (slot->dev == NULL) { 463 /* If card is present - attach mmc bus. */ 464 slot->dev = device_add_child(slot->bus, "mmc", -1); 465 device_set_ivars(slot->dev, slot); 466 SDHCI_UNLOCK(slot); 467 device_probe_and_attach(slot->dev); 468 } else 469 SDHCI_UNLOCK(slot); 470 } else { 471 if (slot->dev != NULL) { 472 /* If no card present - detach mmc bus. */ 473 device_t d = slot->dev; 474 slot->dev = NULL; 475 SDHCI_UNLOCK(slot); 476 device_delete_child(slot->bus, d); 477 } else 478 SDHCI_UNLOCK(slot); 479 } 480 } 481 482 int 483 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 484 { 485 uint32_t caps, freq; 486 int err; 487 488 SDHCI_LOCK_INIT(slot); 489 slot->num = num; 490 slot->bus = dev; 491 492 /* Allocate DMA tag. */ 493 err = bus_dma_tag_create(bus_get_dma_tag(dev), 494 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 495 BUS_SPACE_MAXADDR, NULL, NULL, 496 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 497 BUS_DMA_ALLOCNOW, NULL, NULL, 498 &slot->dmatag); 499 if (err != 0) { 500 device_printf(dev, "Can't create DMA tag\n"); 501 SDHCI_LOCK_DESTROY(slot); 502 return (err); 503 } 504 /* Allocate DMA memory. */ 505 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 506 BUS_DMA_NOWAIT, &slot->dmamap); 507 if (err != 0) { 508 device_printf(dev, "Can't alloc DMA memory\n"); 509 SDHCI_LOCK_DESTROY(slot); 510 return (err); 511 } 512 /* Map the memory. */ 513 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 514 (void *)slot->dmamem, DMA_BLOCK_SIZE, 515 sdhci_getaddr, &slot->paddr, 0); 516 if (err != 0 || slot->paddr == 0) { 517 device_printf(dev, "Can't load DMA memory\n"); 518 SDHCI_LOCK_DESTROY(slot); 519 if(err) 520 return (err); 521 else 522 return (EFAULT); 523 } 524 525 /* Initialize slot. */ 526 sdhci_init(slot); 527 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 528 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 529 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 530 caps = slot->caps; 531 else 532 caps = RD4(slot, SDHCI_CAPABILITIES); 533 /* Calculate base clock frequency. */ 534 if (slot->version >= SDHCI_SPEC_300) 535 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 536 SDHCI_CLOCK_BASE_SHIFT; 537 else 538 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 539 SDHCI_CLOCK_BASE_SHIFT; 540 if (freq != 0) 541 slot->max_clk = freq * 1000000; 542 /* 543 * If the frequency wasn't in the capabilities and the hardware driver 544 * hasn't already set max_clk we're probably not going to work right 545 * with an assumption, so complain about it. 546 */ 547 if (slot->max_clk == 0) { 548 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 549 device_printf(dev, "Hardware doesn't specify base clock " 550 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 551 } 552 /* Calculate timeout clock frequency. */ 553 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 554 slot->timeout_clk = slot->max_clk / 1000; 555 } else { 556 slot->timeout_clk = 557 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 558 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 559 slot->timeout_clk *= 1000; 560 } 561 /* 562 * If the frequency wasn't in the capabilities and the hardware driver 563 * hasn't already set timeout_clk we'll probably work okay using the 564 * max timeout, but still mention it. 565 */ 566 if (slot->timeout_clk == 0) { 567 device_printf(dev, "Hardware doesn't specify timeout clock " 568 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 569 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 570 } 571 572 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 573 slot->host.f_max = slot->max_clk; 574 slot->host.host_ocr = 0; 575 if (caps & SDHCI_CAN_VDD_330) 576 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 577 if (caps & SDHCI_CAN_VDD_300) 578 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 579 if (caps & SDHCI_CAN_VDD_180) 580 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 581 if (slot->host.host_ocr == 0) { 582 device_printf(dev, "Hardware doesn't report any " 583 "support voltages.\n"); 584 } 585 slot->host.caps = MMC_CAP_4_BIT_DATA; 586 if (caps & SDHCI_CAN_DO_HISPD) 587 slot->host.caps |= MMC_CAP_HSPEED; 588 /* Decide if we have usable DMA. */ 589 if (caps & SDHCI_CAN_DO_DMA) 590 slot->opt |= SDHCI_HAVE_DMA; 591 592 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 593 slot->opt &= ~SDHCI_HAVE_DMA; 594 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 595 slot->opt |= SDHCI_HAVE_DMA; 596 597 /* 598 * Use platform-provided transfer backend 599 * with PIO as a fallback mechanism 600 */ 601 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 602 slot->opt &= ~SDHCI_HAVE_DMA; 603 604 if (bootverbose || sdhci_debug) { 605 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 606 slot->max_clk / 1000000, 607 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 608 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 609 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 610 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 611 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 612 sdhci_dumpregs(slot); 613 } 614 615 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 616 callout_init(&slot->card_callout, 1); 617 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 618 return (0); 619 } 620 621 void 622 sdhci_start_slot(struct sdhci_slot *slot) 623 { 624 sdhci_card_task(slot, 0); 625 } 626 627 int 628 sdhci_cleanup_slot(struct sdhci_slot *slot) 629 { 630 device_t d; 631 632 callout_drain(&slot->timeout_callout); 633 callout_drain(&slot->card_callout); 634 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 635 636 SDHCI_LOCK(slot); 637 d = slot->dev; 638 slot->dev = NULL; 639 SDHCI_UNLOCK(slot); 640 if (d != NULL) 641 device_delete_child(slot->bus, d); 642 643 SDHCI_LOCK(slot); 644 sdhci_reset(slot, SDHCI_RESET_ALL); 645 SDHCI_UNLOCK(slot); 646 bus_dmamap_unload(slot->dmatag, slot->dmamap); 647 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 648 bus_dma_tag_destroy(slot->dmatag); 649 650 SDHCI_LOCK_DESTROY(slot); 651 652 return (0); 653 } 654 655 int 656 sdhci_generic_suspend(struct sdhci_slot *slot) 657 { 658 sdhci_reset(slot, SDHCI_RESET_ALL); 659 660 return (0); 661 } 662 663 int 664 sdhci_generic_resume(struct sdhci_slot *slot) 665 { 666 sdhci_init(slot); 667 668 return (0); 669 } 670 671 uint32_t 672 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 673 { 674 if (slot->version >= SDHCI_SPEC_300) 675 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 676 else 677 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 678 } 679 680 int 681 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 682 { 683 struct sdhci_slot *slot = device_get_ivars(reqdev); 684 struct mmc_ios *ios = &slot->host.ios; 685 686 SDHCI_LOCK(slot); 687 /* Do full reset on bus power down to clear from any state. */ 688 if (ios->power_mode == power_off) { 689 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 690 sdhci_init(slot); 691 } 692 /* Configure the bus. */ 693 sdhci_set_clock(slot, ios->clock); 694 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 695 if (ios->bus_width == bus_width_4) 696 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 697 else 698 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 699 if (ios->timing == bus_timing_hs) 700 slot->hostctrl |= SDHCI_CTRL_HISPD; 701 else 702 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 703 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 704 /* Some controllers like reset after bus changes. */ 705 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 706 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 707 708 SDHCI_UNLOCK(slot); 709 return (0); 710 } 711 712 static void 713 sdhci_req_done(struct sdhci_slot *slot) 714 { 715 struct mmc_request *req; 716 717 if (slot->req != NULL && slot->curcmd != NULL) { 718 callout_stop(&slot->timeout_callout); 719 req = slot->req; 720 slot->req = NULL; 721 slot->curcmd = NULL; 722 req->done(req); 723 } 724 } 725 726 static void 727 sdhci_timeout(void *arg) 728 { 729 struct sdhci_slot *slot = arg; 730 731 if (slot->curcmd != NULL) { 732 slot_printf(slot, " Controller timeout\n"); 733 sdhci_dumpregs(slot); 734 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 735 slot->curcmd->error = MMC_ERR_TIMEOUT; 736 sdhci_req_done(slot); 737 } else { 738 slot_printf(slot, " Spurious timeout - no active command\n"); 739 } 740 } 741 742 static void 743 sdhci_set_transfer_mode(struct sdhci_slot *slot, 744 struct mmc_data *data) 745 { 746 uint16_t mode; 747 748 if (data == NULL) 749 return; 750 751 mode = SDHCI_TRNS_BLK_CNT_EN; 752 if (data->len > 512) 753 mode |= SDHCI_TRNS_MULTI; 754 if (data->flags & MMC_DATA_READ) 755 mode |= SDHCI_TRNS_READ; 756 if (slot->req->stop) 757 mode |= SDHCI_TRNS_ACMD12; 758 if (slot->flags & SDHCI_USE_DMA) 759 mode |= SDHCI_TRNS_DMA; 760 761 WR2(slot, SDHCI_TRANSFER_MODE, mode); 762 } 763 764 static void 765 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 766 { 767 int flags, timeout; 768 uint32_t mask, state; 769 770 slot->curcmd = cmd; 771 slot->cmd_done = 0; 772 773 cmd->error = MMC_ERR_NONE; 774 775 /* This flags combination is not supported by controller. */ 776 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 777 slot_printf(slot, "Unsupported response type!\n"); 778 cmd->error = MMC_ERR_FAILED; 779 sdhci_req_done(slot); 780 return; 781 } 782 783 /* Read controller present state. */ 784 state = RD4(slot, SDHCI_PRESENT_STATE); 785 /* Do not issue command if there is no card, clock or power. 786 * Controller will not detect timeout without clock active. */ 787 if ((state & SDHCI_CARD_PRESENT) == 0 || 788 slot->power == 0 || 789 slot->clock == 0) { 790 cmd->error = MMC_ERR_FAILED; 791 sdhci_req_done(slot); 792 return; 793 } 794 /* Always wait for free CMD bus. */ 795 mask = SDHCI_CMD_INHIBIT; 796 /* Wait for free DAT if we have data or busy signal. */ 797 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 798 mask |= SDHCI_DAT_INHIBIT; 799 /* We shouldn't wait for DAT for stop commands. */ 800 if (cmd == slot->req->stop) 801 mask &= ~SDHCI_DAT_INHIBIT; 802 /* 803 * Wait for bus no more then 250 ms. Typically there will be no wait 804 * here at all, but when writing a crash dump we may be bypassing the 805 * host platform's interrupt handler, and in some cases that handler 806 * may be working around hardware quirks such as not respecting r1b 807 * busy indications. In those cases, this wait-loop serves the purpose 808 * of waiting for the prior command and data transfers to be done, and 809 * SD cards are allowed to take up to 250ms for write and erase ops. 810 * (It's usually more like 20-30ms in the real world.) 811 */ 812 timeout = 250; 813 while (state & mask) { 814 if (timeout == 0) { 815 slot_printf(slot, "Controller never released " 816 "inhibit bit(s).\n"); 817 sdhci_dumpregs(slot); 818 cmd->error = MMC_ERR_FAILED; 819 sdhci_req_done(slot); 820 return; 821 } 822 timeout--; 823 DELAY(1000); 824 state = RD4(slot, SDHCI_PRESENT_STATE); 825 } 826 827 /* Prepare command flags. */ 828 if (!(cmd->flags & MMC_RSP_PRESENT)) 829 flags = SDHCI_CMD_RESP_NONE; 830 else if (cmd->flags & MMC_RSP_136) 831 flags = SDHCI_CMD_RESP_LONG; 832 else if (cmd->flags & MMC_RSP_BUSY) 833 flags = SDHCI_CMD_RESP_SHORT_BUSY; 834 else 835 flags = SDHCI_CMD_RESP_SHORT; 836 if (cmd->flags & MMC_RSP_CRC) 837 flags |= SDHCI_CMD_CRC; 838 if (cmd->flags & MMC_RSP_OPCODE) 839 flags |= SDHCI_CMD_INDEX; 840 if (cmd->data) 841 flags |= SDHCI_CMD_DATA; 842 if (cmd->opcode == MMC_STOP_TRANSMISSION) 843 flags |= SDHCI_CMD_TYPE_ABORT; 844 /* Prepare data. */ 845 sdhci_start_data(slot, cmd->data); 846 /* 847 * Interrupt aggregation: To reduce total number of interrupts 848 * group response interrupt with data interrupt when possible. 849 * If there going to be data interrupt, mask response one. 850 */ 851 if (slot->data_done == 0) { 852 WR4(slot, SDHCI_SIGNAL_ENABLE, 853 slot->intmask &= ~SDHCI_INT_RESPONSE); 854 } 855 /* Set command argument. */ 856 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 857 /* Set data transfer mode. */ 858 sdhci_set_transfer_mode(slot, cmd->data); 859 /* Start command. */ 860 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 861 /* Start timeout callout. */ 862 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot); 863 } 864 865 static void 866 sdhci_finish_command(struct sdhci_slot *slot) 867 { 868 int i; 869 870 slot->cmd_done = 1; 871 /* Interrupt aggregation: Restore command interrupt. 872 * Main restore point for the case when command interrupt 873 * happened first. */ 874 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 875 /* In case of error - reset host and return. */ 876 if (slot->curcmd->error) { 877 sdhci_reset(slot, SDHCI_RESET_CMD); 878 sdhci_reset(slot, SDHCI_RESET_DATA); 879 sdhci_start(slot); 880 return; 881 } 882 /* If command has response - fetch it. */ 883 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 884 if (slot->curcmd->flags & MMC_RSP_136) { 885 /* CRC is stripped so we need one byte shift. */ 886 uint8_t extra = 0; 887 for (i = 0; i < 4; i++) { 888 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 889 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 890 slot->curcmd->resp[3 - i] = val; 891 else { 892 slot->curcmd->resp[3 - i] = 893 (val << 8) | extra; 894 extra = val >> 24; 895 } 896 } 897 } else 898 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 899 } 900 /* If data ready - finish. */ 901 if (slot->data_done) 902 sdhci_start(slot); 903 } 904 905 static void 906 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 907 { 908 uint32_t target_timeout, current_timeout; 909 uint8_t div; 910 911 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 912 slot->data_done = 1; 913 return; 914 } 915 916 slot->data_done = 0; 917 918 /* Calculate and set data timeout.*/ 919 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 920 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 921 div = 0xE; 922 } else { 923 target_timeout = 1000000; 924 div = 0; 925 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 926 while (current_timeout < target_timeout && div < 0xE) { 927 ++div; 928 current_timeout <<= 1; 929 } 930 /* Compensate for an off-by-one error in the CaFe chip.*/ 931 if (div < 0xE && 932 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 933 ++div; 934 } 935 } 936 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 937 938 if (data == NULL) 939 return; 940 941 /* Use DMA if possible. */ 942 if ((slot->opt & SDHCI_HAVE_DMA)) 943 slot->flags |= SDHCI_USE_DMA; 944 /* If data is small, broken DMA may return zeroes instead of data, */ 945 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 946 (data->len <= 512)) 947 slot->flags &= ~SDHCI_USE_DMA; 948 /* Some controllers require even block sizes. */ 949 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 950 ((data->len) & 0x3)) 951 slot->flags &= ~SDHCI_USE_DMA; 952 /* Load DMA buffer. */ 953 if (slot->flags & SDHCI_USE_DMA) { 954 if (data->flags & MMC_DATA_READ) 955 bus_dmamap_sync(slot->dmatag, slot->dmamap, 956 BUS_DMASYNC_PREREAD); 957 else { 958 memcpy(slot->dmamem, data->data, 959 (data->len < DMA_BLOCK_SIZE) ? 960 data->len : DMA_BLOCK_SIZE); 961 bus_dmamap_sync(slot->dmatag, slot->dmamap, 962 BUS_DMASYNC_PREWRITE); 963 } 964 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 965 /* Interrupt aggregation: Mask border interrupt 966 * for the last page and unmask else. */ 967 if (data->len == DMA_BLOCK_SIZE) 968 slot->intmask &= ~SDHCI_INT_DMA_END; 969 else 970 slot->intmask |= SDHCI_INT_DMA_END; 971 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 972 } 973 /* Current data offset for both PIO and DMA. */ 974 slot->offset = 0; 975 /* Set block size and request IRQ on 4K border. */ 976 WR2(slot, SDHCI_BLOCK_SIZE, 977 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 978 /* Set block count. */ 979 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 980 } 981 982 void 983 sdhci_finish_data(struct sdhci_slot *slot) 984 { 985 struct mmc_data *data = slot->curcmd->data; 986 987 slot->data_done = 1; 988 /* Interrupt aggregation: Restore command interrupt. 989 * Auxiliary restore point for the case when data interrupt 990 * happened first. */ 991 if (!slot->cmd_done) { 992 WR4(slot, SDHCI_SIGNAL_ENABLE, 993 slot->intmask |= SDHCI_INT_RESPONSE); 994 } 995 /* Unload rest of data from DMA buffer. */ 996 if (slot->flags & SDHCI_USE_DMA) { 997 if (data->flags & MMC_DATA_READ) { 998 size_t left = data->len - slot->offset; 999 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1000 BUS_DMASYNC_POSTREAD); 1001 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1002 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1003 } else 1004 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1005 BUS_DMASYNC_POSTWRITE); 1006 } 1007 /* If there was error - reset the host. */ 1008 if (slot->curcmd->error) { 1009 sdhci_reset(slot, SDHCI_RESET_CMD); 1010 sdhci_reset(slot, SDHCI_RESET_DATA); 1011 sdhci_start(slot); 1012 return; 1013 } 1014 /* If we already have command response - finish. */ 1015 if (slot->cmd_done) 1016 sdhci_start(slot); 1017 } 1018 1019 static void 1020 sdhci_start(struct sdhci_slot *slot) 1021 { 1022 struct mmc_request *req; 1023 1024 req = slot->req; 1025 if (req == NULL) 1026 return; 1027 1028 if (!(slot->flags & CMD_STARTED)) { 1029 slot->flags |= CMD_STARTED; 1030 sdhci_start_command(slot, req->cmd); 1031 return; 1032 } 1033 /* We don't need this until using Auto-CMD12 feature 1034 if (!(slot->flags & STOP_STARTED) && req->stop) { 1035 slot->flags |= STOP_STARTED; 1036 sdhci_start_command(slot, req->stop); 1037 return; 1038 } 1039 */ 1040 if (sdhci_debug > 1) 1041 slot_printf(slot, "result: %d\n", req->cmd->error); 1042 if (!req->cmd->error && 1043 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1044 sdhci_reset(slot, SDHCI_RESET_CMD); 1045 sdhci_reset(slot, SDHCI_RESET_DATA); 1046 } 1047 1048 sdhci_req_done(slot); 1049 } 1050 1051 int 1052 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1053 { 1054 struct sdhci_slot *slot = device_get_ivars(reqdev); 1055 1056 SDHCI_LOCK(slot); 1057 if (slot->req != NULL) { 1058 SDHCI_UNLOCK(slot); 1059 return (EBUSY); 1060 } 1061 if (sdhci_debug > 1) { 1062 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1063 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1064 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1065 (req->cmd->data)?req->cmd->data->flags:0); 1066 } 1067 slot->req = req; 1068 slot->flags = 0; 1069 sdhci_start(slot); 1070 SDHCI_UNLOCK(slot); 1071 if (dumping) { 1072 while (slot->req != NULL) { 1073 sdhci_generic_intr(slot); 1074 DELAY(10); 1075 } 1076 } 1077 return (0); 1078 } 1079 1080 int 1081 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1082 { 1083 struct sdhci_slot *slot = device_get_ivars(reqdev); 1084 uint32_t val; 1085 1086 SDHCI_LOCK(slot); 1087 val = RD4(slot, SDHCI_PRESENT_STATE); 1088 SDHCI_UNLOCK(slot); 1089 return (!(val & SDHCI_WRITE_PROTECT)); 1090 } 1091 1092 int 1093 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1094 { 1095 struct sdhci_slot *slot = device_get_ivars(reqdev); 1096 int err = 0; 1097 1098 SDHCI_LOCK(slot); 1099 while (slot->bus_busy) 1100 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1101 slot->bus_busy++; 1102 /* Activate led. */ 1103 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1104 SDHCI_UNLOCK(slot); 1105 return (err); 1106 } 1107 1108 int 1109 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1110 { 1111 struct sdhci_slot *slot = device_get_ivars(reqdev); 1112 1113 SDHCI_LOCK(slot); 1114 /* Deactivate led. */ 1115 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1116 slot->bus_busy--; 1117 SDHCI_UNLOCK(slot); 1118 wakeup(slot); 1119 return (0); 1120 } 1121 1122 static void 1123 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1124 { 1125 1126 if (!slot->curcmd) { 1127 slot_printf(slot, "Got command interrupt 0x%08x, but " 1128 "there is no active command.\n", intmask); 1129 sdhci_dumpregs(slot); 1130 return; 1131 } 1132 if (intmask & SDHCI_INT_TIMEOUT) 1133 slot->curcmd->error = MMC_ERR_TIMEOUT; 1134 else if (intmask & SDHCI_INT_CRC) 1135 slot->curcmd->error = MMC_ERR_BADCRC; 1136 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1137 slot->curcmd->error = MMC_ERR_FIFO; 1138 1139 sdhci_finish_command(slot); 1140 } 1141 1142 static void 1143 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1144 { 1145 1146 if (!slot->curcmd) { 1147 slot_printf(slot, "Got data interrupt 0x%08x, but " 1148 "there is no active command.\n", intmask); 1149 sdhci_dumpregs(slot); 1150 return; 1151 } 1152 if (slot->curcmd->data == NULL && 1153 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1154 slot_printf(slot, "Got data interrupt 0x%08x, but " 1155 "there is no active data operation.\n", 1156 intmask); 1157 sdhci_dumpregs(slot); 1158 return; 1159 } 1160 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1161 slot->curcmd->error = MMC_ERR_TIMEOUT; 1162 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1163 slot->curcmd->error = MMC_ERR_BADCRC; 1164 if (slot->curcmd->data == NULL && 1165 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1166 SDHCI_INT_DMA_END))) { 1167 slot_printf(slot, "Got data interrupt 0x%08x, but " 1168 "there is busy-only command.\n", intmask); 1169 sdhci_dumpregs(slot); 1170 slot->curcmd->error = MMC_ERR_INVALID; 1171 } 1172 if (slot->curcmd->error) { 1173 /* No need to continue after any error. */ 1174 if (slot->flags & PLATFORM_DATA_STARTED) { 1175 slot->flags &= ~PLATFORM_DATA_STARTED; 1176 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1177 } else 1178 sdhci_finish_data(slot); 1179 return; 1180 } 1181 1182 /* Handle PIO interrupt. */ 1183 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1184 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1185 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1186 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1187 slot->flags |= PLATFORM_DATA_STARTED; 1188 } else 1189 sdhci_transfer_pio(slot); 1190 } 1191 /* Handle DMA border. */ 1192 if (intmask & SDHCI_INT_DMA_END) { 1193 struct mmc_data *data = slot->curcmd->data; 1194 size_t left; 1195 1196 /* Unload DMA buffer... */ 1197 left = data->len - slot->offset; 1198 if (data->flags & MMC_DATA_READ) { 1199 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1200 BUS_DMASYNC_POSTREAD); 1201 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1202 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1203 } else { 1204 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1205 BUS_DMASYNC_POSTWRITE); 1206 } 1207 /* ... and reload it again. */ 1208 slot->offset += DMA_BLOCK_SIZE; 1209 left = data->len - slot->offset; 1210 if (data->flags & MMC_DATA_READ) { 1211 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1212 BUS_DMASYNC_PREREAD); 1213 } else { 1214 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1215 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1216 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1217 BUS_DMASYNC_PREWRITE); 1218 } 1219 /* Interrupt aggregation: Mask border interrupt 1220 * for the last page. */ 1221 if (left == DMA_BLOCK_SIZE) { 1222 slot->intmask &= ~SDHCI_INT_DMA_END; 1223 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1224 } 1225 /* Restart DMA. */ 1226 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1227 } 1228 /* We have got all data. */ 1229 if (intmask & SDHCI_INT_DATA_END) { 1230 if (slot->flags & PLATFORM_DATA_STARTED) { 1231 slot->flags &= ~PLATFORM_DATA_STARTED; 1232 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1233 } else 1234 sdhci_finish_data(slot); 1235 } 1236 } 1237 1238 static void 1239 sdhci_acmd_irq(struct sdhci_slot *slot) 1240 { 1241 uint16_t err; 1242 1243 err = RD4(slot, SDHCI_ACMD12_ERR); 1244 if (!slot->curcmd) { 1245 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1246 "there is no active command.\n", err); 1247 sdhci_dumpregs(slot); 1248 return; 1249 } 1250 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1251 sdhci_reset(slot, SDHCI_RESET_CMD); 1252 } 1253 1254 void 1255 sdhci_generic_intr(struct sdhci_slot *slot) 1256 { 1257 uint32_t intmask; 1258 1259 SDHCI_LOCK(slot); 1260 /* Read slot interrupt status. */ 1261 intmask = RD4(slot, SDHCI_INT_STATUS); 1262 if (intmask == 0 || intmask == 0xffffffff) { 1263 SDHCI_UNLOCK(slot); 1264 return; 1265 } 1266 if (sdhci_debug > 2) 1267 slot_printf(slot, "Interrupt %#x\n", intmask); 1268 1269 /* Handle card presence interrupts. */ 1270 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1271 WR4(slot, SDHCI_INT_STATUS, intmask & 1272 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1273 1274 if (intmask & SDHCI_INT_CARD_REMOVE) { 1275 if (bootverbose || sdhci_debug) 1276 slot_printf(slot, "Card removed\n"); 1277 callout_stop(&slot->card_callout); 1278 taskqueue_enqueue(taskqueue_swi_giant, 1279 &slot->card_task); 1280 } 1281 if (intmask & SDHCI_INT_CARD_INSERT) { 1282 if (bootverbose || sdhci_debug) 1283 slot_printf(slot, "Card inserted\n"); 1284 callout_reset(&slot->card_callout, hz / 2, 1285 sdhci_card_delay, slot); 1286 } 1287 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1288 } 1289 /* Handle command interrupts. */ 1290 if (intmask & SDHCI_INT_CMD_MASK) { 1291 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1292 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1293 } 1294 /* Handle data interrupts. */ 1295 if (intmask & SDHCI_INT_DATA_MASK) { 1296 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1297 /* Dont call data_irq in case of errored command */ 1298 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1299 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1300 } 1301 /* Handle AutoCMD12 error interrupt. */ 1302 if (intmask & SDHCI_INT_ACMD12ERR) { 1303 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1304 sdhci_acmd_irq(slot); 1305 } 1306 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1307 intmask &= ~SDHCI_INT_ACMD12ERR; 1308 intmask &= ~SDHCI_INT_ERROR; 1309 /* Handle bus power interrupt. */ 1310 if (intmask & SDHCI_INT_BUS_POWER) { 1311 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1312 slot_printf(slot, 1313 "Card is consuming too much power!\n"); 1314 intmask &= ~SDHCI_INT_BUS_POWER; 1315 } 1316 /* The rest is unknown. */ 1317 if (intmask) { 1318 WR4(slot, SDHCI_INT_STATUS, intmask); 1319 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1320 intmask); 1321 sdhci_dumpregs(slot); 1322 } 1323 1324 SDHCI_UNLOCK(slot); 1325 } 1326 1327 int 1328 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1329 { 1330 struct sdhci_slot *slot = device_get_ivars(child); 1331 1332 switch (which) { 1333 default: 1334 return (EINVAL); 1335 case MMCBR_IVAR_BUS_MODE: 1336 *result = slot->host.ios.bus_mode; 1337 break; 1338 case MMCBR_IVAR_BUS_WIDTH: 1339 *result = slot->host.ios.bus_width; 1340 break; 1341 case MMCBR_IVAR_CHIP_SELECT: 1342 *result = slot->host.ios.chip_select; 1343 break; 1344 case MMCBR_IVAR_CLOCK: 1345 *result = slot->host.ios.clock; 1346 break; 1347 case MMCBR_IVAR_F_MIN: 1348 *result = slot->host.f_min; 1349 break; 1350 case MMCBR_IVAR_F_MAX: 1351 *result = slot->host.f_max; 1352 break; 1353 case MMCBR_IVAR_HOST_OCR: 1354 *result = slot->host.host_ocr; 1355 break; 1356 case MMCBR_IVAR_MODE: 1357 *result = slot->host.mode; 1358 break; 1359 case MMCBR_IVAR_OCR: 1360 *result = slot->host.ocr; 1361 break; 1362 case MMCBR_IVAR_POWER_MODE: 1363 *result = slot->host.ios.power_mode; 1364 break; 1365 case MMCBR_IVAR_VDD: 1366 *result = slot->host.ios.vdd; 1367 break; 1368 case MMCBR_IVAR_CAPS: 1369 *result = slot->host.caps; 1370 break; 1371 case MMCBR_IVAR_TIMING: 1372 *result = slot->host.ios.timing; 1373 break; 1374 case MMCBR_IVAR_MAX_DATA: 1375 *result = 65535; 1376 break; 1377 } 1378 return (0); 1379 } 1380 1381 int 1382 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1383 { 1384 struct sdhci_slot *slot = device_get_ivars(child); 1385 1386 switch (which) { 1387 default: 1388 return (EINVAL); 1389 case MMCBR_IVAR_BUS_MODE: 1390 slot->host.ios.bus_mode = value; 1391 break; 1392 case MMCBR_IVAR_BUS_WIDTH: 1393 slot->host.ios.bus_width = value; 1394 break; 1395 case MMCBR_IVAR_CHIP_SELECT: 1396 slot->host.ios.chip_select = value; 1397 break; 1398 case MMCBR_IVAR_CLOCK: 1399 if (value > 0) { 1400 uint32_t max_clock; 1401 uint32_t clock; 1402 int i; 1403 1404 max_clock = slot->max_clk; 1405 clock = max_clock; 1406 1407 if (slot->version < SDHCI_SPEC_300) { 1408 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1409 i <<= 1) { 1410 if (clock <= value) 1411 break; 1412 clock >>= 1; 1413 } 1414 } 1415 else { 1416 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1417 i += 2) { 1418 if (clock <= value) 1419 break; 1420 clock = max_clock / (i + 2); 1421 } 1422 } 1423 1424 slot->host.ios.clock = clock; 1425 } else 1426 slot->host.ios.clock = 0; 1427 break; 1428 case MMCBR_IVAR_MODE: 1429 slot->host.mode = value; 1430 break; 1431 case MMCBR_IVAR_OCR: 1432 slot->host.ocr = value; 1433 break; 1434 case MMCBR_IVAR_POWER_MODE: 1435 slot->host.ios.power_mode = value; 1436 break; 1437 case MMCBR_IVAR_VDD: 1438 slot->host.ios.vdd = value; 1439 break; 1440 case MMCBR_IVAR_TIMING: 1441 slot->host.ios.timing = value; 1442 break; 1443 case MMCBR_IVAR_CAPS: 1444 case MMCBR_IVAR_HOST_OCR: 1445 case MMCBR_IVAR_F_MIN: 1446 case MMCBR_IVAR_F_MAX: 1447 case MMCBR_IVAR_MAX_DATA: 1448 return (EINVAL); 1449 } 1450 return (0); 1451 } 1452 1453 MODULE_VERSION(sdhci, 1); 1454