1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/kobj.h> 39 #include <sys/libkern.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/resource.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 #include <sys/sbuf.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/stdarg.h> 53 54 #include <dev/mmc/bridge.h> 55 #include <dev/mmc/mmcreg.h> 56 #include <dev/mmc/mmcbrvar.h> 57 58 #include <dev/sdhci/sdhci.h> 59 60 #include <cam/cam.h> 61 #include <cam/cam_ccb.h> 62 #include <cam/cam_debug.h> 63 #include <cam/cam_sim.h> 64 #include <cam/cam_xpt_sim.h> 65 66 #include "mmcbr_if.h" 67 #include "sdhci_if.h" 68 69 #include "opt_mmccam.h" 70 71 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 72 "sdhci driver"); 73 74 static int sdhci_debug = 0; 75 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 76 "Debug level"); 77 u_int sdhci_quirk_clear = 0; 78 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 79 0, "Mask of quirks to clear"); 80 u_int sdhci_quirk_set = 0; 81 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 82 "Mask of quirks to set"); 83 84 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 85 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 86 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 87 #define RD_MULTI_4(slot, off, ptr, count) \ 88 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 89 90 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 91 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 92 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 93 #define WR_MULTI_4(slot, off, ptr, count) \ 94 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 95 96 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err); 97 static void sdhci_card_poll(void *arg); 98 static void sdhci_card_task(void *arg, int pending); 99 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask); 100 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask); 101 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 102 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot, 103 bool is_present); 104 static void sdhci_finish_command(struct sdhci_slot *slot); 105 static void sdhci_init(struct sdhci_slot *slot); 106 static void sdhci_read_block_pio(struct sdhci_slot *slot); 107 static void sdhci_req_done(struct sdhci_slot *slot); 108 static void sdhci_req_wakeup(struct mmc_request *req); 109 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask); 110 static void sdhci_retune(void *arg); 111 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 112 static void sdhci_set_power(struct sdhci_slot *slot, u_char power); 113 static void sdhci_set_transfer_mode(struct sdhci_slot *slot, 114 const struct mmc_data *data); 115 static void sdhci_start(struct sdhci_slot *slot); 116 static void sdhci_timeout(void *arg); 117 static void sdhci_start_command(struct sdhci_slot *slot, 118 struct mmc_command *cmd); 119 static void sdhci_start_data(struct sdhci_slot *slot, 120 const struct mmc_data *data); 121 static void sdhci_write_block_pio(struct sdhci_slot *slot); 122 static void sdhci_transfer_pio(struct sdhci_slot *slot); 123 124 #ifdef MMCCAM 125 /* CAM-related */ 126 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 127 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 128 int proposed_clock); 129 static void sdhci_cam_poll(struct cam_sim *sim); 130 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 131 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 132 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 133 #endif 134 135 /* helper routines */ 136 static int sdhci_dma_alloc(struct sdhci_slot *slot, uint32_t caps); 137 static void sdhci_dma_free(struct sdhci_slot *slot); 138 static void sdhci_dumpcaps(struct sdhci_slot *slot); 139 static void sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s); 140 static void sdhci_dumpregs(struct sdhci_slot *slot); 141 static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s); 142 static int sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS); 143 static int sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS); 144 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 145 int error); 146 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 147 __printflike(2, 3); 148 static int slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s, 149 const char * fmt, ...) __printflike(3, 4); 150 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot); 151 152 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 153 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 154 #define SDHCI_LOCK_INIT(_slot) \ 155 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 156 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 157 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 158 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 159 160 #define SDHCI_DEFAULT_MAX_FREQ 50 161 162 #define SDHCI_200_MAX_DIVIDER 256 163 #define SDHCI_300_MAX_DIVIDER 2046 164 165 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 166 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 167 168 /* 169 * Broadcom BCM577xx Controller Constants 170 */ 171 /* Maximum divider supported by the default clock source. */ 172 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 173 /* Alternative clock's base frequency. */ 174 #define BCM577XX_ALT_CLOCK_BASE 63000000 175 176 #define BCM577XX_HOST_CONTROL 0x198 177 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 178 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 179 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 180 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 181 182 static void 183 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 184 { 185 186 if (error != 0) { 187 printf("getaddr: error %d\n", error); 188 return; 189 } 190 *(bus_addr_t *)arg = segs[0].ds_addr; 191 } 192 193 static int 194 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 195 { 196 char buf[128]; 197 va_list ap; 198 int retval; 199 200 /* 201 * Make sure we print a single line all together rather than in two 202 * halves to avoid console gibberish bingo. 203 */ 204 va_start(ap, fmt); 205 retval = vsnprintf(buf, sizeof(buf), fmt, ap); 206 va_end(ap); 207 208 retval += printf("%s-slot%d: %s", 209 device_get_nameunit(slot->bus), slot->num, buf); 210 return (retval); 211 } 212 213 static int 214 slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s, 215 const char * fmt, ...) 216 { 217 va_list ap; 218 int retval; 219 220 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num); 221 222 va_start(ap, fmt); 223 retval += sbuf_vprintf(s, fmt, ap); 224 va_end(ap); 225 226 return (retval); 227 } 228 229 static void 230 sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s) 231 { 232 slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n"); 233 234 slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n", 235 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 236 slot_sprintf(slot, s, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 237 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 238 slot_sprintf(slot, s, "Argument: 0x%08x | Trn mode: 0x%08x\n", 239 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 240 slot_sprintf(slot, s, "Present: 0x%08x | Host ctl: 0x%08x\n", 241 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 242 slot_sprintf(slot, s, "Power: 0x%08x | Blk gap: 0x%08x\n", 243 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 244 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n", 245 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 246 slot_sprintf(slot, s, "Timeout: 0x%08x | Int stat: 0x%08x\n", 247 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 248 slot_sprintf(slot, s, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 249 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 250 slot_sprintf(slot, s, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 251 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 252 slot_sprintf(slot, s, "Caps: 0x%08x | Caps2: 0x%08x\n", 253 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 254 slot_sprintf(slot, s, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 255 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 256 slot_sprintf(slot, s, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 257 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 258 259 slot_sprintf(slot, s, "===========================================\n"); 260 } 261 262 static void 263 sdhci_dumpregs(struct sdhci_slot *slot) 264 { 265 struct sbuf s; 266 267 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) { 268 slot_printf(slot, "sdhci_dumpregs: Failed to allocate memory for sbuf\n"); 269 return; 270 } 271 272 sbuf_set_drain(&s, &sbuf_printf_drain, NULL); 273 sdhci_dumpregs_buf(slot, &s); 274 sbuf_finish(&s); 275 sbuf_delete(&s); 276 } 277 278 static int 279 sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS) 280 { 281 struct sdhci_slot *slot = arg1; 282 struct sbuf s; 283 284 sbuf_new_for_sysctl(&s, NULL, 1024, req); 285 sbuf_putc(&s, '\n'); 286 sdhci_dumpregs_buf(slot, &s); 287 sbuf_finish(&s); 288 sbuf_delete(&s); 289 290 return (0); 291 } 292 293 static void 294 sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s) 295 { 296 int host_caps = slot->host.caps; 297 int caps = slot->caps; 298 299 slot_sprintf(slot, s, 300 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 301 slot->max_clk / 1000000, 302 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 303 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 304 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 305 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 306 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 307 ((caps & SDHCI_CAN_VDD_180) && 308 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 309 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 310 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 311 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 312 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 313 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 314 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 315 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 316 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 317 "removable"); 318 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 319 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 320 slot_sprintf(slot, s, "eMMC:%s%s%s%s\n", 321 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 322 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 323 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 324 ((host_caps & 325 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 326 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 327 " HS400ES" : ""); 328 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 329 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 330 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n", 331 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 332 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 333 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 334 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 335 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 336 if (slot->opt & SDHCI_TUNING_SUPPORTED) 337 slot_sprintf(slot, s, 338 "Re-tuning count %d secs, mode %d\n", 339 slot->retune_count, slot->retune_mode + 1); 340 } 341 342 static void 343 sdhci_dumpcaps(struct sdhci_slot *slot) 344 { 345 struct sbuf s; 346 347 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) { 348 slot_printf(slot, "sdhci_dumpcaps: Failed to allocate memory for sbuf\n"); 349 return; 350 } 351 352 sbuf_set_drain(&s, &sbuf_printf_drain, NULL); 353 sdhci_dumpcaps_buf(slot, &s); 354 sbuf_finish(&s); 355 sbuf_delete(&s); 356 } 357 358 static int 359 sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS) 360 { 361 struct sdhci_slot *slot = arg1; 362 struct sbuf s; 363 364 sbuf_new_for_sysctl(&s, NULL, 1024, req); 365 sbuf_putc(&s, '\n'); 366 sdhci_dumpcaps_buf(slot, &s); 367 sbuf_finish(&s); 368 sbuf_delete(&s); 369 370 return (0); 371 } 372 373 static void 374 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 375 { 376 int timeout; 377 uint32_t clock; 378 379 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 380 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 381 return; 382 } 383 384 /* Some controllers need this kick or reset won't work. */ 385 if ((mask & SDHCI_RESET_ALL) == 0 && 386 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 387 /* This is to force an update */ 388 clock = slot->clock; 389 slot->clock = 0; 390 sdhci_set_clock(slot, clock); 391 } 392 393 if (mask & SDHCI_RESET_ALL) { 394 slot->clock = 0; 395 slot->power = 0; 396 } 397 398 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 399 400 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 401 /* 402 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 403 * specification. The reset bit has internal propagation delay, 404 * so a fast read after write returns 0 even if reset process is 405 * in progress. The workaround is to poll for 1 before polling 406 * for 0. In the worst case, if we miss seeing it asserted the 407 * time we spent waiting is enough to ensure the reset finishes. 408 */ 409 timeout = 10000; 410 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 411 if (timeout <= 0) 412 break; 413 timeout--; 414 DELAY(1); 415 } 416 } 417 418 /* Wait max 100 ms */ 419 timeout = 10000; 420 /* Controller clears the bits when it's done */ 421 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 422 if (timeout <= 0) { 423 slot_printf(slot, "Reset 0x%x never completed.\n", 424 mask); 425 sdhci_dumpregs(slot); 426 return; 427 } 428 timeout--; 429 DELAY(10); 430 } 431 } 432 433 static uint32_t 434 sdhci_tuning_intmask(const struct sdhci_slot *slot) 435 { 436 uint32_t intmask; 437 438 intmask = 0; 439 if (slot->opt & SDHCI_TUNING_ENABLED) { 440 intmask |= SDHCI_INT_TUNEERR; 441 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 442 slot->retune_mode == SDHCI_RETUNE_MODE_3) 443 intmask |= SDHCI_INT_RETUNE; 444 } 445 return (intmask); 446 } 447 448 static void 449 sdhci_init(struct sdhci_slot *slot) 450 { 451 452 sdhci_reset(slot, SDHCI_RESET_ALL); 453 454 /* Enable interrupts. */ 455 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 456 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 457 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 458 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 459 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 460 SDHCI_INT_ACMD12ERR; 461 462 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 463 !(slot->opt & SDHCI_NON_REMOVABLE)) { 464 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 465 } 466 467 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 468 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 469 } 470 471 static void 472 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 473 { 474 uint32_t clk_base; 475 uint32_t clk_sel; 476 uint32_t res; 477 uint16_t clk; 478 uint16_t div; 479 int timeout; 480 481 if (clock == slot->clock) 482 return; 483 slot->clock = clock; 484 485 /* Turn off the clock. */ 486 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 487 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 488 /* If no clock requested - leave it so. */ 489 if (clock == 0) 490 return; 491 492 /* Determine the clock base frequency */ 493 clk_base = slot->max_clk; 494 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 495 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 496 BCM577XX_CTRL_CLKSEL_MASK; 497 498 /* 499 * Select clock source appropriate for the requested frequency. 500 */ 501 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 502 clk_base = BCM577XX_ALT_CLOCK_BASE; 503 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 504 BCM577XX_CTRL_CLKSEL_SHIFT); 505 } else { 506 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 507 BCM577XX_CTRL_CLKSEL_SHIFT); 508 } 509 510 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 511 } 512 513 /* Recalculate timeout clock frequency based on the new sd clock. */ 514 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 515 slot->timeout_clk = slot->clock / 1000; 516 517 if (slot->version < SDHCI_SPEC_300) { 518 /* Looking for highest freq <= clock. */ 519 res = clk_base; 520 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 521 if (res <= clock) 522 break; 523 res >>= 1; 524 } 525 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 526 div >>= 1; 527 } else { 528 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 529 if (clock >= clk_base) 530 div = 0; 531 else { 532 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 533 if ((clk_base / div) <= clock) 534 break; 535 } 536 } 537 div >>= 1; 538 } 539 540 if (bootverbose || sdhci_debug) 541 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 542 div, clock, clk_base); 543 544 /* Now we have got divider, set it. */ 545 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 546 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 547 << SDHCI_DIVIDER_HI_SHIFT; 548 549 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 550 /* Enable clock. */ 551 clk |= SDHCI_CLOCK_INT_EN; 552 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 553 /* Wait up to 10 ms until it stabilize. */ 554 timeout = 10; 555 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 556 & SDHCI_CLOCK_INT_STABLE)) { 557 if (timeout == 0) { 558 slot_printf(slot, 559 "Internal clock never stabilised.\n"); 560 sdhci_dumpregs(slot); 561 return; 562 } 563 timeout--; 564 DELAY(1000); 565 } 566 /* Pass clock signal to the bus. */ 567 clk |= SDHCI_CLOCK_CARD_EN; 568 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 569 } 570 571 static void 572 sdhci_set_power(struct sdhci_slot *slot, u_char power) 573 { 574 int i; 575 uint8_t pwr; 576 577 if (slot->power == power) 578 return; 579 580 slot->power = power; 581 582 /* Turn off the power. */ 583 pwr = 0; 584 WR1(slot, SDHCI_POWER_CONTROL, pwr); 585 /* If power down requested - leave it so. */ 586 if (power == 0) 587 return; 588 /* Set voltage. */ 589 switch (1 << power) { 590 case MMC_OCR_LOW_VOLTAGE: 591 pwr |= SDHCI_POWER_180; 592 break; 593 case MMC_OCR_290_300: 594 case MMC_OCR_300_310: 595 pwr |= SDHCI_POWER_300; 596 break; 597 case MMC_OCR_320_330: 598 case MMC_OCR_330_340: 599 pwr |= SDHCI_POWER_330; 600 break; 601 } 602 WR1(slot, SDHCI_POWER_CONTROL, pwr); 603 /* 604 * Turn on VDD1 power. Note that at least some Intel controllers can 605 * fail to enable bus power on the first try after transiting from D3 606 * to D0, so we give them up to 2 ms. 607 */ 608 pwr |= SDHCI_POWER_ON; 609 for (i = 0; i < 20; i++) { 610 WR1(slot, SDHCI_POWER_CONTROL, pwr); 611 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 612 break; 613 DELAY(100); 614 } 615 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 616 slot_printf(slot, "Bus power failed to enable\n"); 617 618 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 619 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 620 DELAY(10); 621 WR1(slot, SDHCI_POWER_CONTROL, pwr); 622 DELAY(300); 623 } 624 } 625 626 static void 627 sdhci_read_block_pio(struct sdhci_slot *slot) 628 { 629 uint32_t data; 630 char *buffer; 631 size_t left; 632 633 buffer = slot->curcmd->data->data; 634 buffer += slot->offset; 635 /* Transfer one block at a time. */ 636 #ifdef MMCCAM 637 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) 638 left = min(slot->curcmd->data->block_size, 639 slot->curcmd->data->len - slot->offset); 640 else 641 #endif 642 left = min(512, slot->curcmd->data->len - slot->offset); 643 slot->offset += left; 644 645 /* If we are too fast, broken controllers return zeroes. */ 646 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 647 DELAY(10); 648 /* Handle unaligned and aligned buffer cases. */ 649 if ((intptr_t)buffer & 3) { 650 while (left > 3) { 651 data = RD4(slot, SDHCI_BUFFER); 652 buffer[0] = data; 653 buffer[1] = (data >> 8); 654 buffer[2] = (data >> 16); 655 buffer[3] = (data >> 24); 656 buffer += 4; 657 left -= 4; 658 } 659 } else { 660 RD_MULTI_4(slot, SDHCI_BUFFER, 661 (uint32_t *)buffer, left >> 2); 662 left &= 3; 663 } 664 /* Handle uneven size case. */ 665 if (left > 0) { 666 data = RD4(slot, SDHCI_BUFFER); 667 while (left > 0) { 668 *(buffer++) = data; 669 data >>= 8; 670 left--; 671 } 672 } 673 } 674 675 static void 676 sdhci_write_block_pio(struct sdhci_slot *slot) 677 { 678 uint32_t data = 0; 679 char *buffer; 680 size_t left; 681 682 buffer = slot->curcmd->data->data; 683 buffer += slot->offset; 684 /* Transfer one block at a time. */ 685 #ifdef MMCCAM 686 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) { 687 left = min(slot->curcmd->data->block_size, 688 slot->curcmd->data->len - slot->offset); 689 } else 690 #endif 691 left = min(512, slot->curcmd->data->len - slot->offset); 692 slot->offset += left; 693 694 /* Handle unaligned and aligned buffer cases. */ 695 if ((intptr_t)buffer & 3) { 696 while (left > 3) { 697 data = buffer[0] + 698 (buffer[1] << 8) + 699 (buffer[2] << 16) + 700 (buffer[3] << 24); 701 left -= 4; 702 buffer += 4; 703 WR4(slot, SDHCI_BUFFER, data); 704 } 705 } else { 706 WR_MULTI_4(slot, SDHCI_BUFFER, 707 (uint32_t *)buffer, left >> 2); 708 left &= 3; 709 } 710 /* Handle uneven size case. */ 711 if (left > 0) { 712 while (left > 0) { 713 data <<= 8; 714 data += *(buffer++); 715 left--; 716 } 717 WR4(slot, SDHCI_BUFFER, data); 718 } 719 } 720 721 static void 722 sdhci_transfer_pio(struct sdhci_slot *slot) 723 { 724 725 /* Read as many blocks as possible. */ 726 if (slot->curcmd->data->flags & MMC_DATA_READ) { 727 while (RD4(slot, SDHCI_PRESENT_STATE) & 728 SDHCI_DATA_AVAILABLE) { 729 sdhci_read_block_pio(slot); 730 if (slot->offset >= slot->curcmd->data->len) 731 break; 732 } 733 } else { 734 while (RD4(slot, SDHCI_PRESENT_STATE) & 735 SDHCI_SPACE_AVAILABLE) { 736 sdhci_write_block_pio(slot); 737 if (slot->offset >= slot->curcmd->data->len) 738 break; 739 } 740 } 741 } 742 743 static void 744 sdhci_card_task(void *arg, int pending __unused) 745 { 746 struct sdhci_slot *slot = arg; 747 device_t d; 748 749 SDHCI_LOCK(slot); 750 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 751 #ifdef MMCCAM 752 if (slot->card_present == 0) { 753 #else 754 if (slot->dev == NULL) { 755 #endif 756 /* If card is present - attach mmc bus. */ 757 if (bootverbose || sdhci_debug) 758 slot_printf(slot, "Card inserted\n"); 759 #ifdef MMCCAM 760 slot->card_present = 1; 761 mmccam_start_discovery(slot->sim); 762 SDHCI_UNLOCK(slot); 763 #else 764 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 765 SDHCI_UNLOCK(slot); 766 if (d) { 767 device_set_ivars(d, slot); 768 (void)device_probe_and_attach(d); 769 } 770 #endif 771 } else 772 SDHCI_UNLOCK(slot); 773 } else { 774 #ifdef MMCCAM 775 if (slot->card_present == 1) { 776 #else 777 if (slot->dev != NULL) { 778 #endif 779 /* If no card present - detach mmc bus. */ 780 if (bootverbose || sdhci_debug) 781 slot_printf(slot, "Card removed\n"); 782 d = slot->dev; 783 slot->dev = NULL; 784 #ifdef MMCCAM 785 slot->card_present = 0; 786 mmccam_start_discovery(slot->sim); 787 SDHCI_UNLOCK(slot); 788 #else 789 slot->intmask &= ~sdhci_tuning_intmask(slot); 790 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 791 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 792 slot->opt &= ~SDHCI_TUNING_ENABLED; 793 SDHCI_UNLOCK(slot); 794 callout_drain(&slot->retune_callout); 795 device_delete_child(slot->bus, d); 796 #endif 797 } else 798 SDHCI_UNLOCK(slot); 799 } 800 } 801 802 static void 803 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 804 { 805 bool was_present; 806 807 /* 808 * If there was no card and now there is one, schedule the task to 809 * create the child device after a short delay. The delay is to 810 * debounce the card insert (sometimes the card detect pin stabilizes 811 * before the other pins have made good contact). 812 * 813 * If there was a card present and now it's gone, immediately schedule 814 * the task to delete the child device. No debouncing -- gone is gone, 815 * because once power is removed, a full card re-init is needed, and 816 * that happens by deleting and recreating the child device. 817 */ 818 #ifdef MMCCAM 819 was_present = slot->card_present; 820 #else 821 was_present = slot->dev != NULL; 822 #endif 823 if (!was_present && is_present) { 824 taskqueue_enqueue_timeout(taskqueue_swi_giant, 825 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 826 } else if (was_present && !is_present) { 827 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 828 } 829 } 830 831 void 832 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 833 { 834 835 SDHCI_LOCK(slot); 836 sdhci_handle_card_present_locked(slot, is_present); 837 SDHCI_UNLOCK(slot); 838 } 839 840 static void 841 sdhci_card_poll(void *arg) 842 { 843 struct sdhci_slot *slot = arg; 844 845 sdhci_handle_card_present(slot, 846 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 847 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 848 sdhci_card_poll, slot); 849 } 850 851 static int 852 sdhci_dma_alloc(struct sdhci_slot *slot, uint32_t caps) 853 { 854 int err; 855 856 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) { 857 if (maxphys <= 1024 * 4) 858 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 859 else if (maxphys <= 1024 * 8) 860 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K; 861 else if (maxphys <= 1024 * 16) 862 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K; 863 else if (maxphys <= 1024 * 32) 864 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K; 865 else if (maxphys <= 1024 * 64) 866 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K; 867 else if (maxphys <= 1024 * 128) 868 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K; 869 else if (maxphys <= 1024 * 256) 870 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K; 871 else 872 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K; 873 } 874 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary); 875 876 /* 877 * Allocate the DMA tag for an SDMA bounce buffer. 878 * Note that the SDHCI specification doesn't state any alignment 879 * constraint for the SDMA system address. However, controllers 880 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when 881 * forming the actual address of data, requiring the SDMA buffer to 882 * be aligned to the SDMA boundary. 883 */ 884 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz, 885 0, (caps & SDHCI_CAN_DO_64BIT) ? BUS_SPACE_MAXADDR : 886 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 887 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW, 888 NULL, NULL, &slot->dmatag); 889 if (err != 0) { 890 slot_printf(slot, "Can't create DMA tag for SDMA\n"); 891 return (err); 892 } 893 /* Allocate DMA memory for the SDMA bounce buffer. */ 894 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 895 BUS_DMA_NOWAIT, &slot->dmamap); 896 if (err != 0) { 897 slot_printf(slot, "Can't alloc DMA memory for SDMA\n"); 898 bus_dma_tag_destroy(slot->dmatag); 899 return (err); 900 } 901 /* Map the memory of the SDMA bounce buffer. */ 902 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 903 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr, 904 &slot->paddr, 0); 905 if (err != 0 || slot->paddr == 0) { 906 slot_printf(slot, "Can't load DMA memory for SDMA\n"); 907 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 908 bus_dma_tag_destroy(slot->dmatag); 909 if (err) 910 return (err); 911 else 912 return (EFAULT); 913 } 914 915 return (0); 916 } 917 918 static void 919 sdhci_dma_free(struct sdhci_slot *slot) 920 { 921 922 bus_dmamap_unload(slot->dmatag, slot->dmamap); 923 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 924 bus_dma_tag_destroy(slot->dmatag); 925 } 926 927 int 928 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 929 { 930 kobjop_desc_t kobj_desc; 931 kobj_method_t *kobj_method; 932 uint32_t caps, caps2, freq, host_caps; 933 int err; 934 char node_name[8]; 935 struct sysctl_oid *node_oid; 936 937 SDHCI_LOCK_INIT(slot); 938 939 slot->num = num; 940 slot->bus = dev; 941 942 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 943 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 944 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 945 caps = slot->caps; 946 caps2 = slot->caps2; 947 } else { 948 caps = RD4(slot, SDHCI_CAPABILITIES); 949 if (slot->version >= SDHCI_SPEC_300) 950 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 951 else 952 caps2 = 0; 953 } 954 if (slot->version >= SDHCI_SPEC_300) { 955 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 956 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 957 slot_printf(slot, 958 "Driver doesn't support shared bus slots\n"); 959 SDHCI_LOCK_DESTROY(slot); 960 return (ENXIO); 961 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 962 SDHCI_SLOTTYPE_EMBEDDED) { 963 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 964 } 965 } 966 /* Calculate base clock frequency. */ 967 if (slot->version >= SDHCI_SPEC_300) 968 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 969 SDHCI_CLOCK_BASE_SHIFT; 970 else 971 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 972 SDHCI_CLOCK_BASE_SHIFT; 973 if (freq != 0) 974 slot->max_clk = freq * 1000000; 975 /* 976 * If the frequency wasn't in the capabilities and the hardware driver 977 * hasn't already set max_clk we're probably not going to work right 978 * with an assumption, so complain about it. 979 */ 980 if (slot->max_clk == 0) { 981 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 982 slot_printf(slot, "Hardware doesn't specify base clock " 983 "frequency, using %dMHz as default.\n", 984 SDHCI_DEFAULT_MAX_FREQ); 985 } 986 /* Calculate/set timeout clock frequency. */ 987 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 988 slot->timeout_clk = slot->max_clk / 1000; 989 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 990 slot->timeout_clk = 1000; 991 } else { 992 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 993 SDHCI_TIMEOUT_CLK_SHIFT; 994 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 995 slot->timeout_clk *= 1000; 996 } 997 /* 998 * If the frequency wasn't in the capabilities and the hardware driver 999 * hasn't already set timeout_clk we'll probably work okay using the 1000 * max timeout, but still mention it. 1001 */ 1002 if (slot->timeout_clk == 0) { 1003 slot_printf(slot, "Hardware doesn't specify timeout clock " 1004 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 1005 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1006 } 1007 1008 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 1009 slot->host.f_max = slot->max_clk; 1010 slot->host.host_ocr = 0; 1011 if (caps & SDHCI_CAN_VDD_330) 1012 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 1013 if (caps & SDHCI_CAN_VDD_300) 1014 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 1015 /* 1016 * 1.8V VDD is not supposed to be used for removable cards. Hardware 1017 * prior to v3.0 had no way to indicate embedded slots, but did 1018 * sometimes support 1.8v for non-removable devices. 1019 */ 1020 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 || 1021 (slot->opt & SDHCI_SLOT_EMBEDDED))) 1022 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 1023 if (slot->host.host_ocr == 0) { 1024 slot_printf(slot, "Hardware doesn't report any " 1025 "support voltages.\n"); 1026 } 1027 1028 host_caps = slot->host.caps; 1029 host_caps |= MMC_CAP_4_BIT_DATA; 1030 if (caps & SDHCI_CAN_DO_8BITBUS) 1031 host_caps |= MMC_CAP_8_BIT_DATA; 1032 if (caps & SDHCI_CAN_DO_HISPD) 1033 host_caps |= MMC_CAP_HSPEED; 1034 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 1035 host_caps |= MMC_CAP_BOOT_NOACC; 1036 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 1037 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 1038 1039 /* Determine supported UHS-I and eMMC modes. */ 1040 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 1041 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1042 if (caps2 & SDHCI_CAN_SDR104) { 1043 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 1044 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 1045 host_caps |= MMC_CAP_MMC_HS200; 1046 } else if (caps2 & SDHCI_CAN_SDR50) 1047 host_caps |= MMC_CAP_UHS_SDR50; 1048 if (caps2 & SDHCI_CAN_DDR50 && 1049 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 1050 host_caps |= MMC_CAP_UHS_DDR50; 1051 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 1052 host_caps |= MMC_CAP_MMC_DDR52; 1053 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 1054 caps2 & SDHCI_CAN_MMC_HS400) 1055 host_caps |= MMC_CAP_MMC_HS400; 1056 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 && 1057 caps2 & SDHCI_CAN_SDR104) 1058 host_caps |= MMC_CAP_MMC_HS400; 1059 1060 /* 1061 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 1062 * default NULL implementation. 1063 */ 1064 kobj_desc = &sdhci_set_uhs_timing_desc; 1065 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1066 kobj_desc); 1067 if (kobj_method == &kobj_desc->deflt) 1068 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1069 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 1070 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 1071 1072 #define SDHCI_CAP_MODES_TUNING(caps2) \ 1073 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 1074 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 1075 MMC_CAP_MMC_HS400) 1076 1077 /* 1078 * Disable UHS-I and eMMC modes that require (re-)tuning if either 1079 * the tune or re-tune method is the default NULL implementation. 1080 */ 1081 kobj_desc = &mmcbr_tune_desc; 1082 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1083 kobj_desc); 1084 if (kobj_method == &kobj_desc->deflt) 1085 goto no_tuning; 1086 kobj_desc = &mmcbr_retune_desc; 1087 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1088 kobj_desc); 1089 if (kobj_method == &kobj_desc->deflt) { 1090 no_tuning: 1091 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 1092 } 1093 1094 /* Allocate tuning structures and determine tuning parameters. */ 1095 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 1096 slot->opt |= SDHCI_TUNING_SUPPORTED; 1097 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 1098 M_WAITOK); 1099 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 1100 M_WAITOK); 1101 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 1102 M_WAITOK); 1103 if (caps2 & SDHCI_TUNE_SDR50) 1104 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 1105 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 1106 SDHCI_RETUNE_MODES_SHIFT; 1107 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 1108 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 1109 SDHCI_RETUNE_CNT_SHIFT; 1110 if (slot->retune_count > 0xb) { 1111 slot_printf(slot, "Unknown re-tuning count " 1112 "%x, using 1 sec\n", slot->retune_count); 1113 slot->retune_count = 1; 1114 } else if (slot->retune_count != 0) 1115 slot->retune_count = 1116 1 << (slot->retune_count - 1); 1117 } 1118 } 1119 1120 #undef SDHCI_CAP_MODES_TUNING 1121 1122 /* Determine supported VCCQ signaling levels. */ 1123 host_caps |= MMC_CAP_SIGNALING_330; 1124 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1125 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 1126 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 1127 MMC_CAP_MMC_HS400_180)) 1128 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 1129 1130 /* 1131 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 1132 * default NULL implementation. Disable 1.2 V support if it's the 1133 * generic SDHCI implementation. 1134 */ 1135 kobj_desc = &mmcbr_switch_vccq_desc; 1136 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1137 kobj_desc); 1138 if (kobj_method == &kobj_desc->deflt) 1139 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 1140 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 1141 host_caps &= ~MMC_CAP_SIGNALING_120; 1142 1143 /* Determine supported driver types (type B is always mandatory). */ 1144 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 1145 host_caps |= MMC_CAP_DRIVER_TYPE_A; 1146 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 1147 host_caps |= MMC_CAP_DRIVER_TYPE_C; 1148 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 1149 host_caps |= MMC_CAP_DRIVER_TYPE_D; 1150 slot->host.caps = host_caps; 1151 1152 /* Decide if we have usable DMA. */ 1153 if (caps & SDHCI_CAN_DO_DMA) 1154 slot->opt |= SDHCI_HAVE_DMA; 1155 1156 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 1157 slot->opt &= ~SDHCI_HAVE_DMA; 1158 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 1159 slot->opt |= SDHCI_HAVE_DMA; 1160 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 1161 slot->opt |= SDHCI_NON_REMOVABLE; 1162 1163 /* 1164 * Use platform-provided transfer backend 1165 * with PIO as a fallback mechanism 1166 */ 1167 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 1168 slot->opt &= ~SDHCI_HAVE_DMA; 1169 1170 if (slot->opt & SDHCI_HAVE_DMA) { 1171 err = sdhci_dma_alloc(slot, caps); 1172 if (err != 0) { 1173 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1174 free(slot->tune_req, M_DEVBUF); 1175 free(slot->tune_cmd, M_DEVBUF); 1176 free(slot->tune_data, M_DEVBUF); 1177 } 1178 SDHCI_LOCK_DESTROY(slot); 1179 return (err); 1180 } 1181 } 1182 1183 if (bootverbose || sdhci_debug) { 1184 sdhci_dumpcaps(slot); 1185 sdhci_dumpregs(slot); 1186 } 1187 1188 slot->timeout = 10; 1189 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1190 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1191 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0, 1192 "Maximum timeout for SDHCI transfers (in secs)"); 1193 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1194 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1195 sdhci_card_task, slot); 1196 callout_init(&slot->card_poll_callout, 1); 1197 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1198 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1199 1200 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1201 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1202 callout_reset(&slot->card_poll_callout, 1203 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1204 } 1205 1206 sdhci_init(slot); 1207 1208 snprintf(node_name, sizeof(node_name), "slot%d", slot->num); 1209 1210 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev), 1211 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1212 OID_AUTO, node_name, CTLFLAG_RW, 0, "slot specific node"); 1213 1214 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev), 1215 SYSCTL_CHILDREN(node_oid), OID_AUTO, "debug", CTLFLAG_RW, 0, 1216 "Debugging node"); 1217 1218 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid), 1219 OID_AUTO, "dumpregs", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1220 slot, 0, &sdhci_syctl_dumpregs, 1221 "A", "Dump SDHCI registers"); 1222 1223 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid), 1224 OID_AUTO, "dumpcaps", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1225 slot, 0, &sdhci_syctl_dumpcaps, 1226 "A", "Dump SDHCI capabilites"); 1227 1228 return (0); 1229 } 1230 1231 #ifndef MMCCAM 1232 void 1233 sdhci_start_slot(struct sdhci_slot *slot) 1234 { 1235 1236 sdhci_card_task(slot, 0); 1237 } 1238 #endif 1239 1240 int 1241 sdhci_cleanup_slot(struct sdhci_slot *slot) 1242 { 1243 device_t d; 1244 1245 callout_drain(&slot->timeout_callout); 1246 callout_drain(&slot->card_poll_callout); 1247 callout_drain(&slot->retune_callout); 1248 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1249 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1250 1251 SDHCI_LOCK(slot); 1252 d = slot->dev; 1253 slot->dev = NULL; 1254 SDHCI_UNLOCK(slot); 1255 if (d != NULL) 1256 device_delete_child(slot->bus, d); 1257 1258 SDHCI_LOCK(slot); 1259 sdhci_reset(slot, SDHCI_RESET_ALL); 1260 SDHCI_UNLOCK(slot); 1261 if (slot->opt & SDHCI_HAVE_DMA) 1262 sdhci_dma_free(slot); 1263 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1264 free(slot->tune_req, M_DEVBUF); 1265 free(slot->tune_cmd, M_DEVBUF); 1266 free(slot->tune_data, M_DEVBUF); 1267 } 1268 1269 SDHCI_LOCK_DESTROY(slot); 1270 1271 return (0); 1272 } 1273 1274 int 1275 sdhci_generic_suspend(struct sdhci_slot *slot) 1276 { 1277 1278 /* 1279 * We expect the MMC layer to issue initial tuning after resume. 1280 * Otherwise, we'd need to indicate re-tuning including circuit reset 1281 * being required at least for re-tuning modes 1 and 2 ourselves. 1282 */ 1283 callout_drain(&slot->retune_callout); 1284 SDHCI_LOCK(slot); 1285 slot->opt &= ~SDHCI_TUNING_ENABLED; 1286 sdhci_reset(slot, SDHCI_RESET_ALL); 1287 SDHCI_UNLOCK(slot); 1288 1289 return (0); 1290 } 1291 1292 int 1293 sdhci_generic_resume(struct sdhci_slot *slot) 1294 { 1295 1296 SDHCI_LOCK(slot); 1297 sdhci_init(slot); 1298 SDHCI_UNLOCK(slot); 1299 1300 return (0); 1301 } 1302 1303 uint32_t 1304 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1305 { 1306 1307 if (slot->version >= SDHCI_SPEC_300) 1308 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1309 else 1310 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1311 } 1312 1313 bool 1314 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1315 { 1316 1317 if (slot->opt & SDHCI_NON_REMOVABLE) 1318 return true; 1319 1320 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1321 } 1322 1323 void 1324 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1325 { 1326 const struct mmc_ios *ios; 1327 uint16_t hostctrl2; 1328 1329 if (slot->version < SDHCI_SPEC_300) 1330 return; 1331 1332 SDHCI_ASSERT_LOCKED(slot); 1333 ios = &slot->host.ios; 1334 sdhci_set_clock(slot, 0); 1335 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1336 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1337 if (ios->clock > SD_SDR50_MAX) { 1338 if (ios->timing == bus_timing_mmc_hs400 || 1339 ios->timing == bus_timing_mmc_hs400es) 1340 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1341 else 1342 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1343 } 1344 else if (ios->clock > SD_SDR25_MAX) 1345 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1346 else if (ios->clock > SD_SDR12_MAX) { 1347 if (ios->timing == bus_timing_uhs_ddr50 || 1348 ios->timing == bus_timing_mmc_ddr52) 1349 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1350 else 1351 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1352 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1353 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1354 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1355 sdhci_set_clock(slot, ios->clock); 1356 } 1357 1358 int 1359 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1360 { 1361 struct sdhci_slot *slot = device_get_ivars(reqdev); 1362 struct mmc_ios *ios = &slot->host.ios; 1363 1364 SDHCI_LOCK(slot); 1365 /* Do full reset on bus power down to clear from any state. */ 1366 if (ios->power_mode == power_off) { 1367 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1368 sdhci_init(slot); 1369 } 1370 /* Configure the bus. */ 1371 sdhci_set_clock(slot, ios->clock); 1372 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1373 if (ios->bus_width == bus_width_8) { 1374 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1375 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1376 } else if (ios->bus_width == bus_width_4) { 1377 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1378 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1379 } else if (ios->bus_width == bus_width_1) { 1380 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1381 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1382 } else { 1383 panic("Invalid bus width: %d", ios->bus_width); 1384 } 1385 if (ios->clock > SD_SDR12_MAX && 1386 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1387 slot->hostctrl |= SDHCI_CTRL_HISPD; 1388 else 1389 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1390 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1391 SDHCI_SET_UHS_TIMING(brdev, slot); 1392 /* Some controllers like reset after bus changes. */ 1393 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1394 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1395 1396 SDHCI_UNLOCK(slot); 1397 return (0); 1398 } 1399 1400 int 1401 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1402 { 1403 struct sdhci_slot *slot = device_get_ivars(reqdev); 1404 enum mmc_vccq vccq; 1405 int err; 1406 uint16_t hostctrl2; 1407 1408 if (slot->version < SDHCI_SPEC_300) 1409 return (0); 1410 1411 err = 0; 1412 vccq = slot->host.ios.vccq; 1413 SDHCI_LOCK(slot); 1414 sdhci_set_clock(slot, 0); 1415 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1416 switch (vccq) { 1417 case vccq_330: 1418 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1419 goto done; 1420 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1421 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1422 DELAY(5000); 1423 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1424 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1425 goto done; 1426 err = EAGAIN; 1427 break; 1428 case vccq_180: 1429 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1430 err = EINVAL; 1431 goto done; 1432 } 1433 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1434 goto done; 1435 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1436 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1437 DELAY(5000); 1438 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1439 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1440 goto done; 1441 err = EAGAIN; 1442 break; 1443 default: 1444 slot_printf(slot, 1445 "Attempt to set unsupported signaling voltage\n"); 1446 err = EINVAL; 1447 break; 1448 } 1449 done: 1450 sdhci_set_clock(slot, slot->host.ios.clock); 1451 SDHCI_UNLOCK(slot); 1452 return (err); 1453 } 1454 1455 int 1456 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1457 { 1458 struct sdhci_slot *slot = device_get_ivars(reqdev); 1459 const struct mmc_ios *ios = &slot->host.ios; 1460 struct mmc_command *tune_cmd; 1461 struct mmc_data *tune_data; 1462 uint32_t opcode; 1463 int err; 1464 1465 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1466 return (0); 1467 1468 slot->retune_ticks = slot->retune_count * hz; 1469 opcode = MMC_SEND_TUNING_BLOCK; 1470 SDHCI_LOCK(slot); 1471 switch (ios->timing) { 1472 case bus_timing_mmc_hs400: 1473 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1474 SDHCI_UNLOCK(slot); 1475 return (EINVAL); 1476 case bus_timing_mmc_hs200: 1477 /* 1478 * In HS400 mode, controllers use the data strobe line to 1479 * latch data from the devices so periodic re-tuning isn't 1480 * expected to be required. 1481 */ 1482 if (hs400) 1483 slot->retune_ticks = 0; 1484 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1485 break; 1486 case bus_timing_uhs_ddr50: 1487 case bus_timing_uhs_sdr104: 1488 break; 1489 case bus_timing_uhs_sdr50: 1490 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1491 break; 1492 /* FALLTHROUGH */ 1493 default: 1494 SDHCI_UNLOCK(slot); 1495 return (0); 1496 } 1497 1498 tune_cmd = slot->tune_cmd; 1499 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1500 tune_cmd->opcode = opcode; 1501 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1502 tune_data = tune_cmd->data = slot->tune_data; 1503 memset(tune_data, 0, sizeof(*tune_data)); 1504 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1505 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1506 MMC_TUNING_LEN; 1507 tune_data->flags = MMC_DATA_READ; 1508 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1509 1510 slot->opt &= ~SDHCI_TUNING_ENABLED; 1511 err = sdhci_exec_tuning(slot, true); 1512 if (err == 0) { 1513 slot->opt |= SDHCI_TUNING_ENABLED; 1514 slot->intmask |= sdhci_tuning_intmask(slot); 1515 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1516 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1517 if (slot->retune_ticks) { 1518 callout_reset(&slot->retune_callout, slot->retune_ticks, 1519 sdhci_retune, slot); 1520 } 1521 } 1522 SDHCI_UNLOCK(slot); 1523 return (err); 1524 } 1525 1526 int 1527 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1528 { 1529 struct sdhci_slot *slot = device_get_ivars(reqdev); 1530 int err; 1531 1532 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1533 return (0); 1534 1535 /* HS400 must be tuned in HS200 mode. */ 1536 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1537 return (EINVAL); 1538 1539 SDHCI_LOCK(slot); 1540 err = sdhci_exec_tuning(slot, reset); 1541 /* 1542 * There are two ways sdhci_exec_tuning() can fail: 1543 * EBUSY should not actually happen when requests are only issued 1544 * with the host properly acquired, and 1545 * EIO re-tuning failed (but it did work initially). 1546 * 1547 * In both cases, we should retry at later point if periodic re-tuning 1548 * is enabled. Note that due to slot->retune_req not being cleared in 1549 * these failure cases, the MMC layer should trigger another attempt at 1550 * re-tuning with the next request anyway, though. 1551 */ 1552 if (slot->retune_ticks) { 1553 callout_reset(&slot->retune_callout, slot->retune_ticks, 1554 sdhci_retune, slot); 1555 } 1556 SDHCI_UNLOCK(slot); 1557 return (err); 1558 } 1559 1560 static int 1561 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1562 { 1563 struct mmc_request *tune_req; 1564 struct mmc_command *tune_cmd; 1565 int i; 1566 uint32_t intmask; 1567 uint16_t hostctrl2; 1568 u_char opt; 1569 1570 SDHCI_ASSERT_LOCKED(slot); 1571 if (slot->req != NULL) 1572 return (EBUSY); 1573 1574 /* Tuning doesn't work with DMA enabled. */ 1575 opt = slot->opt; 1576 slot->opt = opt & ~SDHCI_HAVE_DMA; 1577 1578 /* 1579 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1580 * kind of interrupt we receive in response to a tuning request. 1581 */ 1582 intmask = slot->intmask; 1583 slot->intmask = SDHCI_INT_DATA_AVAIL; 1584 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL); 1585 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1586 1587 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1588 if (reset) 1589 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1590 else 1591 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1592 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1593 1594 tune_req = slot->tune_req; 1595 tune_cmd = slot->tune_cmd; 1596 for (i = 0; i < MMC_TUNING_MAX; i++) { 1597 memset(tune_req, 0, sizeof(*tune_req)); 1598 tune_req->cmd = tune_cmd; 1599 tune_req->done = sdhci_req_wakeup; 1600 tune_req->done_data = slot; 1601 slot->req = tune_req; 1602 slot->flags = 0; 1603 sdhci_start(slot); 1604 while (!(tune_req->flags & MMC_REQ_DONE)) 1605 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1606 if (!(tune_req->flags & MMC_TUNE_DONE)) 1607 break; 1608 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1609 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1610 break; 1611 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1612 DELAY(1000); 1613 } 1614 1615 /* 1616 * Restore DMA usage and interrupts. 1617 * Note that the interrupt aggregation code might have cleared 1618 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask 1619 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE 1620 * doesn't lose these. 1621 */ 1622 slot->opt = opt; 1623 slot->intmask = intmask; 1624 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END | 1625 SDHCI_INT_RESPONSE); 1626 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1627 1628 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1629 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1630 slot->retune_req = 0; 1631 return (0); 1632 } 1633 1634 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1635 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1636 SDHCI_CTRL2_SAMPLING_CLOCK)); 1637 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1638 return (EIO); 1639 } 1640 1641 static void 1642 sdhci_retune(void *arg) 1643 { 1644 struct sdhci_slot *slot = arg; 1645 1646 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1647 } 1648 1649 #ifdef MMCCAM 1650 static void 1651 sdhci_req_done(struct sdhci_slot *slot) 1652 { 1653 union ccb *ccb; 1654 1655 if (__predict_false(sdhci_debug > 1)) 1656 slot_printf(slot, "%s\n", __func__); 1657 if (slot->ccb != NULL && slot->curcmd != NULL) { 1658 callout_stop(&slot->timeout_callout); 1659 ccb = slot->ccb; 1660 slot->ccb = NULL; 1661 slot->curcmd = NULL; 1662 1663 /* Tell CAM the request is finished */ 1664 struct ccb_mmcio *mmcio; 1665 mmcio = &ccb->mmcio; 1666 1667 ccb->ccb_h.status = 1668 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1669 xpt_done(ccb); 1670 } 1671 } 1672 #else 1673 static void 1674 sdhci_req_done(struct sdhci_slot *slot) 1675 { 1676 struct mmc_request *req; 1677 1678 if (slot->req != NULL && slot->curcmd != NULL) { 1679 callout_stop(&slot->timeout_callout); 1680 req = slot->req; 1681 slot->req = NULL; 1682 slot->curcmd = NULL; 1683 req->done(req); 1684 } 1685 } 1686 #endif 1687 1688 static void 1689 sdhci_req_wakeup(struct mmc_request *req) 1690 { 1691 struct sdhci_slot *slot; 1692 1693 slot = req->done_data; 1694 req->flags |= MMC_REQ_DONE; 1695 wakeup(req); 1696 } 1697 1698 static void 1699 sdhci_timeout(void *arg) 1700 { 1701 struct sdhci_slot *slot = arg; 1702 1703 if (slot->curcmd != NULL) { 1704 slot_printf(slot, "Controller timeout\n"); 1705 sdhci_dumpregs(slot); 1706 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1707 slot->curcmd->error = MMC_ERR_TIMEOUT; 1708 sdhci_req_done(slot); 1709 } else { 1710 slot_printf(slot, "Spurious timeout - no active command\n"); 1711 } 1712 } 1713 1714 static void 1715 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data) 1716 { 1717 uint16_t mode; 1718 1719 if (data == NULL) 1720 return; 1721 1722 mode = SDHCI_TRNS_BLK_CNT_EN; 1723 if (data->len > 512 || data->block_count > 1) { 1724 mode |= SDHCI_TRNS_MULTI; 1725 if (data->block_count == 0 && __predict_true( 1726 #ifdef MMCCAM 1727 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION && 1728 #else 1729 slot->req->stop != NULL && 1730 #endif 1731 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))) 1732 mode |= SDHCI_TRNS_ACMD12; 1733 } 1734 if (data->flags & MMC_DATA_READ) 1735 mode |= SDHCI_TRNS_READ; 1736 if (slot->flags & SDHCI_USE_DMA) 1737 mode |= SDHCI_TRNS_DMA; 1738 1739 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1740 } 1741 1742 static void 1743 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1744 { 1745 int flags, timeout; 1746 uint32_t mask; 1747 1748 slot->curcmd = cmd; 1749 slot->cmd_done = 0; 1750 1751 cmd->error = MMC_ERR_NONE; 1752 1753 /* This flags combination is not supported by controller. */ 1754 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1755 slot_printf(slot, "Unsupported response type!\n"); 1756 cmd->error = MMC_ERR_FAILED; 1757 sdhci_req_done(slot); 1758 return; 1759 } 1760 1761 /* 1762 * Do not issue command if there is no card, clock or power. 1763 * Controller will not detect timeout without clock active. 1764 */ 1765 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1766 slot->power == 0 || 1767 slot->clock == 0) { 1768 slot_printf(slot, 1769 "Cannot issue a command (power=%d clock=%d)\n", 1770 slot->power, slot->clock); 1771 cmd->error = MMC_ERR_FAILED; 1772 sdhci_req_done(slot); 1773 return; 1774 } 1775 /* Always wait for free CMD bus. */ 1776 mask = SDHCI_CMD_INHIBIT; 1777 /* Wait for free DAT if we have data or busy signal. */ 1778 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1779 mask |= SDHCI_DAT_INHIBIT; 1780 /* 1781 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1782 * that these latter are also special in that SDHCI_CMD_DATA should 1783 * be set below but no actual data is ever read from the controller. 1784 */ 1785 #ifdef MMCCAM 1786 if (cmd == &slot->ccb->mmcio.stop || 1787 #else 1788 if (cmd == slot->req->stop || 1789 #endif 1790 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1791 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1792 mask &= ~SDHCI_DAT_INHIBIT; 1793 /* 1794 * Wait for bus no more then 250 ms. Typically there will be no wait 1795 * here at all, but when writing a crash dump we may be bypassing the 1796 * host platform's interrupt handler, and in some cases that handler 1797 * may be working around hardware quirks such as not respecting r1b 1798 * busy indications. In those cases, this wait-loop serves the purpose 1799 * of waiting for the prior command and data transfers to be done, and 1800 * SD cards are allowed to take up to 250ms for write and erase ops. 1801 * (It's usually more like 20-30ms in the real world.) 1802 */ 1803 timeout = 250; 1804 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1805 if (timeout == 0) { 1806 slot_printf(slot, "Controller never released " 1807 "inhibit bit(s).\n"); 1808 sdhci_dumpregs(slot); 1809 cmd->error = MMC_ERR_FAILED; 1810 sdhci_req_done(slot); 1811 return; 1812 } 1813 timeout--; 1814 DELAY(1000); 1815 } 1816 1817 /* Prepare command flags. */ 1818 if (!(cmd->flags & MMC_RSP_PRESENT)) 1819 flags = SDHCI_CMD_RESP_NONE; 1820 else if (cmd->flags & MMC_RSP_136) 1821 flags = SDHCI_CMD_RESP_LONG; 1822 else if (cmd->flags & MMC_RSP_BUSY) 1823 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1824 else 1825 flags = SDHCI_CMD_RESP_SHORT; 1826 if (cmd->flags & MMC_RSP_CRC) 1827 flags |= SDHCI_CMD_CRC; 1828 if (cmd->flags & MMC_RSP_OPCODE) 1829 flags |= SDHCI_CMD_INDEX; 1830 if (cmd->data != NULL) 1831 flags |= SDHCI_CMD_DATA; 1832 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1833 flags |= SDHCI_CMD_TYPE_ABORT; 1834 /* Prepare data. */ 1835 sdhci_start_data(slot, cmd->data); 1836 /* 1837 * Interrupt aggregation: To reduce total number of interrupts 1838 * group response interrupt with data interrupt when possible. 1839 * If there going to be data interrupt, mask response one. 1840 */ 1841 if (slot->data_done == 0) { 1842 WR4(slot, SDHCI_SIGNAL_ENABLE, 1843 slot->intmask &= ~SDHCI_INT_RESPONSE); 1844 } 1845 /* Set command argument. */ 1846 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1847 /* Set data transfer mode. */ 1848 sdhci_set_transfer_mode(slot, cmd->data); 1849 if (__predict_false(sdhci_debug > 1)) 1850 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n", 1851 cmd->opcode, flags); 1852 1853 /* Start command. */ 1854 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1855 /* Start timeout callout. */ 1856 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1857 sdhci_timeout, slot); 1858 } 1859 1860 static void 1861 sdhci_finish_command(struct sdhci_slot *slot) 1862 { 1863 int i; 1864 uint32_t val; 1865 uint8_t extra; 1866 1867 if (__predict_false(sdhci_debug > 1)) 1868 slot_printf(slot, "%s: called, err %d flags %#04x\n", 1869 __func__, slot->curcmd->error, slot->curcmd->flags); 1870 slot->cmd_done = 1; 1871 /* 1872 * Interrupt aggregation: Restore command interrupt. 1873 * Main restore point for the case when command interrupt 1874 * happened first. 1875 */ 1876 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1877 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1878 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1879 SDHCI_INT_RESPONSE); 1880 /* In case of error - reset host and return. */ 1881 if (slot->curcmd->error) { 1882 if (slot->curcmd->error == MMC_ERR_BADCRC) 1883 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1884 sdhci_reset(slot, SDHCI_RESET_CMD); 1885 sdhci_reset(slot, SDHCI_RESET_DATA); 1886 sdhci_start(slot); 1887 return; 1888 } 1889 /* If command has response - fetch it. */ 1890 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1891 if (slot->curcmd->flags & MMC_RSP_136) { 1892 /* CRC is stripped so we need one byte shift. */ 1893 extra = 0; 1894 for (i = 0; i < 4; i++) { 1895 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1896 if (slot->quirks & 1897 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1898 slot->curcmd->resp[3 - i] = val; 1899 else { 1900 slot->curcmd->resp[3 - i] = 1901 (val << 8) | extra; 1902 extra = val >> 24; 1903 } 1904 } 1905 } else 1906 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1907 } 1908 if (__predict_false(sdhci_debug > 1)) 1909 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n", 1910 slot->curcmd->resp[0], slot->curcmd->resp[1], 1911 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1912 1913 /* If data ready - finish. */ 1914 if (slot->data_done) 1915 sdhci_start(slot); 1916 } 1917 1918 static void 1919 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data) 1920 { 1921 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout; 1922 uint8_t div; 1923 1924 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1925 slot->data_done = 1; 1926 return; 1927 } 1928 1929 slot->data_done = 0; 1930 1931 /* Calculate and set data timeout.*/ 1932 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1933 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1934 div = 0xE; 1935 } else { 1936 target_timeout = 1000000; 1937 div = 0; 1938 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1939 while (current_timeout < target_timeout && div < 0xE) { 1940 ++div; 1941 current_timeout <<= 1; 1942 } 1943 /* Compensate for an off-by-one error in the CaFe chip.*/ 1944 if (div < 0xE && 1945 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1946 ++div; 1947 } 1948 } 1949 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1950 1951 if (data == NULL) 1952 return; 1953 1954 /* Use DMA if possible. */ 1955 if ((slot->opt & SDHCI_HAVE_DMA)) 1956 slot->flags |= SDHCI_USE_DMA; 1957 /* If data is small, broken DMA may return zeroes instead of data. */ 1958 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1959 (data->len <= 512)) 1960 slot->flags &= ~SDHCI_USE_DMA; 1961 /* Some controllers require even block sizes. */ 1962 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1963 ((data->len) & 0x3)) 1964 slot->flags &= ~SDHCI_USE_DMA; 1965 /* Load DMA buffer. */ 1966 if (slot->flags & SDHCI_USE_DMA) { 1967 sdma_bbufsz = slot->sdma_bbufsz; 1968 if (data->flags & MMC_DATA_READ) 1969 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1970 BUS_DMASYNC_PREREAD); 1971 else { 1972 memcpy(slot->dmamem, data->data, ulmin(data->len, 1973 sdma_bbufsz)); 1974 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1975 BUS_DMASYNC_PREWRITE); 1976 } 1977 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1978 /* 1979 * Interrupt aggregation: Mask border interrupt for the last 1980 * bounce buffer and unmask otherwise. 1981 */ 1982 if (data->len == sdma_bbufsz) 1983 slot->intmask &= ~SDHCI_INT_DMA_END; 1984 else 1985 slot->intmask |= SDHCI_INT_DMA_END; 1986 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1987 } 1988 /* Current data offset for both PIO and DMA. */ 1989 slot->offset = 0; 1990 #ifdef MMCCAM 1991 if (data->flags & MMC_DATA_BLOCK_SIZE) { 1992 /* Set block size and request border interrupts on the SDMA boundary. */ 1993 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size); 1994 blkcnt = data->block_count; 1995 if (__predict_false(sdhci_debug > 0)) 1996 slot_printf(slot, "SDIO Custom block params: blksz: " 1997 "%#10x, blk cnt: %#10x\n", blksz, blkcnt); 1998 } else 1999 #endif 2000 { 2001 /* Set block size and request border interrupts on the SDMA boundary. */ 2002 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512)); 2003 blkcnt = howmany(data->len, 512); 2004 } 2005 2006 WR2(slot, SDHCI_BLOCK_SIZE, blksz); 2007 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt); 2008 if (__predict_false(sdhci_debug > 1)) 2009 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 2010 blksz, blkcnt); 2011 } 2012 2013 void 2014 sdhci_finish_data(struct sdhci_slot *slot) 2015 { 2016 struct mmc_data *data = slot->curcmd->data; 2017 size_t left; 2018 2019 /* Interrupt aggregation: Restore command interrupt. 2020 * Auxiliary restore point for the case when data interrupt 2021 * happened first. */ 2022 if (!slot->cmd_done) { 2023 WR4(slot, SDHCI_SIGNAL_ENABLE, 2024 slot->intmask |= SDHCI_INT_RESPONSE); 2025 } 2026 /* Unload rest of data from DMA buffer. */ 2027 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 2028 slot->curcmd->data != NULL) { 2029 if (data->flags & MMC_DATA_READ) { 2030 left = data->len - slot->offset; 2031 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2032 BUS_DMASYNC_POSTREAD); 2033 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2034 ulmin(left, slot->sdma_bbufsz)); 2035 } else 2036 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2037 BUS_DMASYNC_POSTWRITE); 2038 } 2039 slot->data_done = 1; 2040 /* If there was error - reset the host. */ 2041 if (slot->curcmd->error) { 2042 if (slot->curcmd->error == MMC_ERR_BADCRC) 2043 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2044 sdhci_reset(slot, SDHCI_RESET_CMD); 2045 sdhci_reset(slot, SDHCI_RESET_DATA); 2046 sdhci_start(slot); 2047 return; 2048 } 2049 /* If we already have command response - finish. */ 2050 if (slot->cmd_done) 2051 sdhci_start(slot); 2052 } 2053 2054 #ifdef MMCCAM 2055 static void 2056 sdhci_start(struct sdhci_slot *slot) 2057 { 2058 union ccb *ccb; 2059 struct ccb_mmcio *mmcio; 2060 2061 ccb = slot->ccb; 2062 if (ccb == NULL) 2063 return; 2064 2065 mmcio = &ccb->mmcio; 2066 if (!(slot->flags & CMD_STARTED)) { 2067 slot->flags |= CMD_STARTED; 2068 sdhci_start_command(slot, &mmcio->cmd); 2069 return; 2070 } 2071 2072 /* 2073 * Old stack doesn't use this! 2074 * Enabling this code causes significant performance degradation 2075 * and IRQ storms on BBB, Wandboard behaves fine. 2076 * Not using this code does no harm... 2077 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 2078 slot->flags |= STOP_STARTED; 2079 sdhci_start_command(slot, &mmcio->stop); 2080 return; 2081 } 2082 */ 2083 if (__predict_false(sdhci_debug > 1)) 2084 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 2085 if (mmcio->cmd.error == 0 && 2086 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 2087 sdhci_reset(slot, SDHCI_RESET_CMD); 2088 sdhci_reset(slot, SDHCI_RESET_DATA); 2089 } 2090 2091 sdhci_req_done(slot); 2092 } 2093 #else 2094 static void 2095 sdhci_start(struct sdhci_slot *slot) 2096 { 2097 const struct mmc_request *req; 2098 2099 req = slot->req; 2100 if (req == NULL) 2101 return; 2102 2103 if (!(slot->flags & CMD_STARTED)) { 2104 slot->flags |= CMD_STARTED; 2105 sdhci_start_command(slot, req->cmd); 2106 return; 2107 } 2108 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 2109 !(slot->flags & STOP_STARTED) && req->stop) { 2110 slot->flags |= STOP_STARTED; 2111 sdhci_start_command(slot, req->stop); 2112 return; 2113 } 2114 if (__predict_false(sdhci_debug > 1)) 2115 slot_printf(slot, "result: %d\n", req->cmd->error); 2116 if (!req->cmd->error && 2117 ((slot->curcmd == req->stop && 2118 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 2119 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2120 sdhci_reset(slot, SDHCI_RESET_CMD); 2121 sdhci_reset(slot, SDHCI_RESET_DATA); 2122 } 2123 2124 sdhci_req_done(slot); 2125 } 2126 #endif 2127 2128 int 2129 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 2130 struct mmc_request *req) 2131 { 2132 struct sdhci_slot *slot = device_get_ivars(reqdev); 2133 2134 SDHCI_LOCK(slot); 2135 if (slot->req != NULL) { 2136 SDHCI_UNLOCK(slot); 2137 return (EBUSY); 2138 } 2139 if (__predict_false(sdhci_debug > 1)) { 2140 slot_printf(slot, 2141 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2142 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 2143 (req->cmd->data)?(u_int)req->cmd->data->len:0, 2144 (req->cmd->data)?req->cmd->data->flags:0); 2145 } 2146 slot->req = req; 2147 slot->flags = 0; 2148 sdhci_start(slot); 2149 SDHCI_UNLOCK(slot); 2150 if (dumping) { 2151 while (slot->req != NULL) { 2152 sdhci_generic_intr(slot); 2153 DELAY(10); 2154 } 2155 } 2156 return (0); 2157 } 2158 2159 int 2160 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 2161 { 2162 struct sdhci_slot *slot = device_get_ivars(reqdev); 2163 uint32_t val; 2164 2165 SDHCI_LOCK(slot); 2166 val = RD4(slot, SDHCI_PRESENT_STATE); 2167 SDHCI_UNLOCK(slot); 2168 return (!(val & SDHCI_WRITE_PROTECT)); 2169 } 2170 2171 int 2172 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 2173 { 2174 struct sdhci_slot *slot = device_get_ivars(reqdev); 2175 int err = 0; 2176 2177 SDHCI_LOCK(slot); 2178 while (slot->bus_busy) 2179 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 2180 slot->bus_busy++; 2181 /* Activate led. */ 2182 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 2183 SDHCI_UNLOCK(slot); 2184 return (err); 2185 } 2186 2187 int 2188 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 2189 { 2190 struct sdhci_slot *slot = device_get_ivars(reqdev); 2191 2192 SDHCI_LOCK(slot); 2193 /* Deactivate led. */ 2194 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 2195 slot->bus_busy--; 2196 wakeup(slot); 2197 SDHCI_UNLOCK(slot); 2198 return (0); 2199 } 2200 2201 static void 2202 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2203 { 2204 2205 if (!slot->curcmd) { 2206 slot_printf(slot, "Got command interrupt 0x%08x, but " 2207 "there is no active command.\n", intmask); 2208 sdhci_dumpregs(slot); 2209 return; 2210 } 2211 if (intmask & SDHCI_INT_TIMEOUT) 2212 slot->curcmd->error = MMC_ERR_TIMEOUT; 2213 else if (intmask & SDHCI_INT_CRC) 2214 slot->curcmd->error = MMC_ERR_BADCRC; 2215 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2216 slot->curcmd->error = MMC_ERR_FIFO; 2217 2218 sdhci_finish_command(slot); 2219 } 2220 2221 static void 2222 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2223 { 2224 struct mmc_data *data; 2225 size_t left; 2226 uint32_t sdma_bbufsz; 2227 2228 if (!slot->curcmd) { 2229 slot_printf(slot, "Got data interrupt 0x%08x, but " 2230 "there is no active command.\n", intmask); 2231 sdhci_dumpregs(slot); 2232 return; 2233 } 2234 if (slot->curcmd->data == NULL && 2235 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2236 slot_printf(slot, "Got data interrupt 0x%08x, but " 2237 "there is no active data operation.\n", 2238 intmask); 2239 sdhci_dumpregs(slot); 2240 return; 2241 } 2242 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2243 slot->curcmd->error = MMC_ERR_TIMEOUT; 2244 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2245 slot->curcmd->error = MMC_ERR_BADCRC; 2246 if (slot->curcmd->data == NULL && 2247 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2248 SDHCI_INT_DMA_END))) { 2249 slot_printf(slot, "Got data interrupt 0x%08x, but " 2250 "there is busy-only command.\n", intmask); 2251 sdhci_dumpregs(slot); 2252 slot->curcmd->error = MMC_ERR_INVALID; 2253 } 2254 if (slot->curcmd->error) { 2255 /* No need to continue after any error. */ 2256 goto done; 2257 } 2258 2259 /* Handle tuning completion interrupt. */ 2260 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2261 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2262 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2263 slot->req->flags |= MMC_TUNE_DONE; 2264 sdhci_finish_command(slot); 2265 sdhci_finish_data(slot); 2266 return; 2267 } 2268 /* Handle PIO interrupt. */ 2269 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2270 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2271 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2272 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2273 &intmask); 2274 slot->flags |= PLATFORM_DATA_STARTED; 2275 } else 2276 sdhci_transfer_pio(slot); 2277 } 2278 /* Handle DMA border. */ 2279 if (intmask & SDHCI_INT_DMA_END) { 2280 data = slot->curcmd->data; 2281 sdma_bbufsz = slot->sdma_bbufsz; 2282 2283 /* Unload DMA buffer ... */ 2284 left = data->len - slot->offset; 2285 if (data->flags & MMC_DATA_READ) { 2286 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2287 BUS_DMASYNC_POSTREAD); 2288 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2289 ulmin(left, sdma_bbufsz)); 2290 } else { 2291 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2292 BUS_DMASYNC_POSTWRITE); 2293 } 2294 /* ... and reload it again. */ 2295 slot->offset += sdma_bbufsz; 2296 left = data->len - slot->offset; 2297 if (data->flags & MMC_DATA_READ) { 2298 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2299 BUS_DMASYNC_PREREAD); 2300 } else { 2301 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2302 ulmin(left, sdma_bbufsz)); 2303 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2304 BUS_DMASYNC_PREWRITE); 2305 } 2306 /* 2307 * Interrupt aggregation: Mask border interrupt for the last 2308 * bounce buffer. 2309 */ 2310 if (left == sdma_bbufsz) { 2311 slot->intmask &= ~SDHCI_INT_DMA_END; 2312 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2313 } 2314 /* Restart DMA. */ 2315 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2316 } 2317 /* We have got all data. */ 2318 if (intmask & SDHCI_INT_DATA_END) { 2319 if (slot->flags & PLATFORM_DATA_STARTED) { 2320 slot->flags &= ~PLATFORM_DATA_STARTED; 2321 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2322 } else 2323 sdhci_finish_data(slot); 2324 } 2325 done: 2326 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2327 if (slot->flags & PLATFORM_DATA_STARTED) { 2328 slot->flags &= ~PLATFORM_DATA_STARTED; 2329 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2330 } else 2331 sdhci_finish_data(slot); 2332 } 2333 } 2334 2335 static void 2336 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) 2337 { 2338 2339 if (!slot->curcmd) { 2340 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2341 "there is no active command.\n", acmd_err); 2342 sdhci_dumpregs(slot); 2343 return; 2344 } 2345 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err); 2346 sdhci_reset(slot, SDHCI_RESET_CMD); 2347 } 2348 2349 void 2350 sdhci_generic_intr(struct sdhci_slot *slot) 2351 { 2352 uint32_t intmask, present; 2353 uint16_t val16; 2354 2355 SDHCI_LOCK(slot); 2356 /* Read slot interrupt status. */ 2357 intmask = RD4(slot, SDHCI_INT_STATUS); 2358 if (intmask == 0 || intmask == 0xffffffff) { 2359 SDHCI_UNLOCK(slot); 2360 return; 2361 } 2362 if (__predict_false(sdhci_debug > 2)) 2363 slot_printf(slot, "Interrupt %#x\n", intmask); 2364 2365 /* Handle tuning error interrupt. */ 2366 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2367 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR); 2368 slot_printf(slot, "Tuning error indicated\n"); 2369 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2370 if (slot->curcmd) { 2371 slot->curcmd->error = MMC_ERR_BADCRC; 2372 sdhci_finish_command(slot); 2373 } 2374 } 2375 /* Handle re-tuning interrupt. */ 2376 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2377 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2378 /* Handle card presence interrupts. */ 2379 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2380 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2381 slot->intmask &= 2382 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2383 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2384 SDHCI_INT_CARD_INSERT; 2385 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2386 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2387 WR4(slot, SDHCI_INT_STATUS, intmask & 2388 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2389 sdhci_handle_card_present_locked(slot, present); 2390 } 2391 /* Handle command interrupts. */ 2392 if (intmask & SDHCI_INT_CMD_MASK) { 2393 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2394 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2395 } 2396 /* Handle data interrupts. */ 2397 if (intmask & SDHCI_INT_DATA_MASK) { 2398 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2399 /* Don't call data_irq in case of errored command. */ 2400 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2401 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2402 } 2403 /* Handle AutoCMD12 error interrupt. */ 2404 if (intmask & SDHCI_INT_ACMD12ERR) { 2405 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */ 2406 val16 = RD2(slot, SDHCI_ACMD12_ERR); 2407 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2408 sdhci_acmd_irq(slot, val16); 2409 } 2410 /* Handle bus power interrupt. */ 2411 if (intmask & SDHCI_INT_BUS_POWER) { 2412 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2413 slot_printf(slot, "Card is consuming too much power!\n"); 2414 } 2415 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2416 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2417 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2418 /* The rest is unknown. */ 2419 if (intmask) { 2420 WR4(slot, SDHCI_INT_STATUS, intmask); 2421 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2422 intmask); 2423 sdhci_dumpregs(slot); 2424 } 2425 2426 SDHCI_UNLOCK(slot); 2427 } 2428 2429 int 2430 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2431 uintptr_t *result) 2432 { 2433 const struct sdhci_slot *slot = device_get_ivars(child); 2434 2435 switch (which) { 2436 default: 2437 return (EINVAL); 2438 case MMCBR_IVAR_BUS_MODE: 2439 *result = slot->host.ios.bus_mode; 2440 break; 2441 case MMCBR_IVAR_BUS_WIDTH: 2442 *result = slot->host.ios.bus_width; 2443 break; 2444 case MMCBR_IVAR_CHIP_SELECT: 2445 *result = slot->host.ios.chip_select; 2446 break; 2447 case MMCBR_IVAR_CLOCK: 2448 *result = slot->host.ios.clock; 2449 break; 2450 case MMCBR_IVAR_F_MIN: 2451 *result = slot->host.f_min; 2452 break; 2453 case MMCBR_IVAR_F_MAX: 2454 *result = slot->host.f_max; 2455 break; 2456 case MMCBR_IVAR_HOST_OCR: 2457 *result = slot->host.host_ocr; 2458 break; 2459 case MMCBR_IVAR_MODE: 2460 *result = slot->host.mode; 2461 break; 2462 case MMCBR_IVAR_OCR: 2463 *result = slot->host.ocr; 2464 break; 2465 case MMCBR_IVAR_POWER_MODE: 2466 *result = slot->host.ios.power_mode; 2467 break; 2468 case MMCBR_IVAR_VDD: 2469 *result = slot->host.ios.vdd; 2470 break; 2471 case MMCBR_IVAR_RETUNE_REQ: 2472 if (slot->opt & SDHCI_TUNING_ENABLED) { 2473 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2474 *result = retune_req_reset; 2475 break; 2476 } 2477 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2478 *result = retune_req_normal; 2479 break; 2480 } 2481 } 2482 *result = retune_req_none; 2483 break; 2484 case MMCBR_IVAR_VCCQ: 2485 *result = slot->host.ios.vccq; 2486 break; 2487 case MMCBR_IVAR_CAPS: 2488 *result = slot->host.caps; 2489 break; 2490 case MMCBR_IVAR_TIMING: 2491 *result = slot->host.ios.timing; 2492 break; 2493 case MMCBR_IVAR_MAX_DATA: 2494 /* 2495 * Re-tuning modes 1 and 2 restrict the maximum data length 2496 * per read/write command to 4 MiB. 2497 */ 2498 if (slot->opt & SDHCI_TUNING_ENABLED && 2499 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2500 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2501 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2502 break; 2503 } 2504 *result = 65535; 2505 break; 2506 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2507 /* 2508 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2509 */ 2510 *result = 1000000; 2511 break; 2512 } 2513 return (0); 2514 } 2515 2516 int 2517 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2518 uintptr_t value) 2519 { 2520 struct sdhci_slot *slot = device_get_ivars(child); 2521 uint32_t clock, max_clock; 2522 int i; 2523 2524 if (sdhci_debug > 1) 2525 slot_printf(slot, "%s: var=%d\n", __func__, which); 2526 switch (which) { 2527 default: 2528 return (EINVAL); 2529 case MMCBR_IVAR_BUS_MODE: 2530 slot->host.ios.bus_mode = value; 2531 break; 2532 case MMCBR_IVAR_BUS_WIDTH: 2533 slot->host.ios.bus_width = value; 2534 break; 2535 case MMCBR_IVAR_CHIP_SELECT: 2536 slot->host.ios.chip_select = value; 2537 break; 2538 case MMCBR_IVAR_CLOCK: 2539 if (value > 0) { 2540 max_clock = slot->max_clk; 2541 clock = max_clock; 2542 2543 if (slot->version < SDHCI_SPEC_300) { 2544 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2545 i <<= 1) { 2546 if (clock <= value) 2547 break; 2548 clock >>= 1; 2549 } 2550 } else { 2551 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2552 i += 2) { 2553 if (clock <= value) 2554 break; 2555 clock = max_clock / (i + 2); 2556 } 2557 } 2558 2559 slot->host.ios.clock = clock; 2560 } else 2561 slot->host.ios.clock = 0; 2562 break; 2563 case MMCBR_IVAR_MODE: 2564 slot->host.mode = value; 2565 break; 2566 case MMCBR_IVAR_OCR: 2567 slot->host.ocr = value; 2568 break; 2569 case MMCBR_IVAR_POWER_MODE: 2570 slot->host.ios.power_mode = value; 2571 break; 2572 case MMCBR_IVAR_VDD: 2573 slot->host.ios.vdd = value; 2574 break; 2575 case MMCBR_IVAR_VCCQ: 2576 slot->host.ios.vccq = value; 2577 break; 2578 case MMCBR_IVAR_TIMING: 2579 slot->host.ios.timing = value; 2580 break; 2581 case MMCBR_IVAR_CAPS: 2582 case MMCBR_IVAR_HOST_OCR: 2583 case MMCBR_IVAR_F_MIN: 2584 case MMCBR_IVAR_F_MAX: 2585 case MMCBR_IVAR_MAX_DATA: 2586 case MMCBR_IVAR_RETUNE_REQ: 2587 return (EINVAL); 2588 } 2589 return (0); 2590 } 2591 2592 #ifdef MMCCAM 2593 void 2594 sdhci_start_slot(struct sdhci_slot *slot) 2595 { 2596 2597 if ((slot->devq = cam_simq_alloc(1)) == NULL) 2598 goto fail; 2599 2600 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2601 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2602 "sdhci_slot", slot, device_get_unit(slot->bus), 2603 &slot->sim_mtx, 1, 1, slot->devq); 2604 2605 if (slot->sim == NULL) { 2606 cam_simq_free(slot->devq); 2607 slot_printf(slot, "cannot allocate CAM SIM\n"); 2608 goto fail; 2609 } 2610 2611 mtx_lock(&slot->sim_mtx); 2612 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2613 slot_printf(slot, "cannot register SCSI pass-through bus\n"); 2614 cam_sim_free(slot->sim, FALSE); 2615 cam_simq_free(slot->devq); 2616 mtx_unlock(&slot->sim_mtx); 2617 goto fail; 2618 } 2619 mtx_unlock(&slot->sim_mtx); 2620 2621 /* End CAM-specific init */ 2622 slot->card_present = 0; 2623 sdhci_card_task(slot, 0); 2624 return; 2625 2626 fail: 2627 if (slot->sim != NULL) { 2628 mtx_lock(&slot->sim_mtx); 2629 xpt_bus_deregister(cam_sim_path(slot->sim)); 2630 cam_sim_free(slot->sim, FALSE); 2631 mtx_unlock(&slot->sim_mtx); 2632 } 2633 2634 if (slot->devq != NULL) 2635 cam_simq_free(slot->devq); 2636 } 2637 2638 void 2639 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2640 { 2641 struct sdhci_slot *slot; 2642 2643 slot = cam_sim_softc(sim); 2644 if (slot == NULL) { 2645 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2646 xpt_done(ccb); 2647 return; 2648 } 2649 2650 mtx_assert(&slot->sim_mtx, MA_OWNED); 2651 2652 switch (ccb->ccb_h.func_code) { 2653 case XPT_PATH_INQ: 2654 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, maxphys); 2655 break; 2656 2657 case XPT_MMC_GET_TRAN_SETTINGS: 2658 case XPT_GET_TRAN_SETTINGS: 2659 { 2660 struct ccb_trans_settings *cts = &ccb->cts; 2661 uint32_t max_data; 2662 2663 if (sdhci_debug > 1) 2664 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2665 2666 cts->protocol = PROTO_MMCSD; 2667 cts->protocol_version = 1; 2668 cts->transport = XPORT_MMCSD; 2669 cts->transport_version = 1; 2670 cts->xport_specific.valid = 0; 2671 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2672 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2673 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2674 cts->proto_specific.mmc.host_caps = slot->host.caps; 2675 /* 2676 * Re-tuning modes 1 and 2 restrict the maximum data length 2677 * per read/write command to 4 MiB. 2678 */ 2679 if (slot->opt & SDHCI_TUNING_ENABLED && 2680 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2681 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2682 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2683 } else { 2684 max_data = 65535; 2685 } 2686 cts->proto_specific.mmc.host_max_data = max_data; 2687 2688 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2689 ccb->ccb_h.status = CAM_REQ_CMP; 2690 break; 2691 } 2692 case XPT_MMC_SET_TRAN_SETTINGS: 2693 case XPT_SET_TRAN_SETTINGS: 2694 if (sdhci_debug > 1) 2695 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2696 sdhci_cam_settran_settings(slot, ccb); 2697 ccb->ccb_h.status = CAM_REQ_CMP; 2698 break; 2699 case XPT_RESET_BUS: 2700 if (sdhci_debug > 1) 2701 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2702 ccb->ccb_h.status = CAM_REQ_CMP; 2703 break; 2704 case XPT_MMC_IO: 2705 /* 2706 * Here is the HW-dependent part of 2707 * sending the command to the underlying h/w 2708 * At some point in the future an interrupt comes. 2709 * Then the request will be marked as completed. 2710 */ 2711 if (__predict_false(sdhci_debug > 1)) 2712 slot_printf(slot, "Got XPT_MMC_IO\n"); 2713 ccb->ccb_h.status = CAM_REQ_INPROG; 2714 2715 sdhci_cam_request(cam_sim_softc(sim), ccb); 2716 return; 2717 default: 2718 ccb->ccb_h.status = CAM_REQ_INVALID; 2719 break; 2720 } 2721 xpt_done(ccb); 2722 return; 2723 } 2724 2725 void 2726 sdhci_cam_poll(struct cam_sim *sim) 2727 { 2728 return; 2729 } 2730 2731 static int 2732 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 2733 int proposed_clock) 2734 { 2735 int max_clock, clock, i; 2736 2737 if (proposed_clock == 0) 2738 return 0; 2739 max_clock = slot->max_clk; 2740 clock = max_clock; 2741 2742 if (slot->version < SDHCI_SPEC_300) { 2743 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) { 2744 if (clock <= proposed_clock) 2745 break; 2746 clock >>= 1; 2747 } 2748 } else { 2749 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) { 2750 if (clock <= proposed_clock) 2751 break; 2752 clock = max_clock / (i + 2); 2753 } 2754 } 2755 return clock; 2756 } 2757 2758 static int 2759 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2760 { 2761 struct mmc_ios *ios; 2762 const struct mmc_ios *new_ios; 2763 const struct ccb_trans_settings_mmc *cts; 2764 2765 ios = &slot->host.ios; 2766 cts = &ccb->cts.proto_specific.mmc; 2767 new_ios = &cts->ios; 2768 2769 /* Update only requested fields */ 2770 if (cts->ios_valid & MMC_CLK) { 2771 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2772 if (sdhci_debug > 1) 2773 slot_printf(slot, "Clock => %d\n", ios->clock); 2774 } 2775 if (cts->ios_valid & MMC_VDD) { 2776 ios->vdd = new_ios->vdd; 2777 if (sdhci_debug > 1) 2778 slot_printf(slot, "VDD => %d\n", ios->vdd); 2779 } 2780 if (cts->ios_valid & MMC_CS) { 2781 ios->chip_select = new_ios->chip_select; 2782 if (sdhci_debug > 1) 2783 slot_printf(slot, "CS => %d\n", ios->chip_select); 2784 } 2785 if (cts->ios_valid & MMC_BW) { 2786 ios->bus_width = new_ios->bus_width; 2787 if (sdhci_debug > 1) 2788 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2789 } 2790 if (cts->ios_valid & MMC_PM) { 2791 ios->power_mode = new_ios->power_mode; 2792 if (sdhci_debug > 1) 2793 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2794 } 2795 if (cts->ios_valid & MMC_BT) { 2796 ios->timing = new_ios->timing; 2797 if (sdhci_debug > 1) 2798 slot_printf(slot, "Timing => %d\n", ios->timing); 2799 } 2800 if (cts->ios_valid & MMC_BM) { 2801 ios->bus_mode = new_ios->bus_mode; 2802 if (sdhci_debug > 1) 2803 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2804 } 2805 if (cts->ios_valid & MMC_VCCQ) { 2806 ios->vccq = new_ios->vccq; 2807 if (sdhci_debug > 1) 2808 slot_printf(slot, "VCCQ => %d\n", ios->vccq); 2809 } 2810 2811 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2812 return (sdhci_cam_update_ios(slot)); 2813 } 2814 2815 static int 2816 sdhci_cam_update_ios(struct sdhci_slot *slot) 2817 { 2818 struct mmc_ios *ios = &slot->host.ios; 2819 2820 if (sdhci_debug > 1) 2821 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2822 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2823 SDHCI_LOCK(slot); 2824 /* Do full reset on bus power down to clear from any state. */ 2825 if (ios->power_mode == power_off) { 2826 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2827 sdhci_init(slot); 2828 } 2829 /* Configure the bus. */ 2830 sdhci_set_clock(slot, ios->clock); 2831 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2832 if (ios->bus_width == bus_width_8) { 2833 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2834 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2835 } else if (ios->bus_width == bus_width_4) { 2836 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2837 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2838 } else if (ios->bus_width == bus_width_1) { 2839 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2840 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2841 } else { 2842 panic("Invalid bus width: %d", ios->bus_width); 2843 } 2844 if (ios->timing == bus_timing_hs && 2845 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2846 slot->hostctrl |= SDHCI_CTRL_HISPD; 2847 else 2848 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2849 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2850 /* Some controllers like reset after bus changes. */ 2851 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2852 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2853 2854 SDHCI_UNLOCK(slot); 2855 return (0); 2856 } 2857 2858 static int 2859 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2860 { 2861 const struct ccb_mmcio *mmcio; 2862 2863 mmcio = &ccb->mmcio; 2864 2865 SDHCI_LOCK(slot); 2866 /* if (slot->req != NULL) { 2867 SDHCI_UNLOCK(slot); 2868 return (EBUSY); 2869 } 2870 */ 2871 if (__predict_false(sdhci_debug > 1)) { 2872 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x " 2873 "blksz=%zu blkcnt=%zu\n", 2874 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2875 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2876 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0, 2877 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0, 2878 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0); 2879 } 2880 if (mmcio->cmd.data != NULL) { 2881 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2882 panic("data->len = %d, data->flags = %d -- something is b0rked", 2883 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2884 } 2885 slot->ccb = ccb; 2886 slot->flags = 0; 2887 sdhci_start(slot); 2888 SDHCI_UNLOCK(slot); 2889 if (dumping) { 2890 while (slot->ccb != NULL) { 2891 sdhci_generic_intr(slot); 2892 DELAY(10); 2893 } 2894 } 2895 return (0); 2896 } 2897 #endif /* MMCCAM */ 2898 2899 MODULE_VERSION(sdhci, SDHCI_VERSION); 2900