1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 59 "Debug level"); 60 61 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 62 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 64 #define RD_MULTI_4(slot, off, ptr, count) \ 65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 66 67 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 68 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 70 #define WR_MULTI_4(slot, off, ptr, count) \ 71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 72 73 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 74 static void sdhci_start(struct sdhci_slot *slot); 75 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 76 77 static void sdhci_card_poll(void *); 78 static void sdhci_card_task(void *, int); 79 80 /* helper routines */ 81 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 82 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 83 #define SDHCI_LOCK_INIT(_slot) \ 84 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 85 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 86 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 87 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 88 89 #define SDHCI_DEFAULT_MAX_FREQ 50 90 91 #define SDHCI_200_MAX_DIVIDER 256 92 #define SDHCI_300_MAX_DIVIDER 2046 93 94 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 95 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 96 97 /* 98 * Broadcom BCM577xx Controller Constants 99 */ 100 /* Maximum divider supported by the default clock source. */ 101 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 102 /* Alternative clock's base frequency. */ 103 #define BCM577XX_ALT_CLOCK_BASE 63000000 104 105 #define BCM577XX_HOST_CONTROL 0x198 106 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 107 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 108 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 109 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 110 111 static void 112 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 113 { 114 115 if (error != 0) { 116 printf("getaddr: error %d\n", error); 117 return; 118 } 119 *(bus_addr_t *)arg = segs[0].ds_addr; 120 } 121 122 static int 123 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 124 { 125 va_list ap; 126 int retval; 127 128 retval = printf("%s-slot%d: ", 129 device_get_nameunit(slot->bus), slot->num); 130 131 va_start(ap, fmt); 132 retval += vprintf(fmt, ap); 133 va_end(ap); 134 return (retval); 135 } 136 137 static void 138 sdhci_dumpregs(struct sdhci_slot *slot) 139 { 140 141 slot_printf(slot, 142 "============== REGISTER DUMP ==============\n"); 143 144 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 145 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 146 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 147 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 148 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 149 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 150 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 151 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 152 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 153 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 154 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 155 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 156 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 157 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 158 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 159 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 160 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 161 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 162 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 163 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 164 165 slot_printf(slot, 166 "===========================================\n"); 167 } 168 169 static void 170 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 171 { 172 int timeout; 173 uint32_t clock; 174 175 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 176 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 177 return; 178 } 179 180 /* Some controllers need this kick or reset won't work. */ 181 if ((mask & SDHCI_RESET_ALL) == 0 && 182 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 183 /* This is to force an update */ 184 clock = slot->clock; 185 slot->clock = 0; 186 sdhci_set_clock(slot, clock); 187 } 188 189 if (mask & SDHCI_RESET_ALL) { 190 slot->clock = 0; 191 slot->power = 0; 192 } 193 194 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 195 196 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 197 /* 198 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 199 * specification. The reset bit has internal propagation delay, 200 * so a fast read after write returns 0 even if reset process is 201 * in progress. The workaround is to poll for 1 before polling 202 * for 0. In the worst case, if we miss seeing it asserted the 203 * time we spent waiting is enough to ensure the reset finishes. 204 */ 205 timeout = 10000; 206 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 207 if (timeout <= 0) 208 break; 209 timeout--; 210 DELAY(1); 211 } 212 } 213 214 /* Wait max 100 ms */ 215 timeout = 10000; 216 /* Controller clears the bits when it's done */ 217 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 218 if (timeout <= 0) { 219 slot_printf(slot, "Reset 0x%x never completed.\n", 220 mask); 221 sdhci_dumpregs(slot); 222 return; 223 } 224 timeout--; 225 DELAY(10); 226 } 227 } 228 229 static void 230 sdhci_init(struct sdhci_slot *slot) 231 { 232 233 sdhci_reset(slot, SDHCI_RESET_ALL); 234 235 /* Enable interrupts. */ 236 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 238 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 239 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 240 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 241 SDHCI_INT_ACMD12ERR; 242 243 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 244 !(slot->opt & SDHCI_NON_REMOVABLE)) { 245 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 246 } 247 248 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 249 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 250 } 251 252 static void 253 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 254 { 255 uint32_t clk_base; 256 uint32_t clk_sel; 257 uint32_t res; 258 uint16_t clk; 259 uint16_t div; 260 int timeout; 261 262 if (clock == slot->clock) 263 return; 264 slot->clock = clock; 265 266 /* Turn off the clock. */ 267 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 268 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 269 /* If no clock requested - leave it so. */ 270 if (clock == 0) 271 return; 272 273 /* Determine the clock base frequency */ 274 clk_base = slot->max_clk; 275 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 276 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 277 BCM577XX_CTRL_CLKSEL_MASK; 278 279 /* 280 * Select clock source appropriate for the requested frequency. 281 */ 282 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 283 clk_base = BCM577XX_ALT_CLOCK_BASE; 284 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 285 BCM577XX_CTRL_CLKSEL_SHIFT); 286 } else { 287 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 288 BCM577XX_CTRL_CLKSEL_SHIFT); 289 } 290 291 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 292 } 293 294 /* Recalculate timeout clock frequency based on the new sd clock. */ 295 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 296 slot->timeout_clk = slot->clock / 1000; 297 298 if (slot->version < SDHCI_SPEC_300) { 299 /* Looking for highest freq <= clock. */ 300 res = clk_base; 301 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 302 if (res <= clock) 303 break; 304 res >>= 1; 305 } 306 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 307 div >>= 1; 308 } 309 else { 310 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 311 if (clock >= clk_base) 312 div = 0; 313 else { 314 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 315 if ((clk_base / div) <= clock) 316 break; 317 } 318 } 319 div >>= 1; 320 } 321 322 if (bootverbose || sdhci_debug) 323 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 324 div, clock, clk_base); 325 326 /* Now we have got divider, set it. */ 327 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 328 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 329 << SDHCI_DIVIDER_HI_SHIFT; 330 331 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 332 /* Enable clock. */ 333 clk |= SDHCI_CLOCK_INT_EN; 334 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 335 /* Wait up to 10 ms until it stabilize. */ 336 timeout = 10; 337 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 338 & SDHCI_CLOCK_INT_STABLE)) { 339 if (timeout == 0) { 340 slot_printf(slot, 341 "Internal clock never stabilised.\n"); 342 sdhci_dumpregs(slot); 343 return; 344 } 345 timeout--; 346 DELAY(1000); 347 } 348 /* Pass clock signal to the bus. */ 349 clk |= SDHCI_CLOCK_CARD_EN; 350 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 351 } 352 353 static void 354 sdhci_set_power(struct sdhci_slot *slot, u_char power) 355 { 356 uint8_t pwr; 357 358 if (slot->power == power) 359 return; 360 361 slot->power = power; 362 363 /* Turn off the power. */ 364 pwr = 0; 365 WR1(slot, SDHCI_POWER_CONTROL, pwr); 366 /* If power down requested - leave it so. */ 367 if (power == 0) 368 return; 369 /* Set voltage. */ 370 switch (1 << power) { 371 case MMC_OCR_LOW_VOLTAGE: 372 pwr |= SDHCI_POWER_180; 373 break; 374 case MMC_OCR_290_300: 375 case MMC_OCR_300_310: 376 pwr |= SDHCI_POWER_300; 377 break; 378 case MMC_OCR_320_330: 379 case MMC_OCR_330_340: 380 pwr |= SDHCI_POWER_330; 381 break; 382 } 383 WR1(slot, SDHCI_POWER_CONTROL, pwr); 384 /* Turn on the power. */ 385 pwr |= SDHCI_POWER_ON; 386 WR1(slot, SDHCI_POWER_CONTROL, pwr); 387 388 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 389 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 390 DELAY(10); 391 WR1(slot, SDHCI_POWER_CONTROL, pwr); 392 DELAY(300); 393 } 394 } 395 396 static void 397 sdhci_read_block_pio(struct sdhci_slot *slot) 398 { 399 uint32_t data; 400 char *buffer; 401 size_t left; 402 403 buffer = slot->curcmd->data->data; 404 buffer += slot->offset; 405 /* Transfer one block at a time. */ 406 left = min(512, slot->curcmd->data->len - slot->offset); 407 slot->offset += left; 408 409 /* If we are too fast, broken controllers return zeroes. */ 410 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 411 DELAY(10); 412 /* Handle unaligned and aligned buffer cases. */ 413 if ((intptr_t)buffer & 3) { 414 while (left > 3) { 415 data = RD4(slot, SDHCI_BUFFER); 416 buffer[0] = data; 417 buffer[1] = (data >> 8); 418 buffer[2] = (data >> 16); 419 buffer[3] = (data >> 24); 420 buffer += 4; 421 left -= 4; 422 } 423 } else { 424 RD_MULTI_4(slot, SDHCI_BUFFER, 425 (uint32_t *)buffer, left >> 2); 426 left &= 3; 427 } 428 /* Handle uneven size case. */ 429 if (left > 0) { 430 data = RD4(slot, SDHCI_BUFFER); 431 while (left > 0) { 432 *(buffer++) = data; 433 data >>= 8; 434 left--; 435 } 436 } 437 } 438 439 static void 440 sdhci_write_block_pio(struct sdhci_slot *slot) 441 { 442 uint32_t data = 0; 443 char *buffer; 444 size_t left; 445 446 buffer = slot->curcmd->data->data; 447 buffer += slot->offset; 448 /* Transfer one block at a time. */ 449 left = min(512, slot->curcmd->data->len - slot->offset); 450 slot->offset += left; 451 452 /* Handle unaligned and aligned buffer cases. */ 453 if ((intptr_t)buffer & 3) { 454 while (left > 3) { 455 data = buffer[0] + 456 (buffer[1] << 8) + 457 (buffer[2] << 16) + 458 (buffer[3] << 24); 459 left -= 4; 460 buffer += 4; 461 WR4(slot, SDHCI_BUFFER, data); 462 } 463 } else { 464 WR_MULTI_4(slot, SDHCI_BUFFER, 465 (uint32_t *)buffer, left >> 2); 466 left &= 3; 467 } 468 /* Handle uneven size case. */ 469 if (left > 0) { 470 while (left > 0) { 471 data <<= 8; 472 data += *(buffer++); 473 left--; 474 } 475 WR4(slot, SDHCI_BUFFER, data); 476 } 477 } 478 479 static void 480 sdhci_transfer_pio(struct sdhci_slot *slot) 481 { 482 483 /* Read as many blocks as possible. */ 484 if (slot->curcmd->data->flags & MMC_DATA_READ) { 485 while (RD4(slot, SDHCI_PRESENT_STATE) & 486 SDHCI_DATA_AVAILABLE) { 487 sdhci_read_block_pio(slot); 488 if (slot->offset >= slot->curcmd->data->len) 489 break; 490 } 491 } else { 492 while (RD4(slot, SDHCI_PRESENT_STATE) & 493 SDHCI_SPACE_AVAILABLE) { 494 sdhci_write_block_pio(slot); 495 if (slot->offset >= slot->curcmd->data->len) 496 break; 497 } 498 } 499 } 500 501 static void 502 sdhci_card_task(void *arg, int pending __unused) 503 { 504 struct sdhci_slot *slot = arg; 505 device_t d; 506 507 SDHCI_LOCK(slot); 508 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 509 if (slot->dev == NULL) { 510 /* If card is present - attach mmc bus. */ 511 if (bootverbose || sdhci_debug) 512 slot_printf(slot, "Card inserted\n"); 513 slot->dev = device_add_child(slot->bus, "mmc", -1); 514 device_set_ivars(slot->dev, slot); 515 SDHCI_UNLOCK(slot); 516 device_probe_and_attach(slot->dev); 517 } else 518 SDHCI_UNLOCK(slot); 519 } else { 520 if (slot->dev != NULL) { 521 /* If no card present - detach mmc bus. */ 522 if (bootverbose || sdhci_debug) 523 slot_printf(slot, "Card removed\n"); 524 d = slot->dev; 525 slot->dev = NULL; 526 SDHCI_UNLOCK(slot); 527 device_delete_child(slot->bus, d); 528 } else 529 SDHCI_UNLOCK(slot); 530 } 531 } 532 533 static void 534 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 535 { 536 bool was_present; 537 538 /* 539 * If there was no card and now there is one, schedule the task to 540 * create the child device after a short delay. The delay is to 541 * debounce the card insert (sometimes the card detect pin stabilizes 542 * before the other pins have made good contact). 543 * 544 * If there was a card present and now it's gone, immediately schedule 545 * the task to delete the child device. No debouncing -- gone is gone, 546 * because once power is removed, a full card re-init is needed, and 547 * that happens by deleting and recreating the child device. 548 */ 549 was_present = slot->dev != NULL; 550 if (!was_present && is_present) { 551 taskqueue_enqueue_timeout(taskqueue_swi_giant, 552 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 553 } else if (was_present && !is_present) { 554 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 555 } 556 } 557 558 void 559 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 560 { 561 562 SDHCI_LOCK(slot); 563 sdhci_handle_card_present_locked(slot, is_present); 564 SDHCI_UNLOCK(slot); 565 } 566 567 static void 568 sdhci_card_poll(void *arg) 569 { 570 struct sdhci_slot *slot = arg; 571 572 sdhci_handle_card_present(slot, 573 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 574 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 575 sdhci_card_poll, slot); 576 } 577 578 int 579 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 580 { 581 uint32_t caps, freq; 582 int err; 583 584 SDHCI_LOCK_INIT(slot); 585 slot->num = num; 586 slot->bus = dev; 587 588 /* Allocate DMA tag. */ 589 err = bus_dma_tag_create(bus_get_dma_tag(dev), 590 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 591 BUS_SPACE_MAXADDR, NULL, NULL, 592 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 593 BUS_DMA_ALLOCNOW, NULL, NULL, 594 &slot->dmatag); 595 if (err != 0) { 596 device_printf(dev, "Can't create DMA tag\n"); 597 SDHCI_LOCK_DESTROY(slot); 598 return (err); 599 } 600 /* Allocate DMA memory. */ 601 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 602 BUS_DMA_NOWAIT, &slot->dmamap); 603 if (err != 0) { 604 device_printf(dev, "Can't alloc DMA memory\n"); 605 SDHCI_LOCK_DESTROY(slot); 606 return (err); 607 } 608 /* Map the memory. */ 609 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 610 (void *)slot->dmamem, DMA_BLOCK_SIZE, 611 sdhci_getaddr, &slot->paddr, 0); 612 if (err != 0 || slot->paddr == 0) { 613 device_printf(dev, "Can't load DMA memory\n"); 614 SDHCI_LOCK_DESTROY(slot); 615 if (err) 616 return (err); 617 else 618 return (EFAULT); 619 } 620 621 /* Initialize slot. */ 622 sdhci_init(slot); 623 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 624 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 625 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 626 caps = slot->caps; 627 else 628 caps = RD4(slot, SDHCI_CAPABILITIES); 629 /* Calculate base clock frequency. */ 630 if (slot->version >= SDHCI_SPEC_300) 631 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 632 SDHCI_CLOCK_BASE_SHIFT; 633 else 634 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 635 SDHCI_CLOCK_BASE_SHIFT; 636 if (freq != 0) 637 slot->max_clk = freq * 1000000; 638 /* 639 * If the frequency wasn't in the capabilities and the hardware driver 640 * hasn't already set max_clk we're probably not going to work right 641 * with an assumption, so complain about it. 642 */ 643 if (slot->max_clk == 0) { 644 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 645 device_printf(dev, "Hardware doesn't specify base clock " 646 "frequency, using %dMHz as default.\n", 647 SDHCI_DEFAULT_MAX_FREQ); 648 } 649 /* Calculate/set timeout clock frequency. */ 650 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 651 slot->timeout_clk = slot->max_clk / 1000; 652 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 653 slot->timeout_clk = 1000; 654 } else { 655 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 656 SDHCI_TIMEOUT_CLK_SHIFT; 657 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 658 slot->timeout_clk *= 1000; 659 } 660 /* 661 * If the frequency wasn't in the capabilities and the hardware driver 662 * hasn't already set timeout_clk we'll probably work okay using the 663 * max timeout, but still mention it. 664 */ 665 if (slot->timeout_clk == 0) { 666 device_printf(dev, "Hardware doesn't specify timeout clock " 667 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 668 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 669 } 670 671 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 672 slot->host.f_max = slot->max_clk; 673 slot->host.host_ocr = 0; 674 if (caps & SDHCI_CAN_VDD_330) 675 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 676 if (caps & SDHCI_CAN_VDD_300) 677 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 678 if (caps & SDHCI_CAN_VDD_180) 679 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 680 if (slot->host.host_ocr == 0) { 681 device_printf(dev, "Hardware doesn't report any " 682 "support voltages.\n"); 683 } 684 slot->host.caps = MMC_CAP_4_BIT_DATA; 685 if (caps & SDHCI_CAN_DO_8BITBUS) 686 slot->host.caps |= MMC_CAP_8_BIT_DATA; 687 if (caps & SDHCI_CAN_DO_HISPD) 688 slot->host.caps |= MMC_CAP_HSPEED; 689 /* Decide if we have usable DMA. */ 690 if (caps & SDHCI_CAN_DO_DMA) 691 slot->opt |= SDHCI_HAVE_DMA; 692 693 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 694 slot->opt &= ~SDHCI_HAVE_DMA; 695 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 696 slot->opt |= SDHCI_HAVE_DMA; 697 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 698 slot->opt |= SDHCI_NON_REMOVABLE; 699 700 /* 701 * Use platform-provided transfer backend 702 * with PIO as a fallback mechanism 703 */ 704 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 705 slot->opt &= ~SDHCI_HAVE_DMA; 706 707 if (bootverbose || sdhci_debug) { 708 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 709 slot->max_clk / 1000000, 710 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 711 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 712 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" : 713 "1bit"), 714 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 715 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 716 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 717 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 718 sdhci_dumpregs(slot); 719 } 720 721 slot->timeout = 10; 722 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 723 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 724 "timeout", CTLFLAG_RW, &slot->timeout, 0, 725 "Maximum timeout for SDHCI transfers (in secs)"); 726 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 727 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 728 sdhci_card_task, slot); 729 callout_init(&slot->card_poll_callout, 1); 730 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 731 732 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 733 !(slot->opt & SDHCI_NON_REMOVABLE)) { 734 callout_reset(&slot->card_poll_callout, 735 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 736 } 737 738 return (0); 739 } 740 741 void 742 sdhci_start_slot(struct sdhci_slot *slot) 743 { 744 745 sdhci_card_task(slot, 0); 746 } 747 748 int 749 sdhci_cleanup_slot(struct sdhci_slot *slot) 750 { 751 device_t d; 752 753 callout_drain(&slot->timeout_callout); 754 callout_drain(&slot->card_poll_callout); 755 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 756 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 757 758 SDHCI_LOCK(slot); 759 d = slot->dev; 760 slot->dev = NULL; 761 SDHCI_UNLOCK(slot); 762 if (d != NULL) 763 device_delete_child(slot->bus, d); 764 765 SDHCI_LOCK(slot); 766 sdhci_reset(slot, SDHCI_RESET_ALL); 767 SDHCI_UNLOCK(slot); 768 bus_dmamap_unload(slot->dmatag, slot->dmamap); 769 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 770 bus_dma_tag_destroy(slot->dmatag); 771 772 SDHCI_LOCK_DESTROY(slot); 773 774 return (0); 775 } 776 777 int 778 sdhci_generic_suspend(struct sdhci_slot *slot) 779 { 780 781 sdhci_reset(slot, SDHCI_RESET_ALL); 782 783 return (0); 784 } 785 786 int 787 sdhci_generic_resume(struct sdhci_slot *slot) 788 { 789 790 sdhci_init(slot); 791 792 return (0); 793 } 794 795 uint32_t 796 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 797 { 798 799 if (slot->version >= SDHCI_SPEC_300) 800 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 801 else 802 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 803 } 804 805 bool 806 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 807 { 808 809 if (slot->opt & SDHCI_NON_REMOVABLE) 810 return true; 811 812 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 813 } 814 815 int 816 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 817 { 818 struct sdhci_slot *slot = device_get_ivars(reqdev); 819 struct mmc_ios *ios = &slot->host.ios; 820 821 SDHCI_LOCK(slot); 822 /* Do full reset on bus power down to clear from any state. */ 823 if (ios->power_mode == power_off) { 824 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 825 sdhci_init(slot); 826 } 827 /* Configure the bus. */ 828 sdhci_set_clock(slot, ios->clock); 829 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 830 if (ios->bus_width == bus_width_8) { 831 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 832 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 833 } else if (ios->bus_width == bus_width_4) { 834 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 835 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 836 } else if (ios->bus_width == bus_width_1) { 837 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 838 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 839 } else { 840 panic("Invalid bus width: %d", ios->bus_width); 841 } 842 if (ios->timing == bus_timing_hs && 843 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 844 slot->hostctrl |= SDHCI_CTRL_HISPD; 845 else 846 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 847 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 848 /* Some controllers like reset after bus changes. */ 849 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 850 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 851 852 SDHCI_UNLOCK(slot); 853 return (0); 854 } 855 856 static void 857 sdhci_req_done(struct sdhci_slot *slot) 858 { 859 struct mmc_request *req; 860 861 if (slot->req != NULL && slot->curcmd != NULL) { 862 callout_stop(&slot->timeout_callout); 863 req = slot->req; 864 slot->req = NULL; 865 slot->curcmd = NULL; 866 req->done(req); 867 } 868 } 869 870 static void 871 sdhci_timeout(void *arg) 872 { 873 struct sdhci_slot *slot = arg; 874 875 if (slot->curcmd != NULL) { 876 slot_printf(slot, " Controller timeout\n"); 877 sdhci_dumpregs(slot); 878 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 879 slot->curcmd->error = MMC_ERR_TIMEOUT; 880 sdhci_req_done(slot); 881 } else { 882 slot_printf(slot, " Spurious timeout - no active command\n"); 883 } 884 } 885 886 static void 887 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 888 { 889 uint16_t mode; 890 891 if (data == NULL) 892 return; 893 894 mode = SDHCI_TRNS_BLK_CNT_EN; 895 if (data->len > 512) 896 mode |= SDHCI_TRNS_MULTI; 897 if (data->flags & MMC_DATA_READ) 898 mode |= SDHCI_TRNS_READ; 899 if (slot->req->stop) 900 mode |= SDHCI_TRNS_ACMD12; 901 if (slot->flags & SDHCI_USE_DMA) 902 mode |= SDHCI_TRNS_DMA; 903 904 WR2(slot, SDHCI_TRANSFER_MODE, mode); 905 } 906 907 static void 908 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 909 { 910 int flags, timeout; 911 uint32_t mask; 912 913 slot->curcmd = cmd; 914 slot->cmd_done = 0; 915 916 cmd->error = MMC_ERR_NONE; 917 918 /* This flags combination is not supported by controller. */ 919 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 920 slot_printf(slot, "Unsupported response type!\n"); 921 cmd->error = MMC_ERR_FAILED; 922 sdhci_req_done(slot); 923 return; 924 } 925 926 /* 927 * Do not issue command if there is no card, clock or power. 928 * Controller will not detect timeout without clock active. 929 */ 930 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 931 slot->power == 0 || 932 slot->clock == 0) { 933 cmd->error = MMC_ERR_FAILED; 934 sdhci_req_done(slot); 935 return; 936 } 937 /* Always wait for free CMD bus. */ 938 mask = SDHCI_CMD_INHIBIT; 939 /* Wait for free DAT if we have data or busy signal. */ 940 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 941 mask |= SDHCI_DAT_INHIBIT; 942 /* We shouldn't wait for DAT for stop commands. */ 943 if (cmd == slot->req->stop) 944 mask &= ~SDHCI_DAT_INHIBIT; 945 /* 946 * Wait for bus no more then 250 ms. Typically there will be no wait 947 * here at all, but when writing a crash dump we may be bypassing the 948 * host platform's interrupt handler, and in some cases that handler 949 * may be working around hardware quirks such as not respecting r1b 950 * busy indications. In those cases, this wait-loop serves the purpose 951 * of waiting for the prior command and data transfers to be done, and 952 * SD cards are allowed to take up to 250ms for write and erase ops. 953 * (It's usually more like 20-30ms in the real world.) 954 */ 955 timeout = 250; 956 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 957 if (timeout == 0) { 958 slot_printf(slot, "Controller never released " 959 "inhibit bit(s).\n"); 960 sdhci_dumpregs(slot); 961 cmd->error = MMC_ERR_FAILED; 962 sdhci_req_done(slot); 963 return; 964 } 965 timeout--; 966 DELAY(1000); 967 } 968 969 /* Prepare command flags. */ 970 if (!(cmd->flags & MMC_RSP_PRESENT)) 971 flags = SDHCI_CMD_RESP_NONE; 972 else if (cmd->flags & MMC_RSP_136) 973 flags = SDHCI_CMD_RESP_LONG; 974 else if (cmd->flags & MMC_RSP_BUSY) 975 flags = SDHCI_CMD_RESP_SHORT_BUSY; 976 else 977 flags = SDHCI_CMD_RESP_SHORT; 978 if (cmd->flags & MMC_RSP_CRC) 979 flags |= SDHCI_CMD_CRC; 980 if (cmd->flags & MMC_RSP_OPCODE) 981 flags |= SDHCI_CMD_INDEX; 982 if (cmd->data) 983 flags |= SDHCI_CMD_DATA; 984 if (cmd->opcode == MMC_STOP_TRANSMISSION) 985 flags |= SDHCI_CMD_TYPE_ABORT; 986 /* Prepare data. */ 987 sdhci_start_data(slot, cmd->data); 988 /* 989 * Interrupt aggregation: To reduce total number of interrupts 990 * group response interrupt with data interrupt when possible. 991 * If there going to be data interrupt, mask response one. 992 */ 993 if (slot->data_done == 0) { 994 WR4(slot, SDHCI_SIGNAL_ENABLE, 995 slot->intmask &= ~SDHCI_INT_RESPONSE); 996 } 997 /* Set command argument. */ 998 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 999 /* Set data transfer mode. */ 1000 sdhci_set_transfer_mode(slot, cmd->data); 1001 /* Start command. */ 1002 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1003 /* Start timeout callout. */ 1004 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1005 sdhci_timeout, slot); 1006 } 1007 1008 static void 1009 sdhci_finish_command(struct sdhci_slot *slot) 1010 { 1011 int i; 1012 uint32_t val; 1013 uint8_t extra; 1014 1015 slot->cmd_done = 1; 1016 /* Interrupt aggregation: Restore command interrupt. 1017 * Main restore point for the case when command interrupt 1018 * happened first. */ 1019 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1020 /* In case of error - reset host and return. */ 1021 if (slot->curcmd->error) { 1022 sdhci_reset(slot, SDHCI_RESET_CMD); 1023 sdhci_reset(slot, SDHCI_RESET_DATA); 1024 sdhci_start(slot); 1025 return; 1026 } 1027 /* If command has response - fetch it. */ 1028 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1029 if (slot->curcmd->flags & MMC_RSP_136) { 1030 /* CRC is stripped so we need one byte shift. */ 1031 extra = 0; 1032 for (i = 0; i < 4; i++) { 1033 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1034 if (slot->quirks & 1035 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1036 slot->curcmd->resp[3 - i] = val; 1037 else { 1038 slot->curcmd->resp[3 - i] = 1039 (val << 8) | extra; 1040 extra = val >> 24; 1041 } 1042 } 1043 } else 1044 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1045 } 1046 /* If data ready - finish. */ 1047 if (slot->data_done) 1048 sdhci_start(slot); 1049 } 1050 1051 static void 1052 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1053 { 1054 uint32_t target_timeout, current_timeout; 1055 uint8_t div; 1056 1057 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1058 slot->data_done = 1; 1059 return; 1060 } 1061 1062 slot->data_done = 0; 1063 1064 /* Calculate and set data timeout.*/ 1065 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1066 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1067 div = 0xE; 1068 } else { 1069 target_timeout = 1000000; 1070 div = 0; 1071 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1072 while (current_timeout < target_timeout && div < 0xE) { 1073 ++div; 1074 current_timeout <<= 1; 1075 } 1076 /* Compensate for an off-by-one error in the CaFe chip.*/ 1077 if (div < 0xE && 1078 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1079 ++div; 1080 } 1081 } 1082 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1083 1084 if (data == NULL) 1085 return; 1086 1087 /* Use DMA if possible. */ 1088 if ((slot->opt & SDHCI_HAVE_DMA)) 1089 slot->flags |= SDHCI_USE_DMA; 1090 /* If data is small, broken DMA may return zeroes instead of data, */ 1091 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1092 (data->len <= 512)) 1093 slot->flags &= ~SDHCI_USE_DMA; 1094 /* Some controllers require even block sizes. */ 1095 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1096 ((data->len) & 0x3)) 1097 slot->flags &= ~SDHCI_USE_DMA; 1098 /* Load DMA buffer. */ 1099 if (slot->flags & SDHCI_USE_DMA) { 1100 if (data->flags & MMC_DATA_READ) 1101 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1102 BUS_DMASYNC_PREREAD); 1103 else { 1104 memcpy(slot->dmamem, data->data, 1105 (data->len < DMA_BLOCK_SIZE) ? 1106 data->len : DMA_BLOCK_SIZE); 1107 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1108 BUS_DMASYNC_PREWRITE); 1109 } 1110 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1111 /* Interrupt aggregation: Mask border interrupt 1112 * for the last page and unmask else. */ 1113 if (data->len == DMA_BLOCK_SIZE) 1114 slot->intmask &= ~SDHCI_INT_DMA_END; 1115 else 1116 slot->intmask |= SDHCI_INT_DMA_END; 1117 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1118 } 1119 /* Current data offset for both PIO and DMA. */ 1120 slot->offset = 0; 1121 /* Set block size and request IRQ on 4K border. */ 1122 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1123 (data->len < 512) ? data->len : 512)); 1124 /* Set block count. */ 1125 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1126 } 1127 1128 void 1129 sdhci_finish_data(struct sdhci_slot *slot) 1130 { 1131 struct mmc_data *data = slot->curcmd->data; 1132 size_t left; 1133 1134 /* Interrupt aggregation: Restore command interrupt. 1135 * Auxiliary restore point for the case when data interrupt 1136 * happened first. */ 1137 if (!slot->cmd_done) { 1138 WR4(slot, SDHCI_SIGNAL_ENABLE, 1139 slot->intmask |= SDHCI_INT_RESPONSE); 1140 } 1141 /* Unload rest of data from DMA buffer. */ 1142 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1143 if (data->flags & MMC_DATA_READ) { 1144 left = data->len - slot->offset; 1145 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1146 BUS_DMASYNC_POSTREAD); 1147 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1148 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1149 } else 1150 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1151 BUS_DMASYNC_POSTWRITE); 1152 } 1153 slot->data_done = 1; 1154 /* If there was error - reset the host. */ 1155 if (slot->curcmd->error) { 1156 sdhci_reset(slot, SDHCI_RESET_CMD); 1157 sdhci_reset(slot, SDHCI_RESET_DATA); 1158 sdhci_start(slot); 1159 return; 1160 } 1161 /* If we already have command response - finish. */ 1162 if (slot->cmd_done) 1163 sdhci_start(slot); 1164 } 1165 1166 static void 1167 sdhci_start(struct sdhci_slot *slot) 1168 { 1169 struct mmc_request *req; 1170 1171 req = slot->req; 1172 if (req == NULL) 1173 return; 1174 1175 if (!(slot->flags & CMD_STARTED)) { 1176 slot->flags |= CMD_STARTED; 1177 sdhci_start_command(slot, req->cmd); 1178 return; 1179 } 1180 /* We don't need this until using Auto-CMD12 feature 1181 if (!(slot->flags & STOP_STARTED) && req->stop) { 1182 slot->flags |= STOP_STARTED; 1183 sdhci_start_command(slot, req->stop); 1184 return; 1185 } 1186 */ 1187 if (sdhci_debug > 1) 1188 slot_printf(slot, "result: %d\n", req->cmd->error); 1189 if (!req->cmd->error && 1190 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1191 sdhci_reset(slot, SDHCI_RESET_CMD); 1192 sdhci_reset(slot, SDHCI_RESET_DATA); 1193 } 1194 1195 sdhci_req_done(slot); 1196 } 1197 1198 int 1199 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1200 struct mmc_request *req) 1201 { 1202 struct sdhci_slot *slot = device_get_ivars(reqdev); 1203 1204 SDHCI_LOCK(slot); 1205 if (slot->req != NULL) { 1206 SDHCI_UNLOCK(slot); 1207 return (EBUSY); 1208 } 1209 if (sdhci_debug > 1) { 1210 slot_printf(slot, 1211 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1212 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1213 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1214 (req->cmd->data)?req->cmd->data->flags:0); 1215 } 1216 slot->req = req; 1217 slot->flags = 0; 1218 sdhci_start(slot); 1219 SDHCI_UNLOCK(slot); 1220 if (dumping) { 1221 while (slot->req != NULL) { 1222 sdhci_generic_intr(slot); 1223 DELAY(10); 1224 } 1225 } 1226 return (0); 1227 } 1228 1229 int 1230 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1231 { 1232 struct sdhci_slot *slot = device_get_ivars(reqdev); 1233 uint32_t val; 1234 1235 SDHCI_LOCK(slot); 1236 val = RD4(slot, SDHCI_PRESENT_STATE); 1237 SDHCI_UNLOCK(slot); 1238 return (!(val & SDHCI_WRITE_PROTECT)); 1239 } 1240 1241 int 1242 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1243 { 1244 struct sdhci_slot *slot = device_get_ivars(reqdev); 1245 int err = 0; 1246 1247 SDHCI_LOCK(slot); 1248 while (slot->bus_busy) 1249 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1250 slot->bus_busy++; 1251 /* Activate led. */ 1252 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1253 SDHCI_UNLOCK(slot); 1254 return (err); 1255 } 1256 1257 int 1258 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1259 { 1260 struct sdhci_slot *slot = device_get_ivars(reqdev); 1261 1262 SDHCI_LOCK(slot); 1263 /* Deactivate led. */ 1264 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1265 slot->bus_busy--; 1266 SDHCI_UNLOCK(slot); 1267 wakeup(slot); 1268 return (0); 1269 } 1270 1271 static void 1272 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1273 { 1274 1275 if (!slot->curcmd) { 1276 slot_printf(slot, "Got command interrupt 0x%08x, but " 1277 "there is no active command.\n", intmask); 1278 sdhci_dumpregs(slot); 1279 return; 1280 } 1281 if (intmask & SDHCI_INT_TIMEOUT) 1282 slot->curcmd->error = MMC_ERR_TIMEOUT; 1283 else if (intmask & SDHCI_INT_CRC) 1284 slot->curcmd->error = MMC_ERR_BADCRC; 1285 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1286 slot->curcmd->error = MMC_ERR_FIFO; 1287 1288 sdhci_finish_command(slot); 1289 } 1290 1291 static void 1292 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1293 { 1294 struct mmc_data *data; 1295 size_t left; 1296 1297 if (!slot->curcmd) { 1298 slot_printf(slot, "Got data interrupt 0x%08x, but " 1299 "there is no active command.\n", intmask); 1300 sdhci_dumpregs(slot); 1301 return; 1302 } 1303 if (slot->curcmd->data == NULL && 1304 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1305 slot_printf(slot, "Got data interrupt 0x%08x, but " 1306 "there is no active data operation.\n", 1307 intmask); 1308 sdhci_dumpregs(slot); 1309 return; 1310 } 1311 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1312 slot->curcmd->error = MMC_ERR_TIMEOUT; 1313 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1314 slot->curcmd->error = MMC_ERR_BADCRC; 1315 if (slot->curcmd->data == NULL && 1316 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1317 SDHCI_INT_DMA_END))) { 1318 slot_printf(slot, "Got data interrupt 0x%08x, but " 1319 "there is busy-only command.\n", intmask); 1320 sdhci_dumpregs(slot); 1321 slot->curcmd->error = MMC_ERR_INVALID; 1322 } 1323 if (slot->curcmd->error) { 1324 /* No need to continue after any error. */ 1325 goto done; 1326 } 1327 1328 /* Handle PIO interrupt. */ 1329 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1330 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1331 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1332 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1333 &intmask); 1334 slot->flags |= PLATFORM_DATA_STARTED; 1335 } else 1336 sdhci_transfer_pio(slot); 1337 } 1338 /* Handle DMA border. */ 1339 if (intmask & SDHCI_INT_DMA_END) { 1340 data = slot->curcmd->data; 1341 1342 /* Unload DMA buffer... */ 1343 left = data->len - slot->offset; 1344 if (data->flags & MMC_DATA_READ) { 1345 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1346 BUS_DMASYNC_POSTREAD); 1347 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1348 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1349 } else { 1350 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1351 BUS_DMASYNC_POSTWRITE); 1352 } 1353 /* ... and reload it again. */ 1354 slot->offset += DMA_BLOCK_SIZE; 1355 left = data->len - slot->offset; 1356 if (data->flags & MMC_DATA_READ) { 1357 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1358 BUS_DMASYNC_PREREAD); 1359 } else { 1360 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1361 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1362 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1363 BUS_DMASYNC_PREWRITE); 1364 } 1365 /* Interrupt aggregation: Mask border interrupt 1366 * for the last page. */ 1367 if (left == DMA_BLOCK_SIZE) { 1368 slot->intmask &= ~SDHCI_INT_DMA_END; 1369 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1370 } 1371 /* Restart DMA. */ 1372 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1373 } 1374 /* We have got all data. */ 1375 if (intmask & SDHCI_INT_DATA_END) { 1376 if (slot->flags & PLATFORM_DATA_STARTED) { 1377 slot->flags &= ~PLATFORM_DATA_STARTED; 1378 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1379 } else 1380 sdhci_finish_data(slot); 1381 } 1382 done: 1383 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1384 if (slot->flags & PLATFORM_DATA_STARTED) { 1385 slot->flags &= ~PLATFORM_DATA_STARTED; 1386 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1387 } else 1388 sdhci_finish_data(slot); 1389 } 1390 } 1391 1392 static void 1393 sdhci_acmd_irq(struct sdhci_slot *slot) 1394 { 1395 uint16_t err; 1396 1397 err = RD4(slot, SDHCI_ACMD12_ERR); 1398 if (!slot->curcmd) { 1399 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1400 "there is no active command.\n", err); 1401 sdhci_dumpregs(slot); 1402 return; 1403 } 1404 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1405 sdhci_reset(slot, SDHCI_RESET_CMD); 1406 } 1407 1408 void 1409 sdhci_generic_intr(struct sdhci_slot *slot) 1410 { 1411 uint32_t intmask, present; 1412 1413 SDHCI_LOCK(slot); 1414 /* Read slot interrupt status. */ 1415 intmask = RD4(slot, SDHCI_INT_STATUS); 1416 if (intmask == 0 || intmask == 0xffffffff) { 1417 SDHCI_UNLOCK(slot); 1418 return; 1419 } 1420 if (sdhci_debug > 2) 1421 slot_printf(slot, "Interrupt %#x\n", intmask); 1422 1423 /* Handle card presence interrupts. */ 1424 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1425 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1426 slot->intmask &= 1427 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1428 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1429 SDHCI_INT_CARD_INSERT; 1430 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1431 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1432 WR4(slot, SDHCI_INT_STATUS, intmask & 1433 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1434 sdhci_handle_card_present_locked(slot, present); 1435 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1436 } 1437 /* Handle command interrupts. */ 1438 if (intmask & SDHCI_INT_CMD_MASK) { 1439 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1440 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1441 } 1442 /* Handle data interrupts. */ 1443 if (intmask & SDHCI_INT_DATA_MASK) { 1444 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1445 /* Don't call data_irq in case of errored command. */ 1446 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1447 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1448 } 1449 /* Handle AutoCMD12 error interrupt. */ 1450 if (intmask & SDHCI_INT_ACMD12ERR) { 1451 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1452 sdhci_acmd_irq(slot); 1453 } 1454 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1455 intmask &= ~SDHCI_INT_ACMD12ERR; 1456 intmask &= ~SDHCI_INT_ERROR; 1457 /* Handle bus power interrupt. */ 1458 if (intmask & SDHCI_INT_BUS_POWER) { 1459 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1460 slot_printf(slot, 1461 "Card is consuming too much power!\n"); 1462 intmask &= ~SDHCI_INT_BUS_POWER; 1463 } 1464 /* The rest is unknown. */ 1465 if (intmask) { 1466 WR4(slot, SDHCI_INT_STATUS, intmask); 1467 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1468 intmask); 1469 sdhci_dumpregs(slot); 1470 } 1471 1472 SDHCI_UNLOCK(slot); 1473 } 1474 1475 int 1476 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1477 uintptr_t *result) 1478 { 1479 struct sdhci_slot *slot = device_get_ivars(child); 1480 1481 switch (which) { 1482 default: 1483 return (EINVAL); 1484 case MMCBR_IVAR_BUS_MODE: 1485 *result = slot->host.ios.bus_mode; 1486 break; 1487 case MMCBR_IVAR_BUS_WIDTH: 1488 *result = slot->host.ios.bus_width; 1489 break; 1490 case MMCBR_IVAR_CHIP_SELECT: 1491 *result = slot->host.ios.chip_select; 1492 break; 1493 case MMCBR_IVAR_CLOCK: 1494 *result = slot->host.ios.clock; 1495 break; 1496 case MMCBR_IVAR_F_MIN: 1497 *result = slot->host.f_min; 1498 break; 1499 case MMCBR_IVAR_F_MAX: 1500 *result = slot->host.f_max; 1501 break; 1502 case MMCBR_IVAR_HOST_OCR: 1503 *result = slot->host.host_ocr; 1504 break; 1505 case MMCBR_IVAR_MODE: 1506 *result = slot->host.mode; 1507 break; 1508 case MMCBR_IVAR_OCR: 1509 *result = slot->host.ocr; 1510 break; 1511 case MMCBR_IVAR_POWER_MODE: 1512 *result = slot->host.ios.power_mode; 1513 break; 1514 case MMCBR_IVAR_VDD: 1515 *result = slot->host.ios.vdd; 1516 break; 1517 case MMCBR_IVAR_CAPS: 1518 *result = slot->host.caps; 1519 break; 1520 case MMCBR_IVAR_TIMING: 1521 *result = slot->host.ios.timing; 1522 break; 1523 case MMCBR_IVAR_MAX_DATA: 1524 *result = 65535; 1525 break; 1526 } 1527 return (0); 1528 } 1529 1530 int 1531 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1532 uintptr_t value) 1533 { 1534 struct sdhci_slot *slot = device_get_ivars(child); 1535 uint32_t clock, max_clock; 1536 int i; 1537 1538 switch (which) { 1539 default: 1540 return (EINVAL); 1541 case MMCBR_IVAR_BUS_MODE: 1542 slot->host.ios.bus_mode = value; 1543 break; 1544 case MMCBR_IVAR_BUS_WIDTH: 1545 slot->host.ios.bus_width = value; 1546 break; 1547 case MMCBR_IVAR_CHIP_SELECT: 1548 slot->host.ios.chip_select = value; 1549 break; 1550 case MMCBR_IVAR_CLOCK: 1551 if (value > 0) { 1552 max_clock = slot->max_clk; 1553 clock = max_clock; 1554 1555 if (slot->version < SDHCI_SPEC_300) { 1556 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1557 i <<= 1) { 1558 if (clock <= value) 1559 break; 1560 clock >>= 1; 1561 } 1562 } else { 1563 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1564 i += 2) { 1565 if (clock <= value) 1566 break; 1567 clock = max_clock / (i + 2); 1568 } 1569 } 1570 1571 slot->host.ios.clock = clock; 1572 } else 1573 slot->host.ios.clock = 0; 1574 break; 1575 case MMCBR_IVAR_MODE: 1576 slot->host.mode = value; 1577 break; 1578 case MMCBR_IVAR_OCR: 1579 slot->host.ocr = value; 1580 break; 1581 case MMCBR_IVAR_POWER_MODE: 1582 slot->host.ios.power_mode = value; 1583 break; 1584 case MMCBR_IVAR_VDD: 1585 slot->host.ios.vdd = value; 1586 break; 1587 case MMCBR_IVAR_TIMING: 1588 slot->host.ios.timing = value; 1589 break; 1590 case MMCBR_IVAR_CAPS: 1591 case MMCBR_IVAR_HOST_OCR: 1592 case MMCBR_IVAR_F_MIN: 1593 case MMCBR_IVAR_F_MAX: 1594 case MMCBR_IVAR_MAX_DATA: 1595 return (EINVAL); 1596 } 1597 return (0); 1598 } 1599 1600 MODULE_VERSION(sdhci, 1); 1601