1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 59 "Debug level"); 60 61 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 62 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 64 #define RD_MULTI_4(slot, off, ptr, count) \ 65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 66 67 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 68 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 70 #define WR_MULTI_4(slot, off, ptr, count) \ 71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 72 73 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 74 static void sdhci_start(struct sdhci_slot *slot); 75 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 76 77 static void sdhci_card_poll(void *); 78 static void sdhci_card_task(void *, int); 79 80 /* helper routines */ 81 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 82 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 83 #define SDHCI_LOCK_INIT(_slot) \ 84 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 85 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 86 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 87 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 88 89 #define SDHCI_DEFAULT_MAX_FREQ 50 90 91 #define SDHCI_200_MAX_DIVIDER 256 92 #define SDHCI_300_MAX_DIVIDER 2046 93 94 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 95 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 96 97 /* 98 * Broadcom BCM577xx Controller Constants 99 */ 100 /* Maximum divider supported by the default clock source. */ 101 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 102 /* Alternative clock's base frequency. */ 103 #define BCM577XX_ALT_CLOCK_BASE 63000000 104 105 #define BCM577XX_HOST_CONTROL 0x198 106 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 107 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 108 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 109 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 110 111 static void 112 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 113 { 114 115 if (error != 0) { 116 printf("getaddr: error %d\n", error); 117 return; 118 } 119 *(bus_addr_t *)arg = segs[0].ds_addr; 120 } 121 122 static int 123 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 124 { 125 va_list ap; 126 int retval; 127 128 retval = printf("%s-slot%d: ", 129 device_get_nameunit(slot->bus), slot->num); 130 131 va_start(ap, fmt); 132 retval += vprintf(fmt, ap); 133 va_end(ap); 134 return (retval); 135 } 136 137 static void 138 sdhci_dumpregs(struct sdhci_slot *slot) 139 { 140 141 slot_printf(slot, 142 "============== REGISTER DUMP ==============\n"); 143 144 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 145 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 146 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 147 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 148 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 149 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 150 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 151 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 152 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 153 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 154 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 155 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 156 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 157 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 158 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 159 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 160 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 161 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 162 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 163 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 164 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 165 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 166 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 167 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 168 169 slot_printf(slot, 170 "===========================================\n"); 171 } 172 173 static void 174 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 175 { 176 int timeout; 177 uint32_t clock; 178 179 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 180 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 181 return; 182 } 183 184 /* Some controllers need this kick or reset won't work. */ 185 if ((mask & SDHCI_RESET_ALL) == 0 && 186 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 187 /* This is to force an update */ 188 clock = slot->clock; 189 slot->clock = 0; 190 sdhci_set_clock(slot, clock); 191 } 192 193 if (mask & SDHCI_RESET_ALL) { 194 slot->clock = 0; 195 slot->power = 0; 196 } 197 198 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 199 200 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 201 /* 202 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 203 * specification. The reset bit has internal propagation delay, 204 * so a fast read after write returns 0 even if reset process is 205 * in progress. The workaround is to poll for 1 before polling 206 * for 0. In the worst case, if we miss seeing it asserted the 207 * time we spent waiting is enough to ensure the reset finishes. 208 */ 209 timeout = 10000; 210 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 211 if (timeout <= 0) 212 break; 213 timeout--; 214 DELAY(1); 215 } 216 } 217 218 /* Wait max 100 ms */ 219 timeout = 10000; 220 /* Controller clears the bits when it's done */ 221 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 222 if (timeout <= 0) { 223 slot_printf(slot, "Reset 0x%x never completed.\n", 224 mask); 225 sdhci_dumpregs(slot); 226 return; 227 } 228 timeout--; 229 DELAY(10); 230 } 231 } 232 233 static void 234 sdhci_init(struct sdhci_slot *slot) 235 { 236 237 sdhci_reset(slot, SDHCI_RESET_ALL); 238 239 /* Enable interrupts. */ 240 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 241 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 242 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 243 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 244 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 245 SDHCI_INT_ACMD12ERR; 246 247 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 248 !(slot->opt & SDHCI_NON_REMOVABLE)) { 249 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 250 } 251 252 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 253 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 254 } 255 256 static void 257 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 258 { 259 uint32_t clk_base; 260 uint32_t clk_sel; 261 uint32_t res; 262 uint16_t clk; 263 uint16_t div; 264 int timeout; 265 266 if (clock == slot->clock) 267 return; 268 slot->clock = clock; 269 270 /* Turn off the clock. */ 271 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 272 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 273 /* If no clock requested - leave it so. */ 274 if (clock == 0) 275 return; 276 277 /* Determine the clock base frequency */ 278 clk_base = slot->max_clk; 279 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 280 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 281 BCM577XX_CTRL_CLKSEL_MASK; 282 283 /* 284 * Select clock source appropriate for the requested frequency. 285 */ 286 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 287 clk_base = BCM577XX_ALT_CLOCK_BASE; 288 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 289 BCM577XX_CTRL_CLKSEL_SHIFT); 290 } else { 291 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 292 BCM577XX_CTRL_CLKSEL_SHIFT); 293 } 294 295 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 296 } 297 298 /* Recalculate timeout clock frequency based on the new sd clock. */ 299 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 300 slot->timeout_clk = slot->clock / 1000; 301 302 if (slot->version < SDHCI_SPEC_300) { 303 /* Looking for highest freq <= clock. */ 304 res = clk_base; 305 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 306 if (res <= clock) 307 break; 308 res >>= 1; 309 } 310 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 311 div >>= 1; 312 } 313 else { 314 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 315 if (clock >= clk_base) 316 div = 0; 317 else { 318 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 319 if ((clk_base / div) <= clock) 320 break; 321 } 322 } 323 div >>= 1; 324 } 325 326 if (bootverbose || sdhci_debug) 327 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 328 div, clock, clk_base); 329 330 /* Now we have got divider, set it. */ 331 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 332 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 333 << SDHCI_DIVIDER_HI_SHIFT; 334 335 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 336 /* Enable clock. */ 337 clk |= SDHCI_CLOCK_INT_EN; 338 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 339 /* Wait up to 10 ms until it stabilize. */ 340 timeout = 10; 341 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 342 & SDHCI_CLOCK_INT_STABLE)) { 343 if (timeout == 0) { 344 slot_printf(slot, 345 "Internal clock never stabilised.\n"); 346 sdhci_dumpregs(slot); 347 return; 348 } 349 timeout--; 350 DELAY(1000); 351 } 352 /* Pass clock signal to the bus. */ 353 clk |= SDHCI_CLOCK_CARD_EN; 354 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 355 } 356 357 static void 358 sdhci_set_power(struct sdhci_slot *slot, u_char power) 359 { 360 uint8_t pwr; 361 362 if (slot->power == power) 363 return; 364 365 slot->power = power; 366 367 /* Turn off the power. */ 368 pwr = 0; 369 WR1(slot, SDHCI_POWER_CONTROL, pwr); 370 /* If power down requested - leave it so. */ 371 if (power == 0) 372 return; 373 /* Set voltage. */ 374 switch (1 << power) { 375 case MMC_OCR_LOW_VOLTAGE: 376 pwr |= SDHCI_POWER_180; 377 break; 378 case MMC_OCR_290_300: 379 case MMC_OCR_300_310: 380 pwr |= SDHCI_POWER_300; 381 break; 382 case MMC_OCR_320_330: 383 case MMC_OCR_330_340: 384 pwr |= SDHCI_POWER_330; 385 break; 386 } 387 WR1(slot, SDHCI_POWER_CONTROL, pwr); 388 /* Turn on the power. */ 389 pwr |= SDHCI_POWER_ON; 390 WR1(slot, SDHCI_POWER_CONTROL, pwr); 391 392 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 393 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 394 DELAY(10); 395 WR1(slot, SDHCI_POWER_CONTROL, pwr); 396 DELAY(300); 397 } 398 } 399 400 static void 401 sdhci_read_block_pio(struct sdhci_slot *slot) 402 { 403 uint32_t data; 404 char *buffer; 405 size_t left; 406 407 buffer = slot->curcmd->data->data; 408 buffer += slot->offset; 409 /* Transfer one block at a time. */ 410 left = min(512, slot->curcmd->data->len - slot->offset); 411 slot->offset += left; 412 413 /* If we are too fast, broken controllers return zeroes. */ 414 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 415 DELAY(10); 416 /* Handle unaligned and aligned buffer cases. */ 417 if ((intptr_t)buffer & 3) { 418 while (left > 3) { 419 data = RD4(slot, SDHCI_BUFFER); 420 buffer[0] = data; 421 buffer[1] = (data >> 8); 422 buffer[2] = (data >> 16); 423 buffer[3] = (data >> 24); 424 buffer += 4; 425 left -= 4; 426 } 427 } else { 428 RD_MULTI_4(slot, SDHCI_BUFFER, 429 (uint32_t *)buffer, left >> 2); 430 left &= 3; 431 } 432 /* Handle uneven size case. */ 433 if (left > 0) { 434 data = RD4(slot, SDHCI_BUFFER); 435 while (left > 0) { 436 *(buffer++) = data; 437 data >>= 8; 438 left--; 439 } 440 } 441 } 442 443 static void 444 sdhci_write_block_pio(struct sdhci_slot *slot) 445 { 446 uint32_t data = 0; 447 char *buffer; 448 size_t left; 449 450 buffer = slot->curcmd->data->data; 451 buffer += slot->offset; 452 /* Transfer one block at a time. */ 453 left = min(512, slot->curcmd->data->len - slot->offset); 454 slot->offset += left; 455 456 /* Handle unaligned and aligned buffer cases. */ 457 if ((intptr_t)buffer & 3) { 458 while (left > 3) { 459 data = buffer[0] + 460 (buffer[1] << 8) + 461 (buffer[2] << 16) + 462 (buffer[3] << 24); 463 left -= 4; 464 buffer += 4; 465 WR4(slot, SDHCI_BUFFER, data); 466 } 467 } else { 468 WR_MULTI_4(slot, SDHCI_BUFFER, 469 (uint32_t *)buffer, left >> 2); 470 left &= 3; 471 } 472 /* Handle uneven size case. */ 473 if (left > 0) { 474 while (left > 0) { 475 data <<= 8; 476 data += *(buffer++); 477 left--; 478 } 479 WR4(slot, SDHCI_BUFFER, data); 480 } 481 } 482 483 static void 484 sdhci_transfer_pio(struct sdhci_slot *slot) 485 { 486 487 /* Read as many blocks as possible. */ 488 if (slot->curcmd->data->flags & MMC_DATA_READ) { 489 while (RD4(slot, SDHCI_PRESENT_STATE) & 490 SDHCI_DATA_AVAILABLE) { 491 sdhci_read_block_pio(slot); 492 if (slot->offset >= slot->curcmd->data->len) 493 break; 494 } 495 } else { 496 while (RD4(slot, SDHCI_PRESENT_STATE) & 497 SDHCI_SPACE_AVAILABLE) { 498 sdhci_write_block_pio(slot); 499 if (slot->offset >= slot->curcmd->data->len) 500 break; 501 } 502 } 503 } 504 505 static void 506 sdhci_card_task(void *arg, int pending __unused) 507 { 508 struct sdhci_slot *slot = arg; 509 device_t d; 510 511 SDHCI_LOCK(slot); 512 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 513 if (slot->dev == NULL) { 514 /* If card is present - attach mmc bus. */ 515 if (bootverbose || sdhci_debug) 516 slot_printf(slot, "Card inserted\n"); 517 slot->dev = device_add_child(slot->bus, "mmc", -1); 518 device_set_ivars(slot->dev, slot); 519 SDHCI_UNLOCK(slot); 520 device_probe_and_attach(slot->dev); 521 } else 522 SDHCI_UNLOCK(slot); 523 } else { 524 if (slot->dev != NULL) { 525 /* If no card present - detach mmc bus. */ 526 if (bootverbose || sdhci_debug) 527 slot_printf(slot, "Card removed\n"); 528 d = slot->dev; 529 slot->dev = NULL; 530 SDHCI_UNLOCK(slot); 531 device_delete_child(slot->bus, d); 532 } else 533 SDHCI_UNLOCK(slot); 534 } 535 } 536 537 static void 538 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 539 { 540 bool was_present; 541 542 /* 543 * If there was no card and now there is one, schedule the task to 544 * create the child device after a short delay. The delay is to 545 * debounce the card insert (sometimes the card detect pin stabilizes 546 * before the other pins have made good contact). 547 * 548 * If there was a card present and now it's gone, immediately schedule 549 * the task to delete the child device. No debouncing -- gone is gone, 550 * because once power is removed, a full card re-init is needed, and 551 * that happens by deleting and recreating the child device. 552 */ 553 was_present = slot->dev != NULL; 554 if (!was_present && is_present) { 555 taskqueue_enqueue_timeout(taskqueue_swi_giant, 556 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 557 } else if (was_present && !is_present) { 558 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 559 } 560 } 561 562 void 563 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 564 { 565 566 SDHCI_LOCK(slot); 567 sdhci_handle_card_present_locked(slot, is_present); 568 SDHCI_UNLOCK(slot); 569 } 570 571 static void 572 sdhci_card_poll(void *arg) 573 { 574 struct sdhci_slot *slot = arg; 575 576 sdhci_handle_card_present(slot, 577 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 578 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 579 sdhci_card_poll, slot); 580 } 581 582 int 583 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 584 { 585 uint32_t caps, freq; 586 int err; 587 588 SDHCI_LOCK_INIT(slot); 589 slot->num = num; 590 slot->bus = dev; 591 592 /* Allocate DMA tag. */ 593 err = bus_dma_tag_create(bus_get_dma_tag(dev), 594 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 595 BUS_SPACE_MAXADDR, NULL, NULL, 596 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 597 BUS_DMA_ALLOCNOW, NULL, NULL, 598 &slot->dmatag); 599 if (err != 0) { 600 device_printf(dev, "Can't create DMA tag\n"); 601 SDHCI_LOCK_DESTROY(slot); 602 return (err); 603 } 604 /* Allocate DMA memory. */ 605 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 606 BUS_DMA_NOWAIT, &slot->dmamap); 607 if (err != 0) { 608 device_printf(dev, "Can't alloc DMA memory\n"); 609 SDHCI_LOCK_DESTROY(slot); 610 return (err); 611 } 612 /* Map the memory. */ 613 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 614 (void *)slot->dmamem, DMA_BLOCK_SIZE, 615 sdhci_getaddr, &slot->paddr, 0); 616 if (err != 0 || slot->paddr == 0) { 617 device_printf(dev, "Can't load DMA memory\n"); 618 SDHCI_LOCK_DESTROY(slot); 619 if (err) 620 return (err); 621 else 622 return (EFAULT); 623 } 624 625 /* Initialize slot. */ 626 sdhci_init(slot); 627 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 628 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 629 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 630 caps = slot->caps; 631 else 632 caps = RD4(slot, SDHCI_CAPABILITIES); 633 /* Calculate base clock frequency. */ 634 if (slot->version >= SDHCI_SPEC_300) 635 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 636 SDHCI_CLOCK_BASE_SHIFT; 637 else 638 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 639 SDHCI_CLOCK_BASE_SHIFT; 640 if (freq != 0) 641 slot->max_clk = freq * 1000000; 642 /* 643 * If the frequency wasn't in the capabilities and the hardware driver 644 * hasn't already set max_clk we're probably not going to work right 645 * with an assumption, so complain about it. 646 */ 647 if (slot->max_clk == 0) { 648 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 649 device_printf(dev, "Hardware doesn't specify base clock " 650 "frequency, using %dMHz as default.\n", 651 SDHCI_DEFAULT_MAX_FREQ); 652 } 653 /* Calculate/set timeout clock frequency. */ 654 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 655 slot->timeout_clk = slot->max_clk / 1000; 656 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 657 slot->timeout_clk = 1000; 658 } else { 659 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 660 SDHCI_TIMEOUT_CLK_SHIFT; 661 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 662 slot->timeout_clk *= 1000; 663 } 664 /* 665 * If the frequency wasn't in the capabilities and the hardware driver 666 * hasn't already set timeout_clk we'll probably work okay using the 667 * max timeout, but still mention it. 668 */ 669 if (slot->timeout_clk == 0) { 670 device_printf(dev, "Hardware doesn't specify timeout clock " 671 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 672 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 673 } 674 675 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 676 slot->host.f_max = slot->max_clk; 677 slot->host.host_ocr = 0; 678 if (caps & SDHCI_CAN_VDD_330) 679 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 680 if (caps & SDHCI_CAN_VDD_300) 681 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 682 if (caps & SDHCI_CAN_VDD_180) 683 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 684 if (slot->host.host_ocr == 0) { 685 device_printf(dev, "Hardware doesn't report any " 686 "support voltages.\n"); 687 } 688 slot->host.caps = MMC_CAP_4_BIT_DATA; 689 if (caps & SDHCI_CAN_DO_8BITBUS) 690 slot->host.caps |= MMC_CAP_8_BIT_DATA; 691 if (caps & SDHCI_CAN_DO_HISPD) 692 slot->host.caps |= MMC_CAP_HSPEED; 693 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 694 slot->host.caps |= MMC_CAP_BOOT_NOACC; 695 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 696 slot->host.caps |= MMC_CAP_WAIT_WHILE_BUSY; 697 /* Decide if we have usable DMA. */ 698 if (caps & SDHCI_CAN_DO_DMA) 699 slot->opt |= SDHCI_HAVE_DMA; 700 701 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 702 slot->opt &= ~SDHCI_HAVE_DMA; 703 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 704 slot->opt |= SDHCI_HAVE_DMA; 705 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 706 slot->opt |= SDHCI_NON_REMOVABLE; 707 708 /* 709 * Use platform-provided transfer backend 710 * with PIO as a fallback mechanism 711 */ 712 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 713 slot->opt &= ~SDHCI_HAVE_DMA; 714 715 if (bootverbose || sdhci_debug) { 716 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 717 slot->max_clk / 1000000, 718 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 719 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 720 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" : 721 "1bit"), 722 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 723 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 724 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 725 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 726 sdhci_dumpregs(slot); 727 } 728 729 slot->timeout = 10; 730 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 731 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 732 "timeout", CTLFLAG_RW, &slot->timeout, 0, 733 "Maximum timeout for SDHCI transfers (in secs)"); 734 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 735 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 736 sdhci_card_task, slot); 737 callout_init(&slot->card_poll_callout, 1); 738 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 739 740 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 741 !(slot->opt & SDHCI_NON_REMOVABLE)) { 742 callout_reset(&slot->card_poll_callout, 743 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 744 } 745 746 return (0); 747 } 748 749 void 750 sdhci_start_slot(struct sdhci_slot *slot) 751 { 752 753 sdhci_card_task(slot, 0); 754 } 755 756 int 757 sdhci_cleanup_slot(struct sdhci_slot *slot) 758 { 759 device_t d; 760 761 callout_drain(&slot->timeout_callout); 762 callout_drain(&slot->card_poll_callout); 763 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 764 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 765 766 SDHCI_LOCK(slot); 767 d = slot->dev; 768 slot->dev = NULL; 769 SDHCI_UNLOCK(slot); 770 if (d != NULL) 771 device_delete_child(slot->bus, d); 772 773 SDHCI_LOCK(slot); 774 sdhci_reset(slot, SDHCI_RESET_ALL); 775 SDHCI_UNLOCK(slot); 776 bus_dmamap_unload(slot->dmatag, slot->dmamap); 777 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 778 bus_dma_tag_destroy(slot->dmatag); 779 780 SDHCI_LOCK_DESTROY(slot); 781 782 return (0); 783 } 784 785 int 786 sdhci_generic_suspend(struct sdhci_slot *slot) 787 { 788 789 sdhci_reset(slot, SDHCI_RESET_ALL); 790 791 return (0); 792 } 793 794 int 795 sdhci_generic_resume(struct sdhci_slot *slot) 796 { 797 798 sdhci_init(slot); 799 800 return (0); 801 } 802 803 uint32_t 804 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 805 { 806 807 if (slot->version >= SDHCI_SPEC_300) 808 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 809 else 810 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 811 } 812 813 bool 814 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 815 { 816 817 if (slot->opt & SDHCI_NON_REMOVABLE) 818 return true; 819 820 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 821 } 822 823 int 824 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 825 { 826 struct sdhci_slot *slot = device_get_ivars(reqdev); 827 struct mmc_ios *ios = &slot->host.ios; 828 829 SDHCI_LOCK(slot); 830 /* Do full reset on bus power down to clear from any state. */ 831 if (ios->power_mode == power_off) { 832 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 833 sdhci_init(slot); 834 } 835 /* Configure the bus. */ 836 sdhci_set_clock(slot, ios->clock); 837 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 838 if (ios->bus_width == bus_width_8) { 839 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 840 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 841 } else if (ios->bus_width == bus_width_4) { 842 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 843 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 844 } else if (ios->bus_width == bus_width_1) { 845 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 846 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 847 } else { 848 panic("Invalid bus width: %d", ios->bus_width); 849 } 850 if (ios->timing == bus_timing_hs && 851 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 852 slot->hostctrl |= SDHCI_CTRL_HISPD; 853 else 854 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 855 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 856 /* Some controllers like reset after bus changes. */ 857 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 858 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 859 860 SDHCI_UNLOCK(slot); 861 return (0); 862 } 863 864 static void 865 sdhci_req_done(struct sdhci_slot *slot) 866 { 867 struct mmc_request *req; 868 869 if (slot->req != NULL && slot->curcmd != NULL) { 870 callout_stop(&slot->timeout_callout); 871 req = slot->req; 872 slot->req = NULL; 873 slot->curcmd = NULL; 874 req->done(req); 875 } 876 } 877 878 static void 879 sdhci_timeout(void *arg) 880 { 881 struct sdhci_slot *slot = arg; 882 883 if (slot->curcmd != NULL) { 884 slot_printf(slot, " Controller timeout\n"); 885 sdhci_dumpregs(slot); 886 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 887 slot->curcmd->error = MMC_ERR_TIMEOUT; 888 sdhci_req_done(slot); 889 } else { 890 slot_printf(slot, " Spurious timeout - no active command\n"); 891 } 892 } 893 894 static void 895 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 896 { 897 uint16_t mode; 898 899 if (data == NULL) 900 return; 901 902 mode = SDHCI_TRNS_BLK_CNT_EN; 903 if (data->len > 512) 904 mode |= SDHCI_TRNS_MULTI; 905 if (data->flags & MMC_DATA_READ) 906 mode |= SDHCI_TRNS_READ; 907 if (slot->req->stop) 908 mode |= SDHCI_TRNS_ACMD12; 909 if (slot->flags & SDHCI_USE_DMA) 910 mode |= SDHCI_TRNS_DMA; 911 912 WR2(slot, SDHCI_TRANSFER_MODE, mode); 913 } 914 915 static void 916 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 917 { 918 int flags, timeout; 919 uint32_t mask; 920 921 slot->curcmd = cmd; 922 slot->cmd_done = 0; 923 924 cmd->error = MMC_ERR_NONE; 925 926 /* This flags combination is not supported by controller. */ 927 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 928 slot_printf(slot, "Unsupported response type!\n"); 929 cmd->error = MMC_ERR_FAILED; 930 sdhci_req_done(slot); 931 return; 932 } 933 934 /* 935 * Do not issue command if there is no card, clock or power. 936 * Controller will not detect timeout without clock active. 937 */ 938 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 939 slot->power == 0 || 940 slot->clock == 0) { 941 cmd->error = MMC_ERR_FAILED; 942 sdhci_req_done(slot); 943 return; 944 } 945 /* Always wait for free CMD bus. */ 946 mask = SDHCI_CMD_INHIBIT; 947 /* Wait for free DAT if we have data or busy signal. */ 948 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 949 mask |= SDHCI_DAT_INHIBIT; 950 /* We shouldn't wait for DAT for stop commands. */ 951 if (cmd == slot->req->stop) 952 mask &= ~SDHCI_DAT_INHIBIT; 953 /* 954 * Wait for bus no more then 250 ms. Typically there will be no wait 955 * here at all, but when writing a crash dump we may be bypassing the 956 * host platform's interrupt handler, and in some cases that handler 957 * may be working around hardware quirks such as not respecting r1b 958 * busy indications. In those cases, this wait-loop serves the purpose 959 * of waiting for the prior command and data transfers to be done, and 960 * SD cards are allowed to take up to 250ms for write and erase ops. 961 * (It's usually more like 20-30ms in the real world.) 962 */ 963 timeout = 250; 964 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 965 if (timeout == 0) { 966 slot_printf(slot, "Controller never released " 967 "inhibit bit(s).\n"); 968 sdhci_dumpregs(slot); 969 cmd->error = MMC_ERR_FAILED; 970 sdhci_req_done(slot); 971 return; 972 } 973 timeout--; 974 DELAY(1000); 975 } 976 977 /* Prepare command flags. */ 978 if (!(cmd->flags & MMC_RSP_PRESENT)) 979 flags = SDHCI_CMD_RESP_NONE; 980 else if (cmd->flags & MMC_RSP_136) 981 flags = SDHCI_CMD_RESP_LONG; 982 else if (cmd->flags & MMC_RSP_BUSY) 983 flags = SDHCI_CMD_RESP_SHORT_BUSY; 984 else 985 flags = SDHCI_CMD_RESP_SHORT; 986 if (cmd->flags & MMC_RSP_CRC) 987 flags |= SDHCI_CMD_CRC; 988 if (cmd->flags & MMC_RSP_OPCODE) 989 flags |= SDHCI_CMD_INDEX; 990 if (cmd->data) 991 flags |= SDHCI_CMD_DATA; 992 if (cmd->opcode == MMC_STOP_TRANSMISSION) 993 flags |= SDHCI_CMD_TYPE_ABORT; 994 /* Prepare data. */ 995 sdhci_start_data(slot, cmd->data); 996 /* 997 * Interrupt aggregation: To reduce total number of interrupts 998 * group response interrupt with data interrupt when possible. 999 * If there going to be data interrupt, mask response one. 1000 */ 1001 if (slot->data_done == 0) { 1002 WR4(slot, SDHCI_SIGNAL_ENABLE, 1003 slot->intmask &= ~SDHCI_INT_RESPONSE); 1004 } 1005 /* Set command argument. */ 1006 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1007 /* Set data transfer mode. */ 1008 sdhci_set_transfer_mode(slot, cmd->data); 1009 /* Start command. */ 1010 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1011 /* Start timeout callout. */ 1012 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1013 sdhci_timeout, slot); 1014 } 1015 1016 static void 1017 sdhci_finish_command(struct sdhci_slot *slot) 1018 { 1019 int i; 1020 uint32_t val; 1021 uint8_t extra; 1022 1023 slot->cmd_done = 1; 1024 /* 1025 * Interrupt aggregation: Restore command interrupt. 1026 * Main restore point for the case when command interrupt 1027 * happened first. 1028 */ 1029 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1030 /* In case of error - reset host and return. */ 1031 if (slot->curcmd->error) { 1032 sdhci_reset(slot, SDHCI_RESET_CMD); 1033 sdhci_reset(slot, SDHCI_RESET_DATA); 1034 sdhci_start(slot); 1035 return; 1036 } 1037 /* If command has response - fetch it. */ 1038 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1039 if (slot->curcmd->flags & MMC_RSP_136) { 1040 /* CRC is stripped so we need one byte shift. */ 1041 extra = 0; 1042 for (i = 0; i < 4; i++) { 1043 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1044 if (slot->quirks & 1045 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1046 slot->curcmd->resp[3 - i] = val; 1047 else { 1048 slot->curcmd->resp[3 - i] = 1049 (val << 8) | extra; 1050 extra = val >> 24; 1051 } 1052 } 1053 } else 1054 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1055 } 1056 /* If data ready - finish. */ 1057 if (slot->data_done) 1058 sdhci_start(slot); 1059 } 1060 1061 static void 1062 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1063 { 1064 uint32_t target_timeout, current_timeout; 1065 uint8_t div; 1066 1067 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1068 slot->data_done = 1; 1069 return; 1070 } 1071 1072 slot->data_done = 0; 1073 1074 /* Calculate and set data timeout.*/ 1075 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1076 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1077 div = 0xE; 1078 } else { 1079 target_timeout = 1000000; 1080 div = 0; 1081 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1082 while (current_timeout < target_timeout && div < 0xE) { 1083 ++div; 1084 current_timeout <<= 1; 1085 } 1086 /* Compensate for an off-by-one error in the CaFe chip.*/ 1087 if (div < 0xE && 1088 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1089 ++div; 1090 } 1091 } 1092 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1093 1094 if (data == NULL) 1095 return; 1096 1097 /* Use DMA if possible. */ 1098 if ((slot->opt & SDHCI_HAVE_DMA)) 1099 slot->flags |= SDHCI_USE_DMA; 1100 /* If data is small, broken DMA may return zeroes instead of data, */ 1101 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1102 (data->len <= 512)) 1103 slot->flags &= ~SDHCI_USE_DMA; 1104 /* Some controllers require even block sizes. */ 1105 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1106 ((data->len) & 0x3)) 1107 slot->flags &= ~SDHCI_USE_DMA; 1108 /* Load DMA buffer. */ 1109 if (slot->flags & SDHCI_USE_DMA) { 1110 if (data->flags & MMC_DATA_READ) 1111 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1112 BUS_DMASYNC_PREREAD); 1113 else { 1114 memcpy(slot->dmamem, data->data, 1115 (data->len < DMA_BLOCK_SIZE) ? 1116 data->len : DMA_BLOCK_SIZE); 1117 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1118 BUS_DMASYNC_PREWRITE); 1119 } 1120 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1121 /* Interrupt aggregation: Mask border interrupt 1122 * for the last page and unmask else. */ 1123 if (data->len == DMA_BLOCK_SIZE) 1124 slot->intmask &= ~SDHCI_INT_DMA_END; 1125 else 1126 slot->intmask |= SDHCI_INT_DMA_END; 1127 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1128 } 1129 /* Current data offset for both PIO and DMA. */ 1130 slot->offset = 0; 1131 /* Set block size and request IRQ on 4K border. */ 1132 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1133 (data->len < 512) ? data->len : 512)); 1134 /* Set block count. */ 1135 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1136 } 1137 1138 void 1139 sdhci_finish_data(struct sdhci_slot *slot) 1140 { 1141 struct mmc_data *data = slot->curcmd->data; 1142 size_t left; 1143 1144 /* Interrupt aggregation: Restore command interrupt. 1145 * Auxiliary restore point for the case when data interrupt 1146 * happened first. */ 1147 if (!slot->cmd_done) { 1148 WR4(slot, SDHCI_SIGNAL_ENABLE, 1149 slot->intmask |= SDHCI_INT_RESPONSE); 1150 } 1151 /* Unload rest of data from DMA buffer. */ 1152 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1153 if (data->flags & MMC_DATA_READ) { 1154 left = data->len - slot->offset; 1155 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1156 BUS_DMASYNC_POSTREAD); 1157 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1158 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1159 } else 1160 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1161 BUS_DMASYNC_POSTWRITE); 1162 } 1163 slot->data_done = 1; 1164 /* If there was error - reset the host. */ 1165 if (slot->curcmd->error) { 1166 sdhci_reset(slot, SDHCI_RESET_CMD); 1167 sdhci_reset(slot, SDHCI_RESET_DATA); 1168 sdhci_start(slot); 1169 return; 1170 } 1171 /* If we already have command response - finish. */ 1172 if (slot->cmd_done) 1173 sdhci_start(slot); 1174 } 1175 1176 static void 1177 sdhci_start(struct sdhci_slot *slot) 1178 { 1179 struct mmc_request *req; 1180 1181 req = slot->req; 1182 if (req == NULL) 1183 return; 1184 1185 if (!(slot->flags & CMD_STARTED)) { 1186 slot->flags |= CMD_STARTED; 1187 sdhci_start_command(slot, req->cmd); 1188 return; 1189 } 1190 /* We don't need this until using Auto-CMD12 feature 1191 if (!(slot->flags & STOP_STARTED) && req->stop) { 1192 slot->flags |= STOP_STARTED; 1193 sdhci_start_command(slot, req->stop); 1194 return; 1195 } 1196 */ 1197 if (sdhci_debug > 1) 1198 slot_printf(slot, "result: %d\n", req->cmd->error); 1199 if (!req->cmd->error && 1200 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1201 sdhci_reset(slot, SDHCI_RESET_CMD); 1202 sdhci_reset(slot, SDHCI_RESET_DATA); 1203 } 1204 1205 sdhci_req_done(slot); 1206 } 1207 1208 int 1209 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1210 struct mmc_request *req) 1211 { 1212 struct sdhci_slot *slot = device_get_ivars(reqdev); 1213 1214 SDHCI_LOCK(slot); 1215 if (slot->req != NULL) { 1216 SDHCI_UNLOCK(slot); 1217 return (EBUSY); 1218 } 1219 if (sdhci_debug > 1) { 1220 slot_printf(slot, 1221 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1222 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1223 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1224 (req->cmd->data)?req->cmd->data->flags:0); 1225 } 1226 slot->req = req; 1227 slot->flags = 0; 1228 sdhci_start(slot); 1229 SDHCI_UNLOCK(slot); 1230 if (dumping) { 1231 while (slot->req != NULL) { 1232 sdhci_generic_intr(slot); 1233 DELAY(10); 1234 } 1235 } 1236 return (0); 1237 } 1238 1239 int 1240 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1241 { 1242 struct sdhci_slot *slot = device_get_ivars(reqdev); 1243 uint32_t val; 1244 1245 SDHCI_LOCK(slot); 1246 val = RD4(slot, SDHCI_PRESENT_STATE); 1247 SDHCI_UNLOCK(slot); 1248 return (!(val & SDHCI_WRITE_PROTECT)); 1249 } 1250 1251 int 1252 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1253 { 1254 struct sdhci_slot *slot = device_get_ivars(reqdev); 1255 int err = 0; 1256 1257 SDHCI_LOCK(slot); 1258 while (slot->bus_busy) 1259 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1260 slot->bus_busy++; 1261 /* Activate led. */ 1262 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1263 SDHCI_UNLOCK(slot); 1264 return (err); 1265 } 1266 1267 int 1268 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1269 { 1270 struct sdhci_slot *slot = device_get_ivars(reqdev); 1271 1272 SDHCI_LOCK(slot); 1273 /* Deactivate led. */ 1274 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1275 slot->bus_busy--; 1276 SDHCI_UNLOCK(slot); 1277 wakeup(slot); 1278 return (0); 1279 } 1280 1281 static void 1282 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1283 { 1284 1285 if (!slot->curcmd) { 1286 slot_printf(slot, "Got command interrupt 0x%08x, but " 1287 "there is no active command.\n", intmask); 1288 sdhci_dumpregs(slot); 1289 return; 1290 } 1291 if (intmask & SDHCI_INT_TIMEOUT) 1292 slot->curcmd->error = MMC_ERR_TIMEOUT; 1293 else if (intmask & SDHCI_INT_CRC) 1294 slot->curcmd->error = MMC_ERR_BADCRC; 1295 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1296 slot->curcmd->error = MMC_ERR_FIFO; 1297 1298 sdhci_finish_command(slot); 1299 } 1300 1301 static void 1302 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1303 { 1304 struct mmc_data *data; 1305 size_t left; 1306 1307 if (!slot->curcmd) { 1308 slot_printf(slot, "Got data interrupt 0x%08x, but " 1309 "there is no active command.\n", intmask); 1310 sdhci_dumpregs(slot); 1311 return; 1312 } 1313 if (slot->curcmd->data == NULL && 1314 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1315 slot_printf(slot, "Got data interrupt 0x%08x, but " 1316 "there is no active data operation.\n", 1317 intmask); 1318 sdhci_dumpregs(slot); 1319 return; 1320 } 1321 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1322 slot->curcmd->error = MMC_ERR_TIMEOUT; 1323 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1324 slot->curcmd->error = MMC_ERR_BADCRC; 1325 if (slot->curcmd->data == NULL && 1326 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1327 SDHCI_INT_DMA_END))) { 1328 slot_printf(slot, "Got data interrupt 0x%08x, but " 1329 "there is busy-only command.\n", intmask); 1330 sdhci_dumpregs(slot); 1331 slot->curcmd->error = MMC_ERR_INVALID; 1332 } 1333 if (slot->curcmd->error) { 1334 /* No need to continue after any error. */ 1335 goto done; 1336 } 1337 1338 /* Handle PIO interrupt. */ 1339 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1340 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1341 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1342 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1343 &intmask); 1344 slot->flags |= PLATFORM_DATA_STARTED; 1345 } else 1346 sdhci_transfer_pio(slot); 1347 } 1348 /* Handle DMA border. */ 1349 if (intmask & SDHCI_INT_DMA_END) { 1350 data = slot->curcmd->data; 1351 1352 /* Unload DMA buffer... */ 1353 left = data->len - slot->offset; 1354 if (data->flags & MMC_DATA_READ) { 1355 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1356 BUS_DMASYNC_POSTREAD); 1357 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1358 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1359 } else { 1360 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1361 BUS_DMASYNC_POSTWRITE); 1362 } 1363 /* ... and reload it again. */ 1364 slot->offset += DMA_BLOCK_SIZE; 1365 left = data->len - slot->offset; 1366 if (data->flags & MMC_DATA_READ) { 1367 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1368 BUS_DMASYNC_PREREAD); 1369 } else { 1370 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1371 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1372 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1373 BUS_DMASYNC_PREWRITE); 1374 } 1375 /* Interrupt aggregation: Mask border interrupt 1376 * for the last page. */ 1377 if (left == DMA_BLOCK_SIZE) { 1378 slot->intmask &= ~SDHCI_INT_DMA_END; 1379 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1380 } 1381 /* Restart DMA. */ 1382 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1383 } 1384 /* We have got all data. */ 1385 if (intmask & SDHCI_INT_DATA_END) { 1386 if (slot->flags & PLATFORM_DATA_STARTED) { 1387 slot->flags &= ~PLATFORM_DATA_STARTED; 1388 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1389 } else 1390 sdhci_finish_data(slot); 1391 } 1392 done: 1393 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1394 if (slot->flags & PLATFORM_DATA_STARTED) { 1395 slot->flags &= ~PLATFORM_DATA_STARTED; 1396 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1397 } else 1398 sdhci_finish_data(slot); 1399 } 1400 } 1401 1402 static void 1403 sdhci_acmd_irq(struct sdhci_slot *slot) 1404 { 1405 uint16_t err; 1406 1407 err = RD4(slot, SDHCI_ACMD12_ERR); 1408 if (!slot->curcmd) { 1409 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1410 "there is no active command.\n", err); 1411 sdhci_dumpregs(slot); 1412 return; 1413 } 1414 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1415 sdhci_reset(slot, SDHCI_RESET_CMD); 1416 } 1417 1418 void 1419 sdhci_generic_intr(struct sdhci_slot *slot) 1420 { 1421 uint32_t intmask, present; 1422 1423 SDHCI_LOCK(slot); 1424 /* Read slot interrupt status. */ 1425 intmask = RD4(slot, SDHCI_INT_STATUS); 1426 if (intmask == 0 || intmask == 0xffffffff) { 1427 SDHCI_UNLOCK(slot); 1428 return; 1429 } 1430 if (sdhci_debug > 2) 1431 slot_printf(slot, "Interrupt %#x\n", intmask); 1432 1433 /* Handle card presence interrupts. */ 1434 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1435 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1436 slot->intmask &= 1437 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1438 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1439 SDHCI_INT_CARD_INSERT; 1440 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1441 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1442 WR4(slot, SDHCI_INT_STATUS, intmask & 1443 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1444 sdhci_handle_card_present_locked(slot, present); 1445 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1446 } 1447 /* Handle command interrupts. */ 1448 if (intmask & SDHCI_INT_CMD_MASK) { 1449 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1450 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1451 } 1452 /* Handle data interrupts. */ 1453 if (intmask & SDHCI_INT_DATA_MASK) { 1454 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1455 /* Don't call data_irq in case of errored command. */ 1456 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1457 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1458 } 1459 /* Handle AutoCMD12 error interrupt. */ 1460 if (intmask & SDHCI_INT_ACMD12ERR) { 1461 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1462 sdhci_acmd_irq(slot); 1463 } 1464 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1465 intmask &= ~SDHCI_INT_ACMD12ERR; 1466 intmask &= ~SDHCI_INT_ERROR; 1467 /* Handle bus power interrupt. */ 1468 if (intmask & SDHCI_INT_BUS_POWER) { 1469 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1470 slot_printf(slot, 1471 "Card is consuming too much power!\n"); 1472 intmask &= ~SDHCI_INT_BUS_POWER; 1473 } 1474 /* The rest is unknown. */ 1475 if (intmask) { 1476 WR4(slot, SDHCI_INT_STATUS, intmask); 1477 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1478 intmask); 1479 sdhci_dumpregs(slot); 1480 } 1481 1482 SDHCI_UNLOCK(slot); 1483 } 1484 1485 int 1486 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1487 uintptr_t *result) 1488 { 1489 struct sdhci_slot *slot = device_get_ivars(child); 1490 1491 switch (which) { 1492 default: 1493 return (EINVAL); 1494 case MMCBR_IVAR_BUS_MODE: 1495 *result = slot->host.ios.bus_mode; 1496 break; 1497 case MMCBR_IVAR_BUS_WIDTH: 1498 *result = slot->host.ios.bus_width; 1499 break; 1500 case MMCBR_IVAR_CHIP_SELECT: 1501 *result = slot->host.ios.chip_select; 1502 break; 1503 case MMCBR_IVAR_CLOCK: 1504 *result = slot->host.ios.clock; 1505 break; 1506 case MMCBR_IVAR_F_MIN: 1507 *result = slot->host.f_min; 1508 break; 1509 case MMCBR_IVAR_F_MAX: 1510 *result = slot->host.f_max; 1511 break; 1512 case MMCBR_IVAR_HOST_OCR: 1513 *result = slot->host.host_ocr; 1514 break; 1515 case MMCBR_IVAR_MODE: 1516 *result = slot->host.mode; 1517 break; 1518 case MMCBR_IVAR_OCR: 1519 *result = slot->host.ocr; 1520 break; 1521 case MMCBR_IVAR_POWER_MODE: 1522 *result = slot->host.ios.power_mode; 1523 break; 1524 case MMCBR_IVAR_VDD: 1525 *result = slot->host.ios.vdd; 1526 break; 1527 case MMCBR_IVAR_CAPS: 1528 *result = slot->host.caps; 1529 break; 1530 case MMCBR_IVAR_TIMING: 1531 *result = slot->host.ios.timing; 1532 break; 1533 case MMCBR_IVAR_MAX_DATA: 1534 *result = 65535; 1535 break; 1536 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1537 /* 1538 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1539 */ 1540 *result = 1000000; 1541 break; 1542 } 1543 return (0); 1544 } 1545 1546 int 1547 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1548 uintptr_t value) 1549 { 1550 struct sdhci_slot *slot = device_get_ivars(child); 1551 uint32_t clock, max_clock; 1552 int i; 1553 1554 switch (which) { 1555 default: 1556 return (EINVAL); 1557 case MMCBR_IVAR_BUS_MODE: 1558 slot->host.ios.bus_mode = value; 1559 break; 1560 case MMCBR_IVAR_BUS_WIDTH: 1561 slot->host.ios.bus_width = value; 1562 break; 1563 case MMCBR_IVAR_CHIP_SELECT: 1564 slot->host.ios.chip_select = value; 1565 break; 1566 case MMCBR_IVAR_CLOCK: 1567 if (value > 0) { 1568 max_clock = slot->max_clk; 1569 clock = max_clock; 1570 1571 if (slot->version < SDHCI_SPEC_300) { 1572 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1573 i <<= 1) { 1574 if (clock <= value) 1575 break; 1576 clock >>= 1; 1577 } 1578 } else { 1579 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1580 i += 2) { 1581 if (clock <= value) 1582 break; 1583 clock = max_clock / (i + 2); 1584 } 1585 } 1586 1587 slot->host.ios.clock = clock; 1588 } else 1589 slot->host.ios.clock = 0; 1590 break; 1591 case MMCBR_IVAR_MODE: 1592 slot->host.mode = value; 1593 break; 1594 case MMCBR_IVAR_OCR: 1595 slot->host.ocr = value; 1596 break; 1597 case MMCBR_IVAR_POWER_MODE: 1598 slot->host.ios.power_mode = value; 1599 break; 1600 case MMCBR_IVAR_VDD: 1601 slot->host.ios.vdd = value; 1602 break; 1603 case MMCBR_IVAR_TIMING: 1604 slot->host.ios.timing = value; 1605 break; 1606 case MMCBR_IVAR_CAPS: 1607 case MMCBR_IVAR_HOST_OCR: 1608 case MMCBR_IVAR_F_MIN: 1609 case MMCBR_IVAR_F_MAX: 1610 case MMCBR_IVAR_MAX_DATA: 1611 return (EINVAL); 1612 } 1613 return (0); 1614 } 1615 1616 MODULE_VERSION(sdhci, 1); 1617