1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level"); 59 60 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 61 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 62 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 63 #define RD_MULTI_4(slot, off, ptr, count) \ 64 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 65 66 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 67 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 68 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 69 #define WR_MULTI_4(slot, off, ptr, count) \ 70 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 71 72 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 73 static void sdhci_start(struct sdhci_slot *slot); 74 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 75 76 static void sdhci_card_poll(void *); 77 static void sdhci_card_task(void *, int); 78 79 /* helper routines */ 80 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 81 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 82 #define SDHCI_LOCK_INIT(_slot) \ 83 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 84 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 85 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 86 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 87 88 #define SDHCI_DEFAULT_MAX_FREQ 50 89 90 #define SDHCI_200_MAX_DIVIDER 256 91 #define SDHCI_300_MAX_DIVIDER 2046 92 93 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 94 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 95 96 /* 97 * Broadcom BCM577xx Controller Constants 98 */ 99 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */ 100 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */ 101 102 #define BCM577XX_HOST_CONTROL 0x198 103 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 104 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 105 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 106 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 107 108 109 static void 110 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 111 { 112 if (error != 0) { 113 printf("getaddr: error %d\n", error); 114 return; 115 } 116 *(bus_addr_t *)arg = segs[0].ds_addr; 117 } 118 119 static int 120 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 121 { 122 va_list ap; 123 int retval; 124 125 retval = printf("%s-slot%d: ", 126 device_get_nameunit(slot->bus), slot->num); 127 128 va_start(ap, fmt); 129 retval += vprintf(fmt, ap); 130 va_end(ap); 131 return (retval); 132 } 133 134 static void 135 sdhci_dumpregs(struct sdhci_slot *slot) 136 { 137 slot_printf(slot, 138 "============== REGISTER DUMP ==============\n"); 139 140 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 141 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 142 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 143 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 144 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 145 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 146 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 147 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 148 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 149 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 150 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 151 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 152 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 153 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 154 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 155 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 156 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 157 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 158 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 159 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 160 161 slot_printf(slot, 162 "===========================================\n"); 163 } 164 165 static void 166 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 167 { 168 int timeout; 169 170 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 171 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 172 return; 173 } 174 175 /* Some controllers need this kick or reset won't work. */ 176 if ((mask & SDHCI_RESET_ALL) == 0 && 177 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 178 uint32_t clock; 179 180 /* This is to force an update */ 181 clock = slot->clock; 182 slot->clock = 0; 183 sdhci_set_clock(slot, clock); 184 } 185 186 if (mask & SDHCI_RESET_ALL) { 187 slot->clock = 0; 188 slot->power = 0; 189 } 190 191 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 192 193 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 194 /* 195 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 196 * specification. The reset bit has internal propagation delay, 197 * so a fast read after write returns 0 even if reset process is 198 * in progress. The workaround is to poll for 1 before polling 199 * for 0. In the worst case, if we miss seeing it asserted the 200 * time we spent waiting is enough to ensure the reset finishes. 201 */ 202 timeout = 10000; 203 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 204 if (timeout <= 0) 205 break; 206 timeout--; 207 DELAY(1); 208 } 209 } 210 211 /* Wait max 100 ms */ 212 timeout = 10000; 213 /* Controller clears the bits when it's done */ 214 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 215 if (timeout <= 0) { 216 slot_printf(slot, "Reset 0x%x never completed.\n", 217 mask); 218 sdhci_dumpregs(slot); 219 return; 220 } 221 timeout--; 222 DELAY(10); 223 } 224 } 225 226 static void 227 sdhci_init(struct sdhci_slot *slot) 228 { 229 230 sdhci_reset(slot, SDHCI_RESET_ALL); 231 232 /* Enable interrupts. */ 233 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 236 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 237 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 238 SDHCI_INT_ACMD12ERR; 239 240 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 241 !(slot->opt & SDHCI_NON_REMOVABLE)) { 242 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 243 } 244 245 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 246 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 247 } 248 249 static void 250 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 251 { 252 uint32_t clk_base; 253 uint32_t clk_sel; 254 uint32_t res; 255 uint16_t clk; 256 uint16_t div; 257 int timeout; 258 259 if (clock == slot->clock) 260 return; 261 slot->clock = clock; 262 263 /* Turn off the clock. */ 264 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 265 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 266 /* If no clock requested - left it so. */ 267 if (clock == 0) 268 return; 269 270 /* Determine the clock base frequency */ 271 clk_base = slot->max_clk; 272 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 273 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; 274 275 /* Select clock source appropriate for the requested frequency. */ 276 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 277 clk_base = BCM577XX_ALT_CLOCK_BASE; 278 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); 279 } else { 280 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); 281 } 282 283 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 284 } 285 286 /* Recalculate timeout clock frequency based on the new sd clock. */ 287 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 288 slot->timeout_clk = slot->clock / 1000; 289 290 if (slot->version < SDHCI_SPEC_300) { 291 /* Looking for highest freq <= clock. */ 292 res = clk_base; 293 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 294 if (res <= clock) 295 break; 296 res >>= 1; 297 } 298 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 299 div >>= 1; 300 } 301 else { 302 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 303 if (clock >= clk_base) 304 div = 0; 305 else { 306 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 307 if ((clk_base / div) <= clock) 308 break; 309 } 310 } 311 div >>= 1; 312 } 313 314 if (bootverbose || sdhci_debug) 315 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 316 div, clock, clk_base); 317 318 /* Now we have got divider, set it. */ 319 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 320 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 321 << SDHCI_DIVIDER_HI_SHIFT; 322 323 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 324 /* Enable clock. */ 325 clk |= SDHCI_CLOCK_INT_EN; 326 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 327 /* Wait up to 10 ms until it stabilize. */ 328 timeout = 10; 329 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 330 & SDHCI_CLOCK_INT_STABLE)) { 331 if (timeout == 0) { 332 slot_printf(slot, 333 "Internal clock never stabilised.\n"); 334 sdhci_dumpregs(slot); 335 return; 336 } 337 timeout--; 338 DELAY(1000); 339 } 340 /* Pass clock signal to the bus. */ 341 clk |= SDHCI_CLOCK_CARD_EN; 342 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 343 } 344 345 static void 346 sdhci_set_power(struct sdhci_slot *slot, u_char power) 347 { 348 uint8_t pwr; 349 350 if (slot->power == power) 351 return; 352 353 slot->power = power; 354 355 /* Turn off the power. */ 356 pwr = 0; 357 WR1(slot, SDHCI_POWER_CONTROL, pwr); 358 /* If power down requested - left it so. */ 359 if (power == 0) 360 return; 361 /* Set voltage. */ 362 switch (1 << power) { 363 case MMC_OCR_LOW_VOLTAGE: 364 pwr |= SDHCI_POWER_180; 365 break; 366 case MMC_OCR_290_300: 367 case MMC_OCR_300_310: 368 pwr |= SDHCI_POWER_300; 369 break; 370 case MMC_OCR_320_330: 371 case MMC_OCR_330_340: 372 pwr |= SDHCI_POWER_330; 373 break; 374 } 375 WR1(slot, SDHCI_POWER_CONTROL, pwr); 376 /* Turn on the power. */ 377 pwr |= SDHCI_POWER_ON; 378 WR1(slot, SDHCI_POWER_CONTROL, pwr); 379 380 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 381 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 382 DELAY(10); 383 WR1(slot, SDHCI_POWER_CONTROL, pwr); 384 DELAY(300); 385 } 386 } 387 388 static void 389 sdhci_read_block_pio(struct sdhci_slot *slot) 390 { 391 uint32_t data; 392 char *buffer; 393 size_t left; 394 395 buffer = slot->curcmd->data->data; 396 buffer += slot->offset; 397 /* Transfer one block at a time. */ 398 left = min(512, slot->curcmd->data->len - slot->offset); 399 slot->offset += left; 400 401 /* If we are too fast, broken controllers return zeroes. */ 402 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 403 DELAY(10); 404 /* Handle unaligned and aligned buffer cases. */ 405 if ((intptr_t)buffer & 3) { 406 while (left > 3) { 407 data = RD4(slot, SDHCI_BUFFER); 408 buffer[0] = data; 409 buffer[1] = (data >> 8); 410 buffer[2] = (data >> 16); 411 buffer[3] = (data >> 24); 412 buffer += 4; 413 left -= 4; 414 } 415 } else { 416 RD_MULTI_4(slot, SDHCI_BUFFER, 417 (uint32_t *)buffer, left >> 2); 418 left &= 3; 419 } 420 /* Handle uneven size case. */ 421 if (left > 0) { 422 data = RD4(slot, SDHCI_BUFFER); 423 while (left > 0) { 424 *(buffer++) = data; 425 data >>= 8; 426 left--; 427 } 428 } 429 } 430 431 static void 432 sdhci_write_block_pio(struct sdhci_slot *slot) 433 { 434 uint32_t data = 0; 435 char *buffer; 436 size_t left; 437 438 buffer = slot->curcmd->data->data; 439 buffer += slot->offset; 440 /* Transfer one block at a time. */ 441 left = min(512, slot->curcmd->data->len - slot->offset); 442 slot->offset += left; 443 444 /* Handle unaligned and aligned buffer cases. */ 445 if ((intptr_t)buffer & 3) { 446 while (left > 3) { 447 data = buffer[0] + 448 (buffer[1] << 8) + 449 (buffer[2] << 16) + 450 (buffer[3] << 24); 451 left -= 4; 452 buffer += 4; 453 WR4(slot, SDHCI_BUFFER, data); 454 } 455 } else { 456 WR_MULTI_4(slot, SDHCI_BUFFER, 457 (uint32_t *)buffer, left >> 2); 458 left &= 3; 459 } 460 /* Handle uneven size case. */ 461 if (left > 0) { 462 while (left > 0) { 463 data <<= 8; 464 data += *(buffer++); 465 left--; 466 } 467 WR4(slot, SDHCI_BUFFER, data); 468 } 469 } 470 471 static void 472 sdhci_transfer_pio(struct sdhci_slot *slot) 473 { 474 475 /* Read as many blocks as possible. */ 476 if (slot->curcmd->data->flags & MMC_DATA_READ) { 477 while (RD4(slot, SDHCI_PRESENT_STATE) & 478 SDHCI_DATA_AVAILABLE) { 479 sdhci_read_block_pio(slot); 480 if (slot->offset >= slot->curcmd->data->len) 481 break; 482 } 483 } else { 484 while (RD4(slot, SDHCI_PRESENT_STATE) & 485 SDHCI_SPACE_AVAILABLE) { 486 sdhci_write_block_pio(slot); 487 if (slot->offset >= slot->curcmd->data->len) 488 break; 489 } 490 } 491 } 492 493 static void 494 sdhci_card_task(void *arg, int pending) 495 { 496 struct sdhci_slot *slot = arg; 497 498 SDHCI_LOCK(slot); 499 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 500 if (slot->dev == NULL) { 501 /* If card is present - attach mmc bus. */ 502 if (bootverbose || sdhci_debug) 503 slot_printf(slot, "Card inserted\n"); 504 slot->dev = device_add_child(slot->bus, "mmc", -1); 505 device_set_ivars(slot->dev, slot); 506 SDHCI_UNLOCK(slot); 507 device_probe_and_attach(slot->dev); 508 } else 509 SDHCI_UNLOCK(slot); 510 } else { 511 if (slot->dev != NULL) { 512 /* If no card present - detach mmc bus. */ 513 if (bootverbose || sdhci_debug) 514 slot_printf(slot, "Card removed\n"); 515 device_t d = slot->dev; 516 slot->dev = NULL; 517 SDHCI_UNLOCK(slot); 518 device_delete_child(slot->bus, d); 519 } else 520 SDHCI_UNLOCK(slot); 521 } 522 } 523 524 static void 525 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 526 { 527 bool was_present; 528 529 /* 530 * If there was no card and now there is one, schedule the task to 531 * create the child device after a short delay. The delay is to 532 * debounce the card insert (sometimes the card detect pin stabilizes 533 * before the other pins have made good contact). 534 * 535 * If there was a card present and now it's gone, immediately schedule 536 * the task to delete the child device. No debouncing -- gone is gone, 537 * because once power is removed, a full card re-init is needed, and 538 * that happens by deleting and recreating the child device. 539 */ 540 was_present = slot->dev != NULL; 541 if (!was_present && is_present) { 542 taskqueue_enqueue_timeout(taskqueue_swi_giant, 543 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 544 } else if (was_present && !is_present) { 545 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 546 } 547 } 548 549 void 550 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 551 { 552 553 SDHCI_LOCK(slot); 554 sdhci_handle_card_present_locked(slot, is_present); 555 SDHCI_UNLOCK(slot); 556 } 557 558 static void 559 sdhci_card_poll(void *arg) 560 { 561 struct sdhci_slot *slot = arg; 562 563 sdhci_handle_card_present(slot, 564 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 565 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 566 sdhci_card_poll, slot); 567 } 568 569 int 570 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 571 { 572 uint32_t caps, freq; 573 int err; 574 575 SDHCI_LOCK_INIT(slot); 576 slot->num = num; 577 slot->bus = dev; 578 579 /* Allocate DMA tag. */ 580 err = bus_dma_tag_create(bus_get_dma_tag(dev), 581 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 582 BUS_SPACE_MAXADDR, NULL, NULL, 583 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 584 BUS_DMA_ALLOCNOW, NULL, NULL, 585 &slot->dmatag); 586 if (err != 0) { 587 device_printf(dev, "Can't create DMA tag\n"); 588 SDHCI_LOCK_DESTROY(slot); 589 return (err); 590 } 591 /* Allocate DMA memory. */ 592 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 593 BUS_DMA_NOWAIT, &slot->dmamap); 594 if (err != 0) { 595 device_printf(dev, "Can't alloc DMA memory\n"); 596 SDHCI_LOCK_DESTROY(slot); 597 return (err); 598 } 599 /* Map the memory. */ 600 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 601 (void *)slot->dmamem, DMA_BLOCK_SIZE, 602 sdhci_getaddr, &slot->paddr, 0); 603 if (err != 0 || slot->paddr == 0) { 604 device_printf(dev, "Can't load DMA memory\n"); 605 SDHCI_LOCK_DESTROY(slot); 606 if(err) 607 return (err); 608 else 609 return (EFAULT); 610 } 611 612 /* Initialize slot. */ 613 sdhci_init(slot); 614 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 615 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 616 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 617 caps = slot->caps; 618 else 619 caps = RD4(slot, SDHCI_CAPABILITIES); 620 /* Calculate base clock frequency. */ 621 if (slot->version >= SDHCI_SPEC_300) 622 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 623 SDHCI_CLOCK_BASE_SHIFT; 624 else 625 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 626 SDHCI_CLOCK_BASE_SHIFT; 627 if (freq != 0) 628 slot->max_clk = freq * 1000000; 629 /* 630 * If the frequency wasn't in the capabilities and the hardware driver 631 * hasn't already set max_clk we're probably not going to work right 632 * with an assumption, so complain about it. 633 */ 634 if (slot->max_clk == 0) { 635 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 636 device_printf(dev, "Hardware doesn't specify base clock " 637 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 638 } 639 /* Calculate/set timeout clock frequency. */ 640 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 641 slot->timeout_clk = slot->max_clk / 1000; 642 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 643 slot->timeout_clk = 1000; 644 } else { 645 slot->timeout_clk = 646 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 647 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 648 slot->timeout_clk *= 1000; 649 } 650 /* 651 * If the frequency wasn't in the capabilities and the hardware driver 652 * hasn't already set timeout_clk we'll probably work okay using the 653 * max timeout, but still mention it. 654 */ 655 if (slot->timeout_clk == 0) { 656 device_printf(dev, "Hardware doesn't specify timeout clock " 657 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 658 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 659 } 660 661 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 662 slot->host.f_max = slot->max_clk; 663 slot->host.host_ocr = 0; 664 if (caps & SDHCI_CAN_VDD_330) 665 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 666 if (caps & SDHCI_CAN_VDD_300) 667 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 668 if (caps & SDHCI_CAN_VDD_180) 669 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 670 if (slot->host.host_ocr == 0) { 671 device_printf(dev, "Hardware doesn't report any " 672 "support voltages.\n"); 673 } 674 slot->host.caps = MMC_CAP_4_BIT_DATA; 675 if (caps & SDHCI_CAN_DO_8BITBUS) 676 slot->host.caps |= MMC_CAP_8_BIT_DATA; 677 if (caps & SDHCI_CAN_DO_HISPD) 678 slot->host.caps |= MMC_CAP_HSPEED; 679 /* Decide if we have usable DMA. */ 680 if (caps & SDHCI_CAN_DO_DMA) 681 slot->opt |= SDHCI_HAVE_DMA; 682 683 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 684 slot->opt &= ~SDHCI_HAVE_DMA; 685 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 686 slot->opt |= SDHCI_HAVE_DMA; 687 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 688 slot->opt |= SDHCI_NON_REMOVABLE; 689 690 /* 691 * Use platform-provided transfer backend 692 * with PIO as a fallback mechanism 693 */ 694 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 695 slot->opt &= ~SDHCI_HAVE_DMA; 696 697 if (bootverbose || sdhci_debug) { 698 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 699 slot->max_clk / 1000000, 700 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 701 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 702 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" : 703 "1bit"), 704 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 705 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 706 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 707 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 708 sdhci_dumpregs(slot); 709 } 710 711 slot->timeout = 10; 712 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 713 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 714 "timeout", CTLFLAG_RW, &slot->timeout, 0, 715 "Maximum timeout for SDHCI transfers (in secs)"); 716 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 717 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 718 sdhci_card_task, slot); 719 callout_init(&slot->card_poll_callout, 1); 720 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 721 722 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 723 !(slot->opt & SDHCI_NON_REMOVABLE)) { 724 callout_reset(&slot->card_poll_callout, 725 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 726 } 727 728 return (0); 729 } 730 731 void 732 sdhci_start_slot(struct sdhci_slot *slot) 733 { 734 sdhci_card_task(slot, 0); 735 } 736 737 int 738 sdhci_cleanup_slot(struct sdhci_slot *slot) 739 { 740 device_t d; 741 742 callout_drain(&slot->timeout_callout); 743 callout_drain(&slot->card_poll_callout); 744 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 745 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 746 747 SDHCI_LOCK(slot); 748 d = slot->dev; 749 slot->dev = NULL; 750 SDHCI_UNLOCK(slot); 751 if (d != NULL) 752 device_delete_child(slot->bus, d); 753 754 SDHCI_LOCK(slot); 755 sdhci_reset(slot, SDHCI_RESET_ALL); 756 SDHCI_UNLOCK(slot); 757 bus_dmamap_unload(slot->dmatag, slot->dmamap); 758 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 759 bus_dma_tag_destroy(slot->dmatag); 760 761 SDHCI_LOCK_DESTROY(slot); 762 763 return (0); 764 } 765 766 int 767 sdhci_generic_suspend(struct sdhci_slot *slot) 768 { 769 sdhci_reset(slot, SDHCI_RESET_ALL); 770 771 return (0); 772 } 773 774 int 775 sdhci_generic_resume(struct sdhci_slot *slot) 776 { 777 sdhci_init(slot); 778 779 return (0); 780 } 781 782 uint32_t 783 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 784 { 785 if (slot->version >= SDHCI_SPEC_300) 786 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 787 else 788 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 789 } 790 791 bool 792 sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot) 793 { 794 795 if (slot->opt & SDHCI_NON_REMOVABLE) 796 return true; 797 798 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 799 } 800 801 int 802 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 803 { 804 struct sdhci_slot *slot = device_get_ivars(reqdev); 805 struct mmc_ios *ios = &slot->host.ios; 806 807 SDHCI_LOCK(slot); 808 /* Do full reset on bus power down to clear from any state. */ 809 if (ios->power_mode == power_off) { 810 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 811 sdhci_init(slot); 812 } 813 /* Configure the bus. */ 814 sdhci_set_clock(slot, ios->clock); 815 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 816 if (ios->bus_width == bus_width_8) { 817 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 818 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 819 } else if (ios->bus_width == bus_width_4) { 820 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 821 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 822 } else if (ios->bus_width == bus_width_1) { 823 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 824 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 825 } else { 826 panic("Invalid bus width: %d", ios->bus_width); 827 } 828 if (ios->timing == bus_timing_hs && 829 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 830 slot->hostctrl |= SDHCI_CTRL_HISPD; 831 else 832 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 833 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 834 /* Some controllers like reset after bus changes. */ 835 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 836 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 837 838 SDHCI_UNLOCK(slot); 839 return (0); 840 } 841 842 static void 843 sdhci_req_done(struct sdhci_slot *slot) 844 { 845 struct mmc_request *req; 846 847 if (slot->req != NULL && slot->curcmd != NULL) { 848 callout_stop(&slot->timeout_callout); 849 req = slot->req; 850 slot->req = NULL; 851 slot->curcmd = NULL; 852 req->done(req); 853 } 854 } 855 856 static void 857 sdhci_timeout(void *arg) 858 { 859 struct sdhci_slot *slot = arg; 860 861 if (slot->curcmd != NULL) { 862 slot_printf(slot, " Controller timeout\n"); 863 sdhci_dumpregs(slot); 864 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 865 slot->curcmd->error = MMC_ERR_TIMEOUT; 866 sdhci_req_done(slot); 867 } else { 868 slot_printf(slot, " Spurious timeout - no active command\n"); 869 } 870 } 871 872 static void 873 sdhci_set_transfer_mode(struct sdhci_slot *slot, 874 struct mmc_data *data) 875 { 876 uint16_t mode; 877 878 if (data == NULL) 879 return; 880 881 mode = SDHCI_TRNS_BLK_CNT_EN; 882 if (data->len > 512) 883 mode |= SDHCI_TRNS_MULTI; 884 if (data->flags & MMC_DATA_READ) 885 mode |= SDHCI_TRNS_READ; 886 if (slot->req->stop) 887 mode |= SDHCI_TRNS_ACMD12; 888 if (slot->flags & SDHCI_USE_DMA) 889 mode |= SDHCI_TRNS_DMA; 890 891 WR2(slot, SDHCI_TRANSFER_MODE, mode); 892 } 893 894 static void 895 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 896 { 897 int flags, timeout; 898 uint32_t mask; 899 900 slot->curcmd = cmd; 901 slot->cmd_done = 0; 902 903 cmd->error = MMC_ERR_NONE; 904 905 /* This flags combination is not supported by controller. */ 906 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 907 slot_printf(slot, "Unsupported response type!\n"); 908 cmd->error = MMC_ERR_FAILED; 909 sdhci_req_done(slot); 910 return; 911 } 912 913 /* Do not issue command if there is no card, clock or power. 914 * Controller will not detect timeout without clock active. */ 915 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 916 slot->power == 0 || 917 slot->clock == 0) { 918 cmd->error = MMC_ERR_FAILED; 919 sdhci_req_done(slot); 920 return; 921 } 922 /* Always wait for free CMD bus. */ 923 mask = SDHCI_CMD_INHIBIT; 924 /* Wait for free DAT if we have data or busy signal. */ 925 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 926 mask |= SDHCI_DAT_INHIBIT; 927 /* We shouldn't wait for DAT for stop commands. */ 928 if (cmd == slot->req->stop) 929 mask &= ~SDHCI_DAT_INHIBIT; 930 /* 931 * Wait for bus no more then 250 ms. Typically there will be no wait 932 * here at all, but when writing a crash dump we may be bypassing the 933 * host platform's interrupt handler, and in some cases that handler 934 * may be working around hardware quirks such as not respecting r1b 935 * busy indications. In those cases, this wait-loop serves the purpose 936 * of waiting for the prior command and data transfers to be done, and 937 * SD cards are allowed to take up to 250ms for write and erase ops. 938 * (It's usually more like 20-30ms in the real world.) 939 */ 940 timeout = 250; 941 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 942 if (timeout == 0) { 943 slot_printf(slot, "Controller never released " 944 "inhibit bit(s).\n"); 945 sdhci_dumpregs(slot); 946 cmd->error = MMC_ERR_FAILED; 947 sdhci_req_done(slot); 948 return; 949 } 950 timeout--; 951 DELAY(1000); 952 } 953 954 /* Prepare command flags. */ 955 if (!(cmd->flags & MMC_RSP_PRESENT)) 956 flags = SDHCI_CMD_RESP_NONE; 957 else if (cmd->flags & MMC_RSP_136) 958 flags = SDHCI_CMD_RESP_LONG; 959 else if (cmd->flags & MMC_RSP_BUSY) 960 flags = SDHCI_CMD_RESP_SHORT_BUSY; 961 else 962 flags = SDHCI_CMD_RESP_SHORT; 963 if (cmd->flags & MMC_RSP_CRC) 964 flags |= SDHCI_CMD_CRC; 965 if (cmd->flags & MMC_RSP_OPCODE) 966 flags |= SDHCI_CMD_INDEX; 967 if (cmd->data) 968 flags |= SDHCI_CMD_DATA; 969 if (cmd->opcode == MMC_STOP_TRANSMISSION) 970 flags |= SDHCI_CMD_TYPE_ABORT; 971 /* Prepare data. */ 972 sdhci_start_data(slot, cmd->data); 973 /* 974 * Interrupt aggregation: To reduce total number of interrupts 975 * group response interrupt with data interrupt when possible. 976 * If there going to be data interrupt, mask response one. 977 */ 978 if (slot->data_done == 0) { 979 WR4(slot, SDHCI_SIGNAL_ENABLE, 980 slot->intmask &= ~SDHCI_INT_RESPONSE); 981 } 982 /* Set command argument. */ 983 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 984 /* Set data transfer mode. */ 985 sdhci_set_transfer_mode(slot, cmd->data); 986 /* Start command. */ 987 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 988 /* Start timeout callout. */ 989 callout_reset(&slot->timeout_callout, slot->timeout * hz, 990 sdhci_timeout, slot); 991 } 992 993 static void 994 sdhci_finish_command(struct sdhci_slot *slot) 995 { 996 int i; 997 998 slot->cmd_done = 1; 999 /* Interrupt aggregation: Restore command interrupt. 1000 * Main restore point for the case when command interrupt 1001 * happened first. */ 1002 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1003 /* In case of error - reset host and return. */ 1004 if (slot->curcmd->error) { 1005 sdhci_reset(slot, SDHCI_RESET_CMD); 1006 sdhci_reset(slot, SDHCI_RESET_DATA); 1007 sdhci_start(slot); 1008 return; 1009 } 1010 /* If command has response - fetch it. */ 1011 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1012 if (slot->curcmd->flags & MMC_RSP_136) { 1013 /* CRC is stripped so we need one byte shift. */ 1014 uint8_t extra = 0; 1015 for (i = 0; i < 4; i++) { 1016 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1017 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1018 slot->curcmd->resp[3 - i] = val; 1019 else { 1020 slot->curcmd->resp[3 - i] = 1021 (val << 8) | extra; 1022 extra = val >> 24; 1023 } 1024 } 1025 } else 1026 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1027 } 1028 /* If data ready - finish. */ 1029 if (slot->data_done) 1030 sdhci_start(slot); 1031 } 1032 1033 static void 1034 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1035 { 1036 uint32_t target_timeout, current_timeout; 1037 uint8_t div; 1038 1039 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1040 slot->data_done = 1; 1041 return; 1042 } 1043 1044 slot->data_done = 0; 1045 1046 /* Calculate and set data timeout.*/ 1047 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1048 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1049 div = 0xE; 1050 } else { 1051 target_timeout = 1000000; 1052 div = 0; 1053 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1054 while (current_timeout < target_timeout && div < 0xE) { 1055 ++div; 1056 current_timeout <<= 1; 1057 } 1058 /* Compensate for an off-by-one error in the CaFe chip.*/ 1059 if (div < 0xE && 1060 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1061 ++div; 1062 } 1063 } 1064 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1065 1066 if (data == NULL) 1067 return; 1068 1069 /* Use DMA if possible. */ 1070 if ((slot->opt & SDHCI_HAVE_DMA)) 1071 slot->flags |= SDHCI_USE_DMA; 1072 /* If data is small, broken DMA may return zeroes instead of data, */ 1073 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1074 (data->len <= 512)) 1075 slot->flags &= ~SDHCI_USE_DMA; 1076 /* Some controllers require even block sizes. */ 1077 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1078 ((data->len) & 0x3)) 1079 slot->flags &= ~SDHCI_USE_DMA; 1080 /* Load DMA buffer. */ 1081 if (slot->flags & SDHCI_USE_DMA) { 1082 if (data->flags & MMC_DATA_READ) 1083 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1084 BUS_DMASYNC_PREREAD); 1085 else { 1086 memcpy(slot->dmamem, data->data, 1087 (data->len < DMA_BLOCK_SIZE) ? 1088 data->len : DMA_BLOCK_SIZE); 1089 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1090 BUS_DMASYNC_PREWRITE); 1091 } 1092 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1093 /* Interrupt aggregation: Mask border interrupt 1094 * for the last page and unmask else. */ 1095 if (data->len == DMA_BLOCK_SIZE) 1096 slot->intmask &= ~SDHCI_INT_DMA_END; 1097 else 1098 slot->intmask |= SDHCI_INT_DMA_END; 1099 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1100 } 1101 /* Current data offset for both PIO and DMA. */ 1102 slot->offset = 0; 1103 /* Set block size and request IRQ on 4K border. */ 1104 WR2(slot, SDHCI_BLOCK_SIZE, 1105 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1106 /* Set block count. */ 1107 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1108 } 1109 1110 void 1111 sdhci_finish_data(struct sdhci_slot *slot) 1112 { 1113 struct mmc_data *data = slot->curcmd->data; 1114 1115 /* Interrupt aggregation: Restore command interrupt. 1116 * Auxiliary restore point for the case when data interrupt 1117 * happened first. */ 1118 if (!slot->cmd_done) { 1119 WR4(slot, SDHCI_SIGNAL_ENABLE, 1120 slot->intmask |= SDHCI_INT_RESPONSE); 1121 } 1122 /* Unload rest of data from DMA buffer. */ 1123 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1124 if (data->flags & MMC_DATA_READ) { 1125 size_t left = data->len - slot->offset; 1126 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1127 BUS_DMASYNC_POSTREAD); 1128 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1129 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1130 } else 1131 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1132 BUS_DMASYNC_POSTWRITE); 1133 } 1134 slot->data_done = 1; 1135 /* If there was error - reset the host. */ 1136 if (slot->curcmd->error) { 1137 sdhci_reset(slot, SDHCI_RESET_CMD); 1138 sdhci_reset(slot, SDHCI_RESET_DATA); 1139 sdhci_start(slot); 1140 return; 1141 } 1142 /* If we already have command response - finish. */ 1143 if (slot->cmd_done) 1144 sdhci_start(slot); 1145 } 1146 1147 static void 1148 sdhci_start(struct sdhci_slot *slot) 1149 { 1150 struct mmc_request *req; 1151 1152 req = slot->req; 1153 if (req == NULL) 1154 return; 1155 1156 if (!(slot->flags & CMD_STARTED)) { 1157 slot->flags |= CMD_STARTED; 1158 sdhci_start_command(slot, req->cmd); 1159 return; 1160 } 1161 /* We don't need this until using Auto-CMD12 feature 1162 if (!(slot->flags & STOP_STARTED) && req->stop) { 1163 slot->flags |= STOP_STARTED; 1164 sdhci_start_command(slot, req->stop); 1165 return; 1166 } 1167 */ 1168 if (sdhci_debug > 1) 1169 slot_printf(slot, "result: %d\n", req->cmd->error); 1170 if (!req->cmd->error && 1171 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1172 sdhci_reset(slot, SDHCI_RESET_CMD); 1173 sdhci_reset(slot, SDHCI_RESET_DATA); 1174 } 1175 1176 sdhci_req_done(slot); 1177 } 1178 1179 int 1180 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1181 { 1182 struct sdhci_slot *slot = device_get_ivars(reqdev); 1183 1184 SDHCI_LOCK(slot); 1185 if (slot->req != NULL) { 1186 SDHCI_UNLOCK(slot); 1187 return (EBUSY); 1188 } 1189 if (sdhci_debug > 1) { 1190 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1191 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1192 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1193 (req->cmd->data)?req->cmd->data->flags:0); 1194 } 1195 slot->req = req; 1196 slot->flags = 0; 1197 sdhci_start(slot); 1198 SDHCI_UNLOCK(slot); 1199 if (dumping) { 1200 while (slot->req != NULL) { 1201 sdhci_generic_intr(slot); 1202 DELAY(10); 1203 } 1204 } 1205 return (0); 1206 } 1207 1208 int 1209 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1210 { 1211 struct sdhci_slot *slot = device_get_ivars(reqdev); 1212 uint32_t val; 1213 1214 SDHCI_LOCK(slot); 1215 val = RD4(slot, SDHCI_PRESENT_STATE); 1216 SDHCI_UNLOCK(slot); 1217 return (!(val & SDHCI_WRITE_PROTECT)); 1218 } 1219 1220 int 1221 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1222 { 1223 struct sdhci_slot *slot = device_get_ivars(reqdev); 1224 int err = 0; 1225 1226 SDHCI_LOCK(slot); 1227 while (slot->bus_busy) 1228 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1229 slot->bus_busy++; 1230 /* Activate led. */ 1231 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1232 SDHCI_UNLOCK(slot); 1233 return (err); 1234 } 1235 1236 int 1237 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1238 { 1239 struct sdhci_slot *slot = device_get_ivars(reqdev); 1240 1241 SDHCI_LOCK(slot); 1242 /* Deactivate led. */ 1243 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1244 slot->bus_busy--; 1245 SDHCI_UNLOCK(slot); 1246 wakeup(slot); 1247 return (0); 1248 } 1249 1250 static void 1251 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1252 { 1253 1254 if (!slot->curcmd) { 1255 slot_printf(slot, "Got command interrupt 0x%08x, but " 1256 "there is no active command.\n", intmask); 1257 sdhci_dumpregs(slot); 1258 return; 1259 } 1260 if (intmask & SDHCI_INT_TIMEOUT) 1261 slot->curcmd->error = MMC_ERR_TIMEOUT; 1262 else if (intmask & SDHCI_INT_CRC) 1263 slot->curcmd->error = MMC_ERR_BADCRC; 1264 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1265 slot->curcmd->error = MMC_ERR_FIFO; 1266 1267 sdhci_finish_command(slot); 1268 } 1269 1270 static void 1271 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1272 { 1273 1274 if (!slot->curcmd) { 1275 slot_printf(slot, "Got data interrupt 0x%08x, but " 1276 "there is no active command.\n", intmask); 1277 sdhci_dumpregs(slot); 1278 return; 1279 } 1280 if (slot->curcmd->data == NULL && 1281 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1282 slot_printf(slot, "Got data interrupt 0x%08x, but " 1283 "there is no active data operation.\n", 1284 intmask); 1285 sdhci_dumpregs(slot); 1286 return; 1287 } 1288 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1289 slot->curcmd->error = MMC_ERR_TIMEOUT; 1290 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1291 slot->curcmd->error = MMC_ERR_BADCRC; 1292 if (slot->curcmd->data == NULL && 1293 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1294 SDHCI_INT_DMA_END))) { 1295 slot_printf(slot, "Got data interrupt 0x%08x, but " 1296 "there is busy-only command.\n", intmask); 1297 sdhci_dumpregs(slot); 1298 slot->curcmd->error = MMC_ERR_INVALID; 1299 } 1300 if (slot->curcmd->error) { 1301 /* No need to continue after any error. */ 1302 goto done; 1303 } 1304 1305 /* Handle PIO interrupt. */ 1306 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1307 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1308 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1309 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1310 slot->flags |= PLATFORM_DATA_STARTED; 1311 } else 1312 sdhci_transfer_pio(slot); 1313 } 1314 /* Handle DMA border. */ 1315 if (intmask & SDHCI_INT_DMA_END) { 1316 struct mmc_data *data = slot->curcmd->data; 1317 size_t left; 1318 1319 /* Unload DMA buffer... */ 1320 left = data->len - slot->offset; 1321 if (data->flags & MMC_DATA_READ) { 1322 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1323 BUS_DMASYNC_POSTREAD); 1324 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1325 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1326 } else { 1327 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1328 BUS_DMASYNC_POSTWRITE); 1329 } 1330 /* ... and reload it again. */ 1331 slot->offset += DMA_BLOCK_SIZE; 1332 left = data->len - slot->offset; 1333 if (data->flags & MMC_DATA_READ) { 1334 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1335 BUS_DMASYNC_PREREAD); 1336 } else { 1337 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1338 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1339 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1340 BUS_DMASYNC_PREWRITE); 1341 } 1342 /* Interrupt aggregation: Mask border interrupt 1343 * for the last page. */ 1344 if (left == DMA_BLOCK_SIZE) { 1345 slot->intmask &= ~SDHCI_INT_DMA_END; 1346 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1347 } 1348 /* Restart DMA. */ 1349 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1350 } 1351 /* We have got all data. */ 1352 if (intmask & SDHCI_INT_DATA_END) { 1353 if (slot->flags & PLATFORM_DATA_STARTED) { 1354 slot->flags &= ~PLATFORM_DATA_STARTED; 1355 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1356 } else 1357 sdhci_finish_data(slot); 1358 } 1359 done: 1360 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1361 if (slot->flags & PLATFORM_DATA_STARTED) { 1362 slot->flags &= ~PLATFORM_DATA_STARTED; 1363 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1364 } else 1365 sdhci_finish_data(slot); 1366 return; 1367 } 1368 } 1369 1370 static void 1371 sdhci_acmd_irq(struct sdhci_slot *slot) 1372 { 1373 uint16_t err; 1374 1375 err = RD4(slot, SDHCI_ACMD12_ERR); 1376 if (!slot->curcmd) { 1377 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1378 "there is no active command.\n", err); 1379 sdhci_dumpregs(slot); 1380 return; 1381 } 1382 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1383 sdhci_reset(slot, SDHCI_RESET_CMD); 1384 } 1385 1386 void 1387 sdhci_generic_intr(struct sdhci_slot *slot) 1388 { 1389 uint32_t intmask, present; 1390 1391 SDHCI_LOCK(slot); 1392 /* Read slot interrupt status. */ 1393 intmask = RD4(slot, SDHCI_INT_STATUS); 1394 if (intmask == 0 || intmask == 0xffffffff) { 1395 SDHCI_UNLOCK(slot); 1396 return; 1397 } 1398 if (sdhci_debug > 2) 1399 slot_printf(slot, "Interrupt %#x\n", intmask); 1400 1401 /* Handle card presence interrupts. */ 1402 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1403 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1404 slot->intmask &= 1405 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1406 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1407 SDHCI_INT_CARD_INSERT; 1408 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1409 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1410 WR4(slot, SDHCI_INT_STATUS, intmask & 1411 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1412 sdhci_handle_card_present_locked(slot, present); 1413 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1414 } 1415 /* Handle command interrupts. */ 1416 if (intmask & SDHCI_INT_CMD_MASK) { 1417 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1418 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1419 } 1420 /* Handle data interrupts. */ 1421 if (intmask & SDHCI_INT_DATA_MASK) { 1422 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1423 /* Dont call data_irq in case of errored command */ 1424 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1425 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1426 } 1427 /* Handle AutoCMD12 error interrupt. */ 1428 if (intmask & SDHCI_INT_ACMD12ERR) { 1429 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1430 sdhci_acmd_irq(slot); 1431 } 1432 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1433 intmask &= ~SDHCI_INT_ACMD12ERR; 1434 intmask &= ~SDHCI_INT_ERROR; 1435 /* Handle bus power interrupt. */ 1436 if (intmask & SDHCI_INT_BUS_POWER) { 1437 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1438 slot_printf(slot, 1439 "Card is consuming too much power!\n"); 1440 intmask &= ~SDHCI_INT_BUS_POWER; 1441 } 1442 /* The rest is unknown. */ 1443 if (intmask) { 1444 WR4(slot, SDHCI_INT_STATUS, intmask); 1445 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1446 intmask); 1447 sdhci_dumpregs(slot); 1448 } 1449 1450 SDHCI_UNLOCK(slot); 1451 } 1452 1453 int 1454 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1455 { 1456 struct sdhci_slot *slot = device_get_ivars(child); 1457 1458 switch (which) { 1459 default: 1460 return (EINVAL); 1461 case MMCBR_IVAR_BUS_MODE: 1462 *result = slot->host.ios.bus_mode; 1463 break; 1464 case MMCBR_IVAR_BUS_WIDTH: 1465 *result = slot->host.ios.bus_width; 1466 break; 1467 case MMCBR_IVAR_CHIP_SELECT: 1468 *result = slot->host.ios.chip_select; 1469 break; 1470 case MMCBR_IVAR_CLOCK: 1471 *result = slot->host.ios.clock; 1472 break; 1473 case MMCBR_IVAR_F_MIN: 1474 *result = slot->host.f_min; 1475 break; 1476 case MMCBR_IVAR_F_MAX: 1477 *result = slot->host.f_max; 1478 break; 1479 case MMCBR_IVAR_HOST_OCR: 1480 *result = slot->host.host_ocr; 1481 break; 1482 case MMCBR_IVAR_MODE: 1483 *result = slot->host.mode; 1484 break; 1485 case MMCBR_IVAR_OCR: 1486 *result = slot->host.ocr; 1487 break; 1488 case MMCBR_IVAR_POWER_MODE: 1489 *result = slot->host.ios.power_mode; 1490 break; 1491 case MMCBR_IVAR_VDD: 1492 *result = slot->host.ios.vdd; 1493 break; 1494 case MMCBR_IVAR_CAPS: 1495 *result = slot->host.caps; 1496 break; 1497 case MMCBR_IVAR_TIMING: 1498 *result = slot->host.ios.timing; 1499 break; 1500 case MMCBR_IVAR_MAX_DATA: 1501 *result = 65535; 1502 break; 1503 } 1504 return (0); 1505 } 1506 1507 int 1508 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1509 { 1510 struct sdhci_slot *slot = device_get_ivars(child); 1511 1512 switch (which) { 1513 default: 1514 return (EINVAL); 1515 case MMCBR_IVAR_BUS_MODE: 1516 slot->host.ios.bus_mode = value; 1517 break; 1518 case MMCBR_IVAR_BUS_WIDTH: 1519 slot->host.ios.bus_width = value; 1520 break; 1521 case MMCBR_IVAR_CHIP_SELECT: 1522 slot->host.ios.chip_select = value; 1523 break; 1524 case MMCBR_IVAR_CLOCK: 1525 if (value > 0) { 1526 uint32_t max_clock; 1527 uint32_t clock; 1528 int i; 1529 1530 max_clock = slot->max_clk; 1531 clock = max_clock; 1532 1533 if (slot->version < SDHCI_SPEC_300) { 1534 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1535 i <<= 1) { 1536 if (clock <= value) 1537 break; 1538 clock >>= 1; 1539 } 1540 } 1541 else { 1542 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1543 i += 2) { 1544 if (clock <= value) 1545 break; 1546 clock = max_clock / (i + 2); 1547 } 1548 } 1549 1550 slot->host.ios.clock = clock; 1551 } else 1552 slot->host.ios.clock = 0; 1553 break; 1554 case MMCBR_IVAR_MODE: 1555 slot->host.mode = value; 1556 break; 1557 case MMCBR_IVAR_OCR: 1558 slot->host.ocr = value; 1559 break; 1560 case MMCBR_IVAR_POWER_MODE: 1561 slot->host.ios.power_mode = value; 1562 break; 1563 case MMCBR_IVAR_VDD: 1564 slot->host.ios.vdd = value; 1565 break; 1566 case MMCBR_IVAR_TIMING: 1567 slot->host.ios.timing = value; 1568 break; 1569 case MMCBR_IVAR_CAPS: 1570 case MMCBR_IVAR_HOST_OCR: 1571 case MMCBR_IVAR_F_MIN: 1572 case MMCBR_IVAR_F_MAX: 1573 case MMCBR_IVAR_MAX_DATA: 1574 return (EINVAL); 1575 } 1576 return (0); 1577 } 1578 1579 MODULE_VERSION(sdhci, 1); 1580