1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/callout.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/kobj.h> 37 #include <sys/libkern.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/sbuf.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/stdarg.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcreg.h> 54 #include <dev/mmc/mmcbrvar.h> 55 56 #include <dev/sdhci/sdhci.h> 57 58 #include <cam/cam.h> 59 #include <cam/cam_ccb.h> 60 #include <cam/cam_debug.h> 61 #include <cam/cam_sim.h> 62 #include <cam/cam_xpt_sim.h> 63 64 #include "mmcbr_if.h" 65 #include "sdhci_if.h" 66 67 #include "opt_mmccam.h" 68 69 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 70 "sdhci driver"); 71 72 static int sdhci_debug = 0; 73 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 74 "Debug level"); 75 u_int sdhci_quirk_clear = 0; 76 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 77 0, "Mask of quirks to clear"); 78 u_int sdhci_quirk_set = 0; 79 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 80 "Mask of quirks to set"); 81 82 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 83 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 84 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 85 #define RD_MULTI_4(slot, off, ptr, count) \ 86 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 87 88 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 89 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 90 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 91 #define WR_MULTI_4(slot, off, ptr, count) \ 92 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 93 94 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err); 95 static void sdhci_card_poll(void *arg); 96 static void sdhci_card_task(void *arg, int pending); 97 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask); 98 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask); 99 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 100 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot, 101 bool is_present); 102 static void sdhci_finish_command(struct sdhci_slot *slot); 103 static void sdhci_init(struct sdhci_slot *slot); 104 static void sdhci_read_block_pio(struct sdhci_slot *slot); 105 static void sdhci_req_done(struct sdhci_slot *slot); 106 static void sdhci_req_wakeup(struct mmc_request *req); 107 static void sdhci_retune(void *arg); 108 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 109 static void sdhci_set_power(struct sdhci_slot *slot, u_char power); 110 static void sdhci_set_transfer_mode(struct sdhci_slot *slot, 111 const struct mmc_data *data); 112 static void sdhci_start(struct sdhci_slot *slot); 113 static void sdhci_timeout(void *arg); 114 static void sdhci_start_command(struct sdhci_slot *slot, 115 struct mmc_command *cmd); 116 static void sdhci_start_data(struct sdhci_slot *slot, 117 const struct mmc_data *data); 118 static void sdhci_write_block_pio(struct sdhci_slot *slot); 119 static void sdhci_transfer_pio(struct sdhci_slot *slot); 120 121 #ifdef MMCCAM 122 /* CAM-related */ 123 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 124 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 125 int proposed_clock); 126 static void sdhci_cam_poll(struct cam_sim *sim); 127 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 128 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 129 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 130 #endif 131 132 /* helper routines */ 133 static int sdhci_dma_alloc(struct sdhci_slot *slot); 134 static void sdhci_dma_free(struct sdhci_slot *slot); 135 static void sdhci_dumpcaps(struct sdhci_slot *slot); 136 static void sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s); 137 static void sdhci_dumpregs(struct sdhci_slot *slot); 138 static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s); 139 static int sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS); 140 static int sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS); 141 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 142 int error); 143 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 144 __printflike(2, 3); 145 static int slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s, 146 const char * fmt, ...) __printflike(3, 4); 147 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot); 148 149 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 150 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 151 #define SDHCI_LOCK_INIT(_slot) \ 152 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 153 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 154 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 155 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 156 157 #define SDHCI_DEFAULT_MAX_FREQ 50 158 159 #define SDHCI_200_MAX_DIVIDER 256 160 #define SDHCI_300_MAX_DIVIDER 2046 161 162 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 163 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 164 165 /* 166 * Broadcom BCM577xx Controller Constants 167 */ 168 /* Maximum divider supported by the default clock source. */ 169 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 170 /* Alternative clock's base frequency. */ 171 #define BCM577XX_ALT_CLOCK_BASE 63000000 172 173 #define BCM577XX_HOST_CONTROL 0x198 174 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 175 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 176 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 177 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 178 179 static void 180 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 181 { 182 183 if (error != 0) { 184 printf("getaddr: error %d\n", error); 185 return; 186 } 187 *(bus_addr_t *)arg = segs[0].ds_addr; 188 } 189 190 static int 191 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 192 { 193 char buf[128]; 194 va_list ap; 195 int retval; 196 197 /* 198 * Make sure we print a single line all together rather than in two 199 * halves to avoid console gibberish bingo. 200 */ 201 va_start(ap, fmt); 202 retval = vsnprintf(buf, sizeof(buf), fmt, ap); 203 va_end(ap); 204 205 retval += printf("%s-slot%d: %s", 206 device_get_nameunit(slot->bus), slot->num, buf); 207 return (retval); 208 } 209 210 static int 211 slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s, 212 const char * fmt, ...) 213 { 214 va_list ap; 215 int retval; 216 217 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num); 218 219 va_start(ap, fmt); 220 retval += sbuf_vprintf(s, fmt, ap); 221 va_end(ap); 222 223 return (retval); 224 } 225 226 static void 227 sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s) 228 { 229 slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n"); 230 231 slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n", 232 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 233 slot_sprintf(slot, s, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 234 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 235 slot_sprintf(slot, s, "Argument: 0x%08x | Trn mode: 0x%08x\n", 236 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 237 slot_sprintf(slot, s, "Present: 0x%08x | Host ctl: 0x%08x\n", 238 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 239 slot_sprintf(slot, s, "Power: 0x%08x | Blk gap: 0x%08x\n", 240 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 241 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n", 242 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 243 slot_sprintf(slot, s, "Timeout: 0x%08x | Int stat: 0x%08x\n", 244 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 245 slot_sprintf(slot, s, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 246 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 247 slot_sprintf(slot, s, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 248 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 249 slot_sprintf(slot, s, "Caps: 0x%08x | Caps2: 0x%08x\n", 250 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 251 slot_sprintf(slot, s, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 252 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 253 slot_sprintf(slot, s, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 254 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 255 256 slot_sprintf(slot, s, "===========================================\n"); 257 } 258 259 static void 260 sdhci_dumpregs(struct sdhci_slot *slot) 261 { 262 struct sbuf s; 263 264 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) { 265 slot_printf(slot, "sdhci_dumpregs: Failed to allocate memory for sbuf\n"); 266 return; 267 } 268 269 sbuf_set_drain(&s, &sbuf_printf_drain, NULL); 270 sdhci_dumpregs_buf(slot, &s); 271 sbuf_finish(&s); 272 sbuf_delete(&s); 273 } 274 275 static int 276 sdhci_syctl_dumpregs(SYSCTL_HANDLER_ARGS) 277 { 278 struct sdhci_slot *slot = arg1; 279 struct sbuf s; 280 281 sbuf_new_for_sysctl(&s, NULL, 1024, req); 282 sbuf_putc(&s, '\n'); 283 sdhci_dumpregs_buf(slot, &s); 284 sbuf_finish(&s); 285 sbuf_delete(&s); 286 287 return (0); 288 } 289 290 static void 291 sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s) 292 { 293 int host_caps = slot->host.caps; 294 int caps = slot->caps; 295 296 slot_sprintf(slot, s, 297 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 298 slot->max_clk / 1000000, 299 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 300 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 301 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 302 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 303 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 304 ((caps & SDHCI_CAN_VDD_180) && 305 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 306 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 307 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 308 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 309 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 310 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 311 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 312 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 313 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 314 "removable"); 315 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 316 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 317 slot_sprintf(slot, s, "eMMC:%s%s%s%s\n", 318 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 319 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 320 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 321 ((host_caps & 322 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 323 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 324 " HS400ES" : ""); 325 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 326 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 327 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n", 328 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 329 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 330 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 331 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 332 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 333 if (slot->opt & SDHCI_TUNING_SUPPORTED) 334 slot_sprintf(slot, s, 335 "Re-tuning count %d secs, mode %d\n", 336 slot->retune_count, slot->retune_mode + 1); 337 } 338 339 static void 340 sdhci_dumpcaps(struct sdhci_slot *slot) 341 { 342 struct sbuf s; 343 344 if (sbuf_new(&s, NULL, 1024, SBUF_NOWAIT | SBUF_AUTOEXTEND) == NULL) { 345 slot_printf(slot, "sdhci_dumpcaps: Failed to allocate memory for sbuf\n"); 346 return; 347 } 348 349 sbuf_set_drain(&s, &sbuf_printf_drain, NULL); 350 sdhci_dumpcaps_buf(slot, &s); 351 sbuf_finish(&s); 352 sbuf_delete(&s); 353 } 354 355 static int 356 sdhci_syctl_dumpcaps(SYSCTL_HANDLER_ARGS) 357 { 358 struct sdhci_slot *slot = arg1; 359 struct sbuf s; 360 361 sbuf_new_for_sysctl(&s, NULL, 1024, req); 362 sbuf_putc(&s, '\n'); 363 sdhci_dumpcaps_buf(slot, &s); 364 sbuf_finish(&s); 365 sbuf_delete(&s); 366 367 return (0); 368 } 369 370 static uint32_t 371 sdhci_tuning_intmask(const struct sdhci_slot *slot) 372 { 373 uint32_t intmask; 374 375 intmask = 0; 376 if (slot->opt & SDHCI_TUNING_ENABLED) { 377 intmask |= SDHCI_INT_TUNEERR; 378 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 379 slot->retune_mode == SDHCI_RETUNE_MODE_3) 380 intmask |= SDHCI_INT_RETUNE; 381 } 382 return (intmask); 383 } 384 385 static void 386 sdhci_init(struct sdhci_slot *slot) 387 { 388 389 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL); 390 391 /* Enable interrupts. */ 392 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 393 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 394 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 395 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 396 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 397 SDHCI_INT_ACMD12ERR; 398 399 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 400 !(slot->opt & SDHCI_NON_REMOVABLE)) { 401 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 402 } 403 404 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 405 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 406 } 407 408 static void 409 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 410 { 411 uint32_t clk_base; 412 uint32_t clk_sel; 413 uint32_t res; 414 uint16_t clk; 415 uint16_t div; 416 int timeout; 417 418 if (clock == slot->clock) 419 return; 420 clock = SDHCI_SET_CLOCK(slot->bus, slot, clock); 421 slot->clock = clock; 422 423 /* Turn off the clock. */ 424 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 425 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 426 /* If no clock requested - leave it so. */ 427 if (clock == 0) 428 return; 429 430 /* Determine the clock base frequency */ 431 clk_base = slot->max_clk; 432 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 433 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 434 BCM577XX_CTRL_CLKSEL_MASK; 435 436 /* 437 * Select clock source appropriate for the requested frequency. 438 */ 439 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 440 clk_base = BCM577XX_ALT_CLOCK_BASE; 441 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 442 BCM577XX_CTRL_CLKSEL_SHIFT); 443 } else { 444 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 445 BCM577XX_CTRL_CLKSEL_SHIFT); 446 } 447 448 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 449 } 450 451 /* Recalculate timeout clock frequency based on the new sd clock. */ 452 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 453 slot->timeout_clk = slot->clock / 1000; 454 455 if (slot->version < SDHCI_SPEC_300) { 456 /* Looking for highest freq <= clock. */ 457 res = clk_base; 458 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 459 if (res <= clock) 460 break; 461 res >>= 1; 462 } 463 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 464 div >>= 1; 465 } else { 466 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 467 if (clock >= clk_base) 468 div = 0; 469 else { 470 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 471 if ((clk_base / div) <= clock) 472 break; 473 } 474 } 475 div >>= 1; 476 } 477 478 if (bootverbose || sdhci_debug) 479 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 480 div, clock, clk_base); 481 482 /* Now we have got divider, set it. */ 483 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 484 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 485 << SDHCI_DIVIDER_HI_SHIFT; 486 487 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 488 /* Enable clock. */ 489 clk |= SDHCI_CLOCK_INT_EN; 490 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 491 /* Wait up to 10 ms until it stabilize. */ 492 timeout = 10; 493 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 494 & SDHCI_CLOCK_INT_STABLE)) { 495 if (timeout == 0) { 496 slot_printf(slot, 497 "Internal clock never stabilised.\n"); 498 sdhci_dumpregs(slot); 499 return; 500 } 501 timeout--; 502 DELAY(1000); 503 } 504 /* Pass clock signal to the bus. */ 505 clk |= SDHCI_CLOCK_CARD_EN; 506 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 507 } 508 509 static void 510 sdhci_set_power(struct sdhci_slot *slot, u_char power) 511 { 512 int i; 513 uint8_t pwr; 514 515 if (slot->power == power) 516 return; 517 518 slot->power = power; 519 520 /* Turn off the power. */ 521 pwr = 0; 522 WR1(slot, SDHCI_POWER_CONTROL, pwr); 523 /* If power down requested - leave it so. */ 524 if (power == 0) 525 return; 526 /* Set voltage. */ 527 switch (1 << power) { 528 case MMC_OCR_LOW_VOLTAGE: 529 pwr |= SDHCI_POWER_180; 530 break; 531 case MMC_OCR_290_300: 532 case MMC_OCR_300_310: 533 pwr |= SDHCI_POWER_300; 534 break; 535 case MMC_OCR_320_330: 536 case MMC_OCR_330_340: 537 pwr |= SDHCI_POWER_330; 538 break; 539 } 540 WR1(slot, SDHCI_POWER_CONTROL, pwr); 541 /* 542 * Turn on VDD1 power. Note that at least some Intel controllers can 543 * fail to enable bus power on the first try after transiting from D3 544 * to D0, so we give them up to 2 ms. 545 */ 546 pwr |= SDHCI_POWER_ON; 547 for (i = 0; i < 20; i++) { 548 WR1(slot, SDHCI_POWER_CONTROL, pwr); 549 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 550 break; 551 DELAY(100); 552 } 553 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 554 slot_printf(slot, "Bus power failed to enable\n"); 555 556 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 557 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 558 DELAY(10); 559 WR1(slot, SDHCI_POWER_CONTROL, pwr); 560 DELAY(300); 561 } 562 } 563 564 static void 565 sdhci_read_block_pio(struct sdhci_slot *slot) 566 { 567 uint32_t data; 568 char *buffer; 569 size_t left; 570 571 buffer = slot->curcmd->data->data; 572 buffer += slot->offset; 573 /* Transfer one block at a time. */ 574 #ifdef MMCCAM 575 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) 576 left = min(slot->curcmd->data->block_size, 577 slot->curcmd->data->len - slot->offset); 578 else 579 #endif 580 left = min(512, slot->curcmd->data->len - slot->offset); 581 slot->offset += left; 582 583 /* If we are too fast, broken controllers return zeroes. */ 584 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 585 DELAY(10); 586 /* Handle unaligned and aligned buffer cases. */ 587 if ((intptr_t)buffer & 3) { 588 while (left > 3) { 589 data = RD4(slot, SDHCI_BUFFER); 590 buffer[0] = data; 591 buffer[1] = (data >> 8); 592 buffer[2] = (data >> 16); 593 buffer[3] = (data >> 24); 594 buffer += 4; 595 left -= 4; 596 } 597 } else { 598 RD_MULTI_4(slot, SDHCI_BUFFER, 599 (uint32_t *)buffer, left >> 2); 600 left &= 3; 601 } 602 /* Handle uneven size case. */ 603 if (left > 0) { 604 data = RD4(slot, SDHCI_BUFFER); 605 while (left > 0) { 606 *(buffer++) = data; 607 data >>= 8; 608 left--; 609 } 610 } 611 } 612 613 static void 614 sdhci_write_block_pio(struct sdhci_slot *slot) 615 { 616 uint32_t data = 0; 617 char *buffer; 618 size_t left; 619 620 buffer = slot->curcmd->data->data; 621 buffer += slot->offset; 622 /* Transfer one block at a time. */ 623 #ifdef MMCCAM 624 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) { 625 left = min(slot->curcmd->data->block_size, 626 slot->curcmd->data->len - slot->offset); 627 } else 628 #endif 629 left = min(512, slot->curcmd->data->len - slot->offset); 630 slot->offset += left; 631 632 /* Handle unaligned and aligned buffer cases. */ 633 if ((intptr_t)buffer & 3) { 634 while (left > 3) { 635 data = buffer[0] + 636 (buffer[1] << 8) + 637 (buffer[2] << 16) + 638 (buffer[3] << 24); 639 left -= 4; 640 buffer += 4; 641 WR4(slot, SDHCI_BUFFER, data); 642 } 643 } else { 644 WR_MULTI_4(slot, SDHCI_BUFFER, 645 (uint32_t *)buffer, left >> 2); 646 left &= 3; 647 } 648 /* Handle uneven size case. */ 649 if (left > 0) { 650 while (left > 0) { 651 data <<= 8; 652 data += *(buffer++); 653 left--; 654 } 655 WR4(slot, SDHCI_BUFFER, data); 656 } 657 } 658 659 static void 660 sdhci_transfer_pio(struct sdhci_slot *slot) 661 { 662 663 /* Read as many blocks as possible. */ 664 if (slot->curcmd->data->flags & MMC_DATA_READ) { 665 while (RD4(slot, SDHCI_PRESENT_STATE) & 666 SDHCI_DATA_AVAILABLE) { 667 sdhci_read_block_pio(slot); 668 if (slot->offset >= slot->curcmd->data->len) 669 break; 670 } 671 } else { 672 while (RD4(slot, SDHCI_PRESENT_STATE) & 673 SDHCI_SPACE_AVAILABLE) { 674 sdhci_write_block_pio(slot); 675 if (slot->offset >= slot->curcmd->data->len) 676 break; 677 } 678 } 679 } 680 681 static void 682 sdhci_card_task(void *arg, int pending __unused) 683 { 684 struct sdhci_slot *slot = arg; 685 #ifndef MMCCAM 686 device_t d; 687 #endif 688 689 SDHCI_LOCK(slot); 690 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 691 #ifdef MMCCAM 692 if (slot->card_present == 0) { 693 #else 694 if (slot->dev == NULL) { 695 #endif 696 /* If card is present - attach mmc bus. */ 697 if (bootverbose || sdhci_debug) 698 slot_printf(slot, "Card inserted\n"); 699 #ifdef MMCCAM 700 slot->card_present = 1; 701 mmccam_start_discovery(slot->sim); 702 SDHCI_UNLOCK(slot); 703 #else 704 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 705 SDHCI_UNLOCK(slot); 706 if (d) { 707 device_set_ivars(d, slot); 708 (void)device_probe_and_attach(d); 709 } 710 #endif 711 } else 712 SDHCI_UNLOCK(slot); 713 } else { 714 #ifdef MMCCAM 715 if (slot->card_present == 1) { 716 #else 717 if (slot->dev != NULL) { 718 d = slot->dev; 719 #endif 720 /* If no card present - detach mmc bus. */ 721 if (bootverbose || sdhci_debug) 722 slot_printf(slot, "Card removed\n"); 723 slot->dev = NULL; 724 #ifdef MMCCAM 725 slot->card_present = 0; 726 mmccam_start_discovery(slot->sim); 727 SDHCI_UNLOCK(slot); 728 #else 729 slot->intmask &= ~sdhci_tuning_intmask(slot); 730 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 731 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 732 slot->opt &= ~SDHCI_TUNING_ENABLED; 733 SDHCI_UNLOCK(slot); 734 callout_drain(&slot->retune_callout); 735 device_delete_child(slot->bus, d); 736 #endif 737 } else 738 SDHCI_UNLOCK(slot); 739 } 740 } 741 742 static void 743 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 744 { 745 bool was_present; 746 747 /* 748 * If there was no card and now there is one, schedule the task to 749 * create the child device after a short delay. The delay is to 750 * debounce the card insert (sometimes the card detect pin stabilizes 751 * before the other pins have made good contact). 752 * 753 * If there was a card present and now it's gone, immediately schedule 754 * the task to delete the child device. No debouncing -- gone is gone, 755 * because once power is removed, a full card re-init is needed, and 756 * that happens by deleting and recreating the child device. 757 */ 758 #ifdef MMCCAM 759 was_present = slot->card_present; 760 #else 761 was_present = slot->dev != NULL; 762 #endif 763 if (!was_present && is_present) { 764 taskqueue_enqueue_timeout(taskqueue_swi_giant, 765 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 766 } else if (was_present && !is_present) { 767 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 768 } 769 } 770 771 void 772 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 773 { 774 775 SDHCI_LOCK(slot); 776 sdhci_handle_card_present_locked(slot, is_present); 777 SDHCI_UNLOCK(slot); 778 } 779 780 static void 781 sdhci_card_poll(void *arg) 782 { 783 struct sdhci_slot *slot = arg; 784 785 sdhci_handle_card_present(slot, 786 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 787 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 788 sdhci_card_poll, slot); 789 } 790 791 static int 792 sdhci_dma_alloc(struct sdhci_slot *slot) 793 { 794 int err; 795 796 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) { 797 if (maxphys <= 1024 * 4) 798 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 799 else if (maxphys <= 1024 * 8) 800 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K; 801 else if (maxphys <= 1024 * 16) 802 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K; 803 else if (maxphys <= 1024 * 32) 804 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K; 805 else if (maxphys <= 1024 * 64) 806 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K; 807 else if (maxphys <= 1024 * 128) 808 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K; 809 else if (maxphys <= 1024 * 256) 810 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K; 811 else 812 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K; 813 } 814 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary); 815 816 /* 817 * Allocate the DMA tag for an SDMA bounce buffer. 818 * Note that the SDHCI specification doesn't state any alignment 819 * constraint for the SDMA system address. However, controllers 820 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when 821 * forming the actual address of data, requiring the SDMA buffer to 822 * be aligned to the SDMA boundary. 823 */ 824 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz, 825 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 826 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW, 827 NULL, NULL, &slot->dmatag); 828 if (err != 0) { 829 slot_printf(slot, "Can't create DMA tag for SDMA\n"); 830 return (err); 831 } 832 /* Allocate DMA memory for the SDMA bounce buffer. */ 833 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 834 BUS_DMA_NOWAIT, &slot->dmamap); 835 if (err != 0) { 836 slot_printf(slot, "Can't alloc DMA memory for SDMA\n"); 837 bus_dma_tag_destroy(slot->dmatag); 838 return (err); 839 } 840 /* Map the memory of the SDMA bounce buffer. */ 841 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 842 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr, 843 &slot->paddr, 0); 844 if (err != 0 || slot->paddr == 0) { 845 slot_printf(slot, "Can't load DMA memory for SDMA\n"); 846 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 847 bus_dma_tag_destroy(slot->dmatag); 848 if (err) 849 return (err); 850 else 851 return (EFAULT); 852 } 853 854 return (0); 855 } 856 857 static void 858 sdhci_dma_free(struct sdhci_slot *slot) 859 { 860 861 bus_dmamap_unload(slot->dmatag, slot->dmamap); 862 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 863 bus_dma_tag_destroy(slot->dmatag); 864 } 865 866 int 867 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 868 { 869 kobjop_desc_t kobj_desc; 870 kobj_method_t *kobj_method; 871 uint32_t caps, caps2, freq, host_caps; 872 int err; 873 char node_name[8]; 874 struct sysctl_oid *node_oid; 875 876 SDHCI_LOCK_INIT(slot); 877 878 slot->num = num; 879 slot->bus = dev; 880 881 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 882 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 883 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 884 caps = slot->caps; 885 caps2 = slot->caps2; 886 } else { 887 caps = RD4(slot, SDHCI_CAPABILITIES); 888 if (slot->version >= SDHCI_SPEC_300) 889 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 890 else 891 caps2 = 0; 892 } 893 if (slot->version >= SDHCI_SPEC_300) { 894 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 895 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 896 slot_printf(slot, 897 "Driver doesn't support shared bus slots\n"); 898 SDHCI_LOCK_DESTROY(slot); 899 return (ENXIO); 900 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 901 SDHCI_SLOTTYPE_EMBEDDED) { 902 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 903 } 904 } 905 /* Calculate base clock frequency. */ 906 if (slot->version >= SDHCI_SPEC_300) 907 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 908 SDHCI_CLOCK_BASE_SHIFT; 909 else 910 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 911 SDHCI_CLOCK_BASE_SHIFT; 912 if (freq != 0) 913 slot->max_clk = freq * 1000000; 914 /* 915 * If the frequency wasn't in the capabilities and the hardware driver 916 * hasn't already set max_clk we're probably not going to work right 917 * with an assumption, so complain about it. 918 */ 919 if (slot->max_clk == 0) { 920 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 921 slot_printf(slot, "Hardware doesn't specify base clock " 922 "frequency, using %dMHz as default.\n", 923 SDHCI_DEFAULT_MAX_FREQ); 924 } 925 /* Calculate/set timeout clock frequency. */ 926 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 927 slot->timeout_clk = slot->max_clk / 1000; 928 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 929 slot->timeout_clk = 1000; 930 } else { 931 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 932 SDHCI_TIMEOUT_CLK_SHIFT; 933 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 934 slot->timeout_clk *= 1000; 935 } 936 /* 937 * If the frequency wasn't in the capabilities and the hardware driver 938 * hasn't already set timeout_clk we'll probably work okay using the 939 * max timeout, but still mention it. 940 */ 941 if (slot->timeout_clk == 0) { 942 slot_printf(slot, "Hardware doesn't specify timeout clock " 943 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 944 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 945 } 946 947 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 948 slot->host.f_max = slot->max_clk; 949 slot->host.host_ocr = 0; 950 if (caps & SDHCI_CAN_VDD_330) 951 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 952 if (caps & SDHCI_CAN_VDD_300) 953 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 954 /* 955 * 1.8V VDD is not supposed to be used for removable cards. Hardware 956 * prior to v3.0 had no way to indicate embedded slots, but did 957 * sometimes support 1.8v for non-removable devices. 958 */ 959 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 || 960 (slot->opt & SDHCI_SLOT_EMBEDDED))) 961 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 962 if (slot->host.host_ocr == 0) { 963 slot_printf(slot, "Hardware doesn't report any " 964 "support voltages.\n"); 965 } 966 967 host_caps = slot->host.caps; 968 host_caps |= MMC_CAP_4_BIT_DATA; 969 if (caps & SDHCI_CAN_DO_8BITBUS) 970 host_caps |= MMC_CAP_8_BIT_DATA; 971 if (caps & SDHCI_CAN_DO_HISPD) 972 host_caps |= MMC_CAP_HSPEED; 973 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 974 host_caps |= MMC_CAP_BOOT_NOACC; 975 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 976 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 977 978 /* Determine supported UHS-I and eMMC modes. */ 979 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 980 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 981 if (caps2 & SDHCI_CAN_SDR104) { 982 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 983 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 984 host_caps |= MMC_CAP_MMC_HS200; 985 } else if (caps2 & SDHCI_CAN_SDR50) 986 host_caps |= MMC_CAP_UHS_SDR50; 987 if (caps2 & SDHCI_CAN_DDR50 && 988 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 989 host_caps |= MMC_CAP_UHS_DDR50; 990 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 991 host_caps |= MMC_CAP_MMC_DDR52; 992 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 993 caps2 & SDHCI_CAN_MMC_HS400) 994 host_caps |= MMC_CAP_MMC_HS400; 995 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 && 996 caps2 & SDHCI_CAN_SDR104) 997 host_caps |= MMC_CAP_MMC_HS400; 998 999 /* 1000 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 1001 * default NULL implementation. 1002 */ 1003 kobj_desc = &sdhci_set_uhs_timing_desc; 1004 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1005 kobj_desc); 1006 if (kobj_method == &kobj_desc->deflt) 1007 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1008 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 1009 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 1010 1011 #define SDHCI_CAP_MODES_TUNING(caps2) \ 1012 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 1013 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 1014 MMC_CAP_MMC_HS400) 1015 1016 /* 1017 * Disable UHS-I and eMMC modes that require (re-)tuning if either 1018 * the tune or re-tune method is the default NULL implementation. 1019 */ 1020 kobj_desc = &mmcbr_tune_desc; 1021 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1022 kobj_desc); 1023 if (kobj_method == &kobj_desc->deflt) 1024 goto no_tuning; 1025 kobj_desc = &mmcbr_retune_desc; 1026 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1027 kobj_desc); 1028 if (kobj_method == &kobj_desc->deflt) { 1029 no_tuning: 1030 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 1031 } 1032 1033 /* Allocate tuning structures and determine tuning parameters. */ 1034 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 1035 slot->opt |= SDHCI_TUNING_SUPPORTED; 1036 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 1037 M_WAITOK); 1038 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 1039 M_WAITOK); 1040 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 1041 M_WAITOK); 1042 if (caps2 & SDHCI_TUNE_SDR50) 1043 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 1044 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 1045 SDHCI_RETUNE_MODES_SHIFT; 1046 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 1047 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 1048 SDHCI_RETUNE_CNT_SHIFT; 1049 if (slot->retune_count > 0xb) { 1050 slot_printf(slot, "Unknown re-tuning count " 1051 "%x, using 1 sec\n", slot->retune_count); 1052 slot->retune_count = 1; 1053 } else if (slot->retune_count != 0) 1054 slot->retune_count = 1055 1 << (slot->retune_count - 1); 1056 } 1057 } 1058 1059 #undef SDHCI_CAP_MODES_TUNING 1060 1061 /* Determine supported VCCQ signaling levels. */ 1062 host_caps |= MMC_CAP_SIGNALING_330; 1063 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1064 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 1065 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 1066 MMC_CAP_MMC_HS400_180)) 1067 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 1068 1069 /* 1070 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 1071 * default NULL implementation. Disable 1.2 V support if it's the 1072 * generic SDHCI implementation. 1073 */ 1074 kobj_desc = &mmcbr_switch_vccq_desc; 1075 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1076 kobj_desc); 1077 if (kobj_method == &kobj_desc->deflt) 1078 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 1079 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 1080 host_caps &= ~MMC_CAP_SIGNALING_120; 1081 1082 /* Determine supported driver types (type B is always mandatory). */ 1083 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 1084 host_caps |= MMC_CAP_DRIVER_TYPE_A; 1085 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 1086 host_caps |= MMC_CAP_DRIVER_TYPE_C; 1087 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 1088 host_caps |= MMC_CAP_DRIVER_TYPE_D; 1089 slot->host.caps = host_caps; 1090 1091 /* Decide if we have usable DMA. */ 1092 if (caps & SDHCI_CAN_DO_DMA) 1093 slot->opt |= SDHCI_HAVE_DMA; 1094 1095 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 1096 slot->opt &= ~SDHCI_HAVE_DMA; 1097 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 1098 slot->opt |= SDHCI_HAVE_DMA; 1099 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 1100 slot->opt |= SDHCI_NON_REMOVABLE; 1101 1102 /* 1103 * Use platform-provided transfer backend 1104 * with PIO as a fallback mechanism 1105 */ 1106 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 1107 slot->opt &= ~SDHCI_HAVE_DMA; 1108 1109 if (slot->opt & SDHCI_HAVE_DMA) { 1110 err = sdhci_dma_alloc(slot); 1111 if (err != 0) { 1112 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1113 free(slot->tune_req, M_DEVBUF); 1114 free(slot->tune_cmd, M_DEVBUF); 1115 free(slot->tune_data, M_DEVBUF); 1116 } 1117 SDHCI_LOCK_DESTROY(slot); 1118 return (err); 1119 } 1120 } 1121 1122 if (bootverbose || sdhci_debug) { 1123 sdhci_dumpcaps(slot); 1124 sdhci_dumpregs(slot); 1125 } 1126 1127 slot->timeout = 10; 1128 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1129 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1130 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0, 1131 "Maximum timeout for SDHCI transfers (in secs)"); 1132 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1133 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1134 sdhci_card_task, slot); 1135 callout_init(&slot->card_poll_callout, 1); 1136 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1137 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1138 1139 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1140 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1141 callout_reset(&slot->card_poll_callout, 1142 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1143 } 1144 1145 sdhci_init(slot); 1146 1147 snprintf(node_name, sizeof(node_name), "slot%d", slot->num); 1148 1149 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev), 1150 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1151 OID_AUTO, node_name, CTLFLAG_RW, 0, "slot specific node"); 1152 1153 node_oid = SYSCTL_ADD_NODE(device_get_sysctl_ctx(dev), 1154 SYSCTL_CHILDREN(node_oid), OID_AUTO, "debug", CTLFLAG_RW, 0, 1155 "Debugging node"); 1156 1157 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid), 1158 OID_AUTO, "dumpregs", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1159 slot, 0, &sdhci_syctl_dumpregs, 1160 "A", "Dump SDHCI registers"); 1161 1162 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(node_oid), 1163 OID_AUTO, "dumpcaps", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, 1164 slot, 0, &sdhci_syctl_dumpcaps, 1165 "A", "Dump SDHCI capabilites"); 1166 1167 return (0); 1168 } 1169 1170 #ifndef MMCCAM 1171 void 1172 sdhci_start_slot(struct sdhci_slot *slot) 1173 { 1174 1175 sdhci_card_task(slot, 0); 1176 } 1177 #endif 1178 1179 int 1180 sdhci_cleanup_slot(struct sdhci_slot *slot) 1181 { 1182 device_t d; 1183 1184 callout_drain(&slot->timeout_callout); 1185 callout_drain(&slot->card_poll_callout); 1186 callout_drain(&slot->retune_callout); 1187 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1188 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1189 1190 SDHCI_LOCK(slot); 1191 d = slot->dev; 1192 slot->dev = NULL; 1193 SDHCI_UNLOCK(slot); 1194 if (d != NULL) 1195 device_delete_child(slot->bus, d); 1196 1197 SDHCI_LOCK(slot); 1198 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL); 1199 SDHCI_UNLOCK(slot); 1200 if (slot->opt & SDHCI_HAVE_DMA) 1201 sdhci_dma_free(slot); 1202 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1203 free(slot->tune_req, M_DEVBUF); 1204 free(slot->tune_cmd, M_DEVBUF); 1205 free(slot->tune_data, M_DEVBUF); 1206 } 1207 1208 SDHCI_LOCK_DESTROY(slot); 1209 1210 return (0); 1211 } 1212 1213 int 1214 sdhci_generic_suspend(struct sdhci_slot *slot) 1215 { 1216 1217 /* 1218 * We expect the MMC layer to issue initial tuning after resume. 1219 * Otherwise, we'd need to indicate re-tuning including circuit reset 1220 * being required at least for re-tuning modes 1 and 2 ourselves. 1221 */ 1222 callout_drain(&slot->retune_callout); 1223 SDHCI_LOCK(slot); 1224 slot->opt &= ~SDHCI_TUNING_ENABLED; 1225 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL); 1226 SDHCI_UNLOCK(slot); 1227 1228 return (0); 1229 } 1230 1231 int 1232 sdhci_generic_resume(struct sdhci_slot *slot) 1233 { 1234 1235 SDHCI_LOCK(slot); 1236 sdhci_init(slot); 1237 SDHCI_UNLOCK(slot); 1238 1239 return (0); 1240 } 1241 1242 void 1243 sdhci_generic_reset(device_t brdev __unused, struct sdhci_slot *slot, 1244 uint8_t mask) 1245 { 1246 int timeout; 1247 uint32_t clock; 1248 1249 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 1250 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 1251 return; 1252 } 1253 1254 /* Some controllers need this kick or reset won't work. */ 1255 if ((mask & SDHCI_RESET_ALL) == 0 && 1256 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 1257 /* This is to force an update */ 1258 clock = slot->clock; 1259 slot->clock = 0; 1260 sdhci_set_clock(slot, clock); 1261 } 1262 1263 if (mask & SDHCI_RESET_ALL) { 1264 slot->clock = 0; 1265 slot->power = 0; 1266 } 1267 1268 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 1269 1270 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 1271 /* 1272 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 1273 * specification. The reset bit has internal propagation delay, 1274 * so a fast read after write returns 0 even if reset process is 1275 * in progress. The workaround is to poll for 1 before polling 1276 * for 0. In the worst case, if we miss seeing it asserted the 1277 * time we spent waiting is enough to ensure the reset finishes. 1278 */ 1279 timeout = 10000; 1280 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 1281 if (timeout <= 0) 1282 break; 1283 timeout--; 1284 DELAY(1); 1285 } 1286 } 1287 1288 /* Wait max 100 ms */ 1289 timeout = 10000; 1290 /* Controller clears the bits when it's done */ 1291 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 1292 if (timeout <= 0) { 1293 slot_printf(slot, "Reset 0x%x never completed.\n", 1294 mask); 1295 sdhci_dumpregs(slot); 1296 return; 1297 } 1298 timeout--; 1299 DELAY(10); 1300 } 1301 } 1302 1303 uint32_t 1304 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1305 { 1306 1307 if (slot->version >= SDHCI_SPEC_300) 1308 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1309 else 1310 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1311 } 1312 1313 bool 1314 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1315 { 1316 1317 if (slot->opt & SDHCI_NON_REMOVABLE) 1318 return true; 1319 1320 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1321 } 1322 1323 void 1324 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1325 { 1326 const struct mmc_ios *ios; 1327 uint16_t hostctrl2; 1328 1329 if (slot->version < SDHCI_SPEC_300) 1330 return; 1331 1332 SDHCI_ASSERT_LOCKED(slot); 1333 ios = &slot->host.ios; 1334 sdhci_set_clock(slot, 0); 1335 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1336 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1337 if (ios->clock > SD_SDR50_MAX) { 1338 if (ios->timing == bus_timing_mmc_hs400 || 1339 ios->timing == bus_timing_mmc_hs400es) 1340 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1341 else 1342 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1343 } 1344 else if (ios->clock > SD_SDR25_MAX) 1345 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1346 else if (ios->clock > SD_SDR12_MAX) { 1347 if (ios->timing == bus_timing_uhs_ddr50 || 1348 ios->timing == bus_timing_mmc_ddr52) 1349 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1350 else 1351 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1352 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1353 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1354 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1355 sdhci_set_clock(slot, ios->clock); 1356 } 1357 1358 int 1359 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1360 { 1361 struct sdhci_slot *slot = device_get_ivars(reqdev); 1362 struct mmc_ios *ios = &slot->host.ios; 1363 1364 SDHCI_LOCK(slot); 1365 /* Do full reset on bus power down to clear from any state. */ 1366 if (ios->power_mode == power_off) { 1367 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1368 sdhci_init(slot); 1369 } 1370 /* Configure the bus. */ 1371 sdhci_set_clock(slot, ios->clock); 1372 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1373 if (ios->bus_width == bus_width_8) { 1374 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1375 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1376 } else if (ios->bus_width == bus_width_4) { 1377 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1378 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1379 } else if (ios->bus_width == bus_width_1) { 1380 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1381 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1382 } else { 1383 panic("Invalid bus width: %d", ios->bus_width); 1384 } 1385 if (ios->clock > SD_SDR12_MAX && 1386 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1387 slot->hostctrl |= SDHCI_CTRL_HISPD; 1388 else 1389 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1390 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1391 SDHCI_SET_UHS_TIMING(brdev, slot); 1392 /* Some controllers like reset after bus changes. */ 1393 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1394 SDHCI_RESET(slot->bus, slot, 1395 SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1396 1397 SDHCI_UNLOCK(slot); 1398 return (0); 1399 } 1400 1401 int 1402 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1403 { 1404 struct sdhci_slot *slot = device_get_ivars(reqdev); 1405 enum mmc_vccq vccq; 1406 int err; 1407 uint16_t hostctrl2; 1408 1409 if (slot->version < SDHCI_SPEC_300) 1410 return (0); 1411 1412 err = 0; 1413 vccq = slot->host.ios.vccq; 1414 SDHCI_LOCK(slot); 1415 sdhci_set_clock(slot, 0); 1416 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1417 switch (vccq) { 1418 case vccq_330: 1419 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1420 goto done; 1421 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1422 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1423 DELAY(5000); 1424 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1425 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1426 goto done; 1427 err = EAGAIN; 1428 break; 1429 case vccq_180: 1430 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1431 err = EINVAL; 1432 goto done; 1433 } 1434 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1435 goto done; 1436 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1437 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1438 DELAY(5000); 1439 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1440 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1441 goto done; 1442 err = EAGAIN; 1443 break; 1444 default: 1445 slot_printf(slot, 1446 "Attempt to set unsupported signaling voltage\n"); 1447 err = EINVAL; 1448 break; 1449 } 1450 done: 1451 sdhci_set_clock(slot, slot->host.ios.clock); 1452 SDHCI_UNLOCK(slot); 1453 return (err); 1454 } 1455 1456 int 1457 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1458 { 1459 struct sdhci_slot *slot = device_get_ivars(reqdev); 1460 const struct mmc_ios *ios = &slot->host.ios; 1461 struct mmc_command *tune_cmd; 1462 struct mmc_data *tune_data; 1463 uint32_t opcode; 1464 int err; 1465 1466 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1467 return (0); 1468 1469 slot->retune_ticks = slot->retune_count * hz; 1470 opcode = MMC_SEND_TUNING_BLOCK; 1471 SDHCI_LOCK(slot); 1472 switch (ios->timing) { 1473 case bus_timing_mmc_hs400: 1474 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1475 SDHCI_UNLOCK(slot); 1476 return (EINVAL); 1477 case bus_timing_mmc_hs200: 1478 /* 1479 * In HS400 mode, controllers use the data strobe line to 1480 * latch data from the devices so periodic re-tuning isn't 1481 * expected to be required. 1482 */ 1483 if (hs400) 1484 slot->retune_ticks = 0; 1485 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1486 break; 1487 case bus_timing_uhs_ddr50: 1488 case bus_timing_uhs_sdr104: 1489 break; 1490 case bus_timing_uhs_sdr50: 1491 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1492 break; 1493 SDHCI_UNLOCK(slot); 1494 return (0); 1495 default: 1496 slot_printf(slot, "Tuning requested but not required.\n"); 1497 SDHCI_UNLOCK(slot); 1498 return (EINVAL); 1499 } 1500 1501 tune_cmd = slot->tune_cmd; 1502 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1503 tune_cmd->opcode = opcode; 1504 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1505 tune_data = tune_cmd->data = slot->tune_data; 1506 memset(tune_data, 0, sizeof(*tune_data)); 1507 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1508 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1509 MMC_TUNING_LEN; 1510 tune_data->flags = MMC_DATA_READ; 1511 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1512 1513 slot->opt &= ~SDHCI_TUNING_ENABLED; 1514 err = sdhci_exec_tuning(slot, true); 1515 if (err == 0) { 1516 slot->opt |= SDHCI_TUNING_ENABLED; 1517 slot->intmask |= sdhci_tuning_intmask(slot); 1518 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1519 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1520 if (slot->retune_ticks) { 1521 callout_reset(&slot->retune_callout, slot->retune_ticks, 1522 sdhci_retune, slot); 1523 } 1524 } 1525 SDHCI_UNLOCK(slot); 1526 return (err); 1527 } 1528 1529 int 1530 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1531 { 1532 struct sdhci_slot *slot = device_get_ivars(reqdev); 1533 int err; 1534 1535 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1536 return (0); 1537 1538 /* HS400 must be tuned in HS200 mode. */ 1539 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1540 return (EINVAL); 1541 1542 SDHCI_LOCK(slot); 1543 err = sdhci_exec_tuning(slot, reset); 1544 /* 1545 * There are two ways sdhci_exec_tuning() can fail: 1546 * EBUSY should not actually happen when requests are only issued 1547 * with the host properly acquired, and 1548 * EIO re-tuning failed (but it did work initially). 1549 * 1550 * In both cases, we should retry at later point if periodic re-tuning 1551 * is enabled. Note that due to slot->retune_req not being cleared in 1552 * these failure cases, the MMC layer should trigger another attempt at 1553 * re-tuning with the next request anyway, though. 1554 */ 1555 if (slot->retune_ticks) { 1556 callout_reset(&slot->retune_callout, slot->retune_ticks, 1557 sdhci_retune, slot); 1558 } 1559 SDHCI_UNLOCK(slot); 1560 return (err); 1561 } 1562 1563 static int 1564 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1565 { 1566 struct mmc_request *tune_req; 1567 struct mmc_command *tune_cmd; 1568 int i; 1569 uint32_t intmask; 1570 uint16_t hostctrl2; 1571 u_char opt; 1572 1573 SDHCI_ASSERT_LOCKED(slot); 1574 if (slot->req != NULL) 1575 return (EBUSY); 1576 1577 /* Tuning doesn't work with DMA enabled. */ 1578 opt = slot->opt; 1579 slot->opt = opt & ~SDHCI_HAVE_DMA; 1580 1581 /* 1582 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1583 * kind of interrupt we receive in response to a tuning request. 1584 */ 1585 intmask = slot->intmask; 1586 slot->intmask = SDHCI_INT_DATA_AVAIL; 1587 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL); 1588 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1589 1590 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1591 if (reset) 1592 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1593 else 1594 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1595 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1596 1597 tune_req = slot->tune_req; 1598 tune_cmd = slot->tune_cmd; 1599 for (i = 0; i < MMC_TUNING_MAX; i++) { 1600 memset(tune_req, 0, sizeof(*tune_req)); 1601 tune_req->cmd = tune_cmd; 1602 tune_req->done = sdhci_req_wakeup; 1603 tune_req->done_data = slot; 1604 slot->req = tune_req; 1605 slot->flags = 0; 1606 sdhci_start(slot); 1607 while (!(tune_req->flags & MMC_REQ_DONE)) 1608 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1609 if (!(tune_req->flags & MMC_TUNE_DONE)) 1610 break; 1611 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1612 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1613 break; 1614 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1615 DELAY(1000); 1616 } 1617 1618 /* 1619 * Restore DMA usage and interrupts. 1620 * Note that the interrupt aggregation code might have cleared 1621 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask 1622 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE 1623 * doesn't lose these. 1624 */ 1625 slot->opt = opt; 1626 slot->intmask = intmask; 1627 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END | 1628 SDHCI_INT_RESPONSE); 1629 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1630 1631 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1632 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1633 slot->retune_req = 0; 1634 return (0); 1635 } 1636 1637 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1638 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1639 SDHCI_CTRL2_SAMPLING_CLOCK)); 1640 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1641 return (EIO); 1642 } 1643 1644 static void 1645 sdhci_retune(void *arg) 1646 { 1647 struct sdhci_slot *slot = arg; 1648 1649 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1650 } 1651 1652 #ifdef MMCCAM 1653 static void 1654 sdhci_req_done(struct sdhci_slot *slot) 1655 { 1656 union ccb *ccb; 1657 1658 if (__predict_false(sdhci_debug > 1)) 1659 slot_printf(slot, "%s\n", __func__); 1660 if (slot->ccb != NULL && slot->curcmd != NULL) { 1661 callout_stop(&slot->timeout_callout); 1662 ccb = slot->ccb; 1663 slot->ccb = NULL; 1664 slot->curcmd = NULL; 1665 1666 /* Tell CAM the request is finished */ 1667 struct ccb_mmcio *mmcio; 1668 mmcio = &ccb->mmcio; 1669 1670 ccb->ccb_h.status = 1671 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1672 xpt_done(ccb); 1673 } 1674 } 1675 #else 1676 static void 1677 sdhci_req_done(struct sdhci_slot *slot) 1678 { 1679 struct mmc_request *req; 1680 1681 if (slot->req != NULL && slot->curcmd != NULL) { 1682 callout_stop(&slot->timeout_callout); 1683 req = slot->req; 1684 slot->req = NULL; 1685 slot->curcmd = NULL; 1686 req->done(req); 1687 } 1688 } 1689 #endif 1690 1691 static void 1692 sdhci_req_wakeup(struct mmc_request *req) 1693 { 1694 1695 req->flags |= MMC_REQ_DONE; 1696 wakeup(req); 1697 } 1698 1699 static void 1700 sdhci_timeout(void *arg) 1701 { 1702 struct sdhci_slot *slot = arg; 1703 1704 if (slot->curcmd != NULL) { 1705 slot_printf(slot, "Controller timeout\n"); 1706 sdhci_dumpregs(slot); 1707 SDHCI_RESET(slot->bus, slot, 1708 SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1709 slot->curcmd->error = MMC_ERR_TIMEOUT; 1710 sdhci_req_done(slot); 1711 } else { 1712 slot_printf(slot, "Spurious timeout - no active command\n"); 1713 } 1714 } 1715 1716 static void 1717 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data) 1718 { 1719 uint16_t mode; 1720 1721 if (data == NULL) 1722 return; 1723 1724 mode = SDHCI_TRNS_BLK_CNT_EN; 1725 if (data->len > 512 || data->block_count > 1) { 1726 mode |= SDHCI_TRNS_MULTI; 1727 if (data->block_count == 0 && __predict_true( 1728 #ifdef MMCCAM 1729 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION && 1730 #else 1731 slot->req->stop != NULL && 1732 #endif 1733 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))) 1734 mode |= SDHCI_TRNS_ACMD12; 1735 } 1736 if (data->flags & MMC_DATA_READ) 1737 mode |= SDHCI_TRNS_READ; 1738 if (slot->flags & SDHCI_USE_DMA) 1739 mode |= SDHCI_TRNS_DMA; 1740 1741 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1742 } 1743 1744 static void 1745 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1746 { 1747 int flags, timeout; 1748 uint32_t mask; 1749 1750 slot->curcmd = cmd; 1751 slot->cmd_done = 0; 1752 1753 cmd->error = MMC_ERR_NONE; 1754 1755 /* This flags combination is not supported by controller. */ 1756 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1757 slot_printf(slot, "Unsupported response type!\n"); 1758 cmd->error = MMC_ERR_FAILED; 1759 sdhci_req_done(slot); 1760 return; 1761 } 1762 1763 /* 1764 * Do not issue command if there is no card, clock or power. 1765 * Controller will not detect timeout without clock active. 1766 */ 1767 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1768 slot->power == 0 || 1769 slot->clock == 0) { 1770 slot_printf(slot, 1771 "Cannot issue a command (power=%d clock=%d)\n", 1772 slot->power, slot->clock); 1773 cmd->error = MMC_ERR_FAILED; 1774 sdhci_req_done(slot); 1775 return; 1776 } 1777 /* Always wait for free CMD bus. */ 1778 mask = SDHCI_CMD_INHIBIT; 1779 /* Wait for free DAT if we have data or busy signal. */ 1780 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1781 mask |= SDHCI_DAT_INHIBIT; 1782 /* 1783 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1784 * that these latter are also special in that SDHCI_CMD_DATA should 1785 * be set below but no actual data is ever read from the controller. 1786 */ 1787 #ifdef MMCCAM 1788 if (cmd == &slot->ccb->mmcio.stop || 1789 #else 1790 if (cmd == slot->req->stop || 1791 #endif 1792 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1793 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1794 mask &= ~SDHCI_DAT_INHIBIT; 1795 /* 1796 * Wait for bus no more then 250 ms. Typically there will be no wait 1797 * here at all, but when writing a crash dump we may be bypassing the 1798 * host platform's interrupt handler, and in some cases that handler 1799 * may be working around hardware quirks such as not respecting r1b 1800 * busy indications. In those cases, this wait-loop serves the purpose 1801 * of waiting for the prior command and data transfers to be done, and 1802 * SD cards are allowed to take up to 250ms for write and erase ops. 1803 * (It's usually more like 20-30ms in the real world.) 1804 */ 1805 timeout = 250; 1806 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1807 if (timeout == 0) { 1808 slot_printf(slot, "Controller never released " 1809 "inhibit bit(s).\n"); 1810 sdhci_dumpregs(slot); 1811 cmd->error = MMC_ERR_FAILED; 1812 sdhci_req_done(slot); 1813 return; 1814 } 1815 timeout--; 1816 DELAY(1000); 1817 } 1818 1819 /* Prepare command flags. */ 1820 if (!(cmd->flags & MMC_RSP_PRESENT)) 1821 flags = SDHCI_CMD_RESP_NONE; 1822 else if (cmd->flags & MMC_RSP_136) 1823 flags = SDHCI_CMD_RESP_LONG; 1824 else if (cmd->flags & MMC_RSP_BUSY) 1825 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1826 else 1827 flags = SDHCI_CMD_RESP_SHORT; 1828 if (cmd->flags & MMC_RSP_CRC) 1829 flags |= SDHCI_CMD_CRC; 1830 if (cmd->flags & MMC_RSP_OPCODE) 1831 flags |= SDHCI_CMD_INDEX; 1832 if (cmd->data != NULL) 1833 flags |= SDHCI_CMD_DATA; 1834 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1835 flags |= SDHCI_CMD_TYPE_ABORT; 1836 /* Prepare data. */ 1837 sdhci_start_data(slot, cmd->data); 1838 /* 1839 * Interrupt aggregation: To reduce total number of interrupts 1840 * group response interrupt with data interrupt when possible. 1841 * If there going to be data interrupt, mask response one. 1842 */ 1843 if (slot->data_done == 0) { 1844 WR4(slot, SDHCI_SIGNAL_ENABLE, 1845 slot->intmask &= ~SDHCI_INT_RESPONSE); 1846 } 1847 /* Set command argument. */ 1848 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1849 /* Set data transfer mode. */ 1850 sdhci_set_transfer_mode(slot, cmd->data); 1851 if (__predict_false(sdhci_debug > 1)) 1852 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n", 1853 cmd->opcode, flags); 1854 1855 /* Start command. */ 1856 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1857 /* Start timeout callout. */ 1858 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1859 sdhci_timeout, slot); 1860 } 1861 1862 static void 1863 sdhci_finish_command(struct sdhci_slot *slot) 1864 { 1865 int i; 1866 uint32_t val; 1867 uint8_t extra; 1868 1869 if (__predict_false(sdhci_debug > 1)) 1870 slot_printf(slot, "%s: called, err %d flags %#04x\n", 1871 __func__, slot->curcmd->error, slot->curcmd->flags); 1872 slot->cmd_done = 1; 1873 /* 1874 * Interrupt aggregation: Restore command interrupt. 1875 * Main restore point for the case when command interrupt 1876 * happened first. 1877 */ 1878 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1879 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1880 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1881 SDHCI_INT_RESPONSE); 1882 /* In case of error - reset host and return. */ 1883 if (slot->curcmd->error) { 1884 if (slot->curcmd->error == MMC_ERR_BADCRC) 1885 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1886 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD); 1887 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA); 1888 sdhci_start(slot); 1889 return; 1890 } 1891 /* If command has response - fetch it. */ 1892 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1893 if (slot->curcmd->flags & MMC_RSP_136) { 1894 /* CRC is stripped so we need one byte shift. */ 1895 extra = 0; 1896 for (i = 0; i < 4; i++) { 1897 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1898 if (slot->quirks & 1899 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1900 slot->curcmd->resp[3 - i] = val; 1901 else { 1902 slot->curcmd->resp[3 - i] = 1903 (val << 8) | extra; 1904 extra = val >> 24; 1905 } 1906 } 1907 } else 1908 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1909 } 1910 if (__predict_false(sdhci_debug > 1)) 1911 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n", 1912 slot->curcmd->resp[0], slot->curcmd->resp[1], 1913 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1914 1915 /* If data ready - finish. */ 1916 if (slot->data_done) 1917 sdhci_start(slot); 1918 } 1919 1920 static void 1921 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data) 1922 { 1923 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout; 1924 uint8_t div; 1925 1926 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1927 slot->data_done = 1; 1928 return; 1929 } 1930 1931 slot->data_done = 0; 1932 1933 /* Calculate and set data timeout.*/ 1934 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1935 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1936 div = 0xE; 1937 } else { 1938 target_timeout = 1000000; 1939 div = 0; 1940 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1941 while (current_timeout < target_timeout && div < 0xE) { 1942 ++div; 1943 current_timeout <<= 1; 1944 } 1945 /* Compensate for an off-by-one error in the CaFe chip.*/ 1946 if (div < 0xE && 1947 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1948 ++div; 1949 } 1950 } 1951 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1952 1953 if (data == NULL) 1954 return; 1955 1956 /* Use DMA if possible. */ 1957 if ((slot->opt & SDHCI_HAVE_DMA)) 1958 slot->flags |= SDHCI_USE_DMA; 1959 /* If data is small, broken DMA may return zeroes instead of data. */ 1960 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1961 (data->len <= 512)) 1962 slot->flags &= ~SDHCI_USE_DMA; 1963 /* Some controllers require even block sizes. */ 1964 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1965 ((data->len) & 0x3)) 1966 slot->flags &= ~SDHCI_USE_DMA; 1967 /* Load DMA buffer. */ 1968 if (slot->flags & SDHCI_USE_DMA) { 1969 sdma_bbufsz = slot->sdma_bbufsz; 1970 if (data->flags & MMC_DATA_READ) 1971 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1972 BUS_DMASYNC_PREREAD); 1973 else { 1974 memcpy(slot->dmamem, data->data, ulmin(data->len, 1975 sdma_bbufsz)); 1976 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1977 BUS_DMASYNC_PREWRITE); 1978 } 1979 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1980 /* 1981 * Interrupt aggregation: Mask border interrupt for the last 1982 * bounce buffer and unmask otherwise. 1983 */ 1984 if (data->len == sdma_bbufsz) 1985 slot->intmask &= ~SDHCI_INT_DMA_END; 1986 else 1987 slot->intmask |= SDHCI_INT_DMA_END; 1988 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1989 } 1990 /* Current data offset for both PIO and DMA. */ 1991 slot->offset = 0; 1992 #ifdef MMCCAM 1993 if (data->flags & MMC_DATA_BLOCK_SIZE) { 1994 /* Set block size and request border interrupts on the SDMA boundary. */ 1995 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size); 1996 blkcnt = data->block_count; 1997 if (__predict_false(sdhci_debug > 0)) 1998 slot_printf(slot, "SDIO Custom block params: blksz: " 1999 "%#10x, blk cnt: %#10x\n", blksz, blkcnt); 2000 } else 2001 #endif 2002 { 2003 /* Set block size and request border interrupts on the SDMA boundary. */ 2004 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512)); 2005 blkcnt = howmany(data->len, 512); 2006 } 2007 2008 WR2(slot, SDHCI_BLOCK_SIZE, blksz); 2009 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt); 2010 if (__predict_false(sdhci_debug > 1)) 2011 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 2012 blksz, blkcnt); 2013 } 2014 2015 void 2016 sdhci_finish_data(struct sdhci_slot *slot) 2017 { 2018 struct mmc_data *data = slot->curcmd->data; 2019 size_t left; 2020 2021 /* Interrupt aggregation: Restore command interrupt. 2022 * Auxiliary restore point for the case when data interrupt 2023 * happened first. */ 2024 if (!slot->cmd_done) { 2025 WR4(slot, SDHCI_SIGNAL_ENABLE, 2026 slot->intmask |= SDHCI_INT_RESPONSE); 2027 } 2028 /* Unload rest of data from DMA buffer. */ 2029 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 2030 slot->curcmd->data != NULL) { 2031 if (data->flags & MMC_DATA_READ) { 2032 left = data->len - slot->offset; 2033 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2034 BUS_DMASYNC_POSTREAD); 2035 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2036 ulmin(left, slot->sdma_bbufsz)); 2037 } else 2038 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2039 BUS_DMASYNC_POSTWRITE); 2040 } 2041 slot->data_done = 1; 2042 /* If there was error - reset the host. */ 2043 if (slot->curcmd->error) { 2044 if (slot->curcmd->error == MMC_ERR_BADCRC) 2045 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2046 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD); 2047 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA); 2048 sdhci_start(slot); 2049 return; 2050 } 2051 /* If we already have command response - finish. */ 2052 if (slot->cmd_done) 2053 sdhci_start(slot); 2054 } 2055 2056 #ifdef MMCCAM 2057 static void 2058 sdhci_start(struct sdhci_slot *slot) 2059 { 2060 union ccb *ccb; 2061 struct ccb_mmcio *mmcio; 2062 2063 ccb = slot->ccb; 2064 if (ccb == NULL) 2065 return; 2066 2067 mmcio = &ccb->mmcio; 2068 if (!(slot->flags & CMD_STARTED)) { 2069 slot->flags |= CMD_STARTED; 2070 sdhci_start_command(slot, &mmcio->cmd); 2071 return; 2072 } 2073 2074 /* 2075 * Old stack doesn't use this! 2076 * Enabling this code causes significant performance degradation 2077 * and IRQ storms on BBB, Wandboard behaves fine. 2078 * Not using this code does no harm... 2079 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 2080 slot->flags |= STOP_STARTED; 2081 sdhci_start_command(slot, &mmcio->stop); 2082 return; 2083 } 2084 */ 2085 if (__predict_false(sdhci_debug > 1)) 2086 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 2087 if (mmcio->cmd.error == 0 && 2088 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 2089 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD); 2090 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA); 2091 } 2092 2093 sdhci_req_done(slot); 2094 } 2095 #else 2096 static void 2097 sdhci_start(struct sdhci_slot *slot) 2098 { 2099 const struct mmc_request *req; 2100 2101 req = slot->req; 2102 if (req == NULL) 2103 return; 2104 2105 if (!(slot->flags & CMD_STARTED)) { 2106 slot->flags |= CMD_STARTED; 2107 sdhci_start_command(slot, req->cmd); 2108 return; 2109 } 2110 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 2111 !(slot->flags & STOP_STARTED) && req->stop) { 2112 slot->flags |= STOP_STARTED; 2113 sdhci_start_command(slot, req->stop); 2114 return; 2115 } 2116 if (__predict_false(sdhci_debug > 1)) 2117 slot_printf(slot, "result: %d\n", req->cmd->error); 2118 if (!req->cmd->error && 2119 ((slot->curcmd == req->stop && 2120 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 2121 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2122 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD); 2123 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA); 2124 } 2125 2126 sdhci_req_done(slot); 2127 } 2128 #endif 2129 2130 int 2131 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 2132 struct mmc_request *req) 2133 { 2134 struct sdhci_slot *slot = device_get_ivars(reqdev); 2135 2136 SDHCI_LOCK(slot); 2137 if (slot->req != NULL) { 2138 SDHCI_UNLOCK(slot); 2139 return (EBUSY); 2140 } 2141 if (__predict_false(sdhci_debug > 1)) { 2142 slot_printf(slot, 2143 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2144 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 2145 (req->cmd->data)?(u_int)req->cmd->data->len:0, 2146 (req->cmd->data)?req->cmd->data->flags:0); 2147 } 2148 slot->req = req; 2149 slot->flags = 0; 2150 sdhci_start(slot); 2151 SDHCI_UNLOCK(slot); 2152 if (dumping) { 2153 while (slot->req != NULL) { 2154 sdhci_generic_intr(slot); 2155 DELAY(10); 2156 } 2157 } 2158 return (0); 2159 } 2160 2161 int 2162 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 2163 { 2164 struct sdhci_slot *slot = device_get_ivars(reqdev); 2165 uint32_t val; 2166 2167 SDHCI_LOCK(slot); 2168 val = RD4(slot, SDHCI_PRESENT_STATE); 2169 SDHCI_UNLOCK(slot); 2170 return (!(val & SDHCI_WRITE_PROTECT)); 2171 } 2172 2173 int 2174 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 2175 { 2176 struct sdhci_slot *slot = device_get_ivars(reqdev); 2177 int err = 0; 2178 2179 SDHCI_LOCK(slot); 2180 while (slot->bus_busy) 2181 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 2182 slot->bus_busy++; 2183 /* Activate led. */ 2184 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 2185 SDHCI_UNLOCK(slot); 2186 return (err); 2187 } 2188 2189 int 2190 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 2191 { 2192 struct sdhci_slot *slot = device_get_ivars(reqdev); 2193 2194 SDHCI_LOCK(slot); 2195 /* Deactivate led. */ 2196 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 2197 slot->bus_busy--; 2198 wakeup(slot); 2199 SDHCI_UNLOCK(slot); 2200 return (0); 2201 } 2202 2203 static void 2204 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2205 { 2206 2207 if (!slot->curcmd) { 2208 slot_printf(slot, "Got command interrupt 0x%08x, but " 2209 "there is no active command.\n", intmask); 2210 sdhci_dumpregs(slot); 2211 return; 2212 } 2213 if (intmask & SDHCI_INT_TIMEOUT) 2214 slot->curcmd->error = MMC_ERR_TIMEOUT; 2215 else if (intmask & SDHCI_INT_CRC) 2216 slot->curcmd->error = MMC_ERR_BADCRC; 2217 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2218 slot->curcmd->error = MMC_ERR_FIFO; 2219 2220 sdhci_finish_command(slot); 2221 } 2222 2223 static void 2224 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2225 { 2226 struct mmc_data *data; 2227 size_t left; 2228 uint32_t sdma_bbufsz; 2229 2230 if (!slot->curcmd) { 2231 slot_printf(slot, "Got data interrupt 0x%08x, but " 2232 "there is no active command.\n", intmask); 2233 sdhci_dumpregs(slot); 2234 return; 2235 } 2236 if (slot->curcmd->data == NULL && 2237 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2238 slot_printf(slot, "Got data interrupt 0x%08x, but " 2239 "there is no active data operation.\n", 2240 intmask); 2241 sdhci_dumpregs(slot); 2242 return; 2243 } 2244 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2245 slot->curcmd->error = MMC_ERR_TIMEOUT; 2246 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2247 slot->curcmd->error = MMC_ERR_BADCRC; 2248 if (slot->curcmd->data == NULL && 2249 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2250 SDHCI_INT_DMA_END))) { 2251 slot_printf(slot, "Got data interrupt 0x%08x, but " 2252 "there is busy-only command.\n", intmask); 2253 sdhci_dumpregs(slot); 2254 slot->curcmd->error = MMC_ERR_INVALID; 2255 } 2256 if (slot->curcmd->error) { 2257 /* No need to continue after any error. */ 2258 goto done; 2259 } 2260 2261 /* Handle tuning completion interrupt. */ 2262 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2263 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2264 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2265 slot->req->flags |= MMC_TUNE_DONE; 2266 sdhci_finish_command(slot); 2267 sdhci_finish_data(slot); 2268 return; 2269 } 2270 /* Handle PIO interrupt. */ 2271 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2272 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2273 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2274 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2275 &intmask); 2276 slot->flags |= PLATFORM_DATA_STARTED; 2277 } else 2278 sdhci_transfer_pio(slot); 2279 } 2280 /* Handle DMA border. */ 2281 if (intmask & SDHCI_INT_DMA_END) { 2282 data = slot->curcmd->data; 2283 sdma_bbufsz = slot->sdma_bbufsz; 2284 2285 /* Unload DMA buffer ... */ 2286 left = data->len - slot->offset; 2287 if (data->flags & MMC_DATA_READ) { 2288 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2289 BUS_DMASYNC_POSTREAD); 2290 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2291 ulmin(left, sdma_bbufsz)); 2292 } else { 2293 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2294 BUS_DMASYNC_POSTWRITE); 2295 } 2296 /* ... and reload it again. */ 2297 slot->offset += sdma_bbufsz; 2298 left = data->len - slot->offset; 2299 if (data->flags & MMC_DATA_READ) { 2300 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2301 BUS_DMASYNC_PREREAD); 2302 } else { 2303 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2304 ulmin(left, sdma_bbufsz)); 2305 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2306 BUS_DMASYNC_PREWRITE); 2307 } 2308 /* 2309 * Interrupt aggregation: Mask border interrupt for the last 2310 * bounce buffer. 2311 */ 2312 if (left == sdma_bbufsz) { 2313 slot->intmask &= ~SDHCI_INT_DMA_END; 2314 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2315 } 2316 /* Restart DMA. */ 2317 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2318 } 2319 /* We have got all data. */ 2320 if (intmask & SDHCI_INT_DATA_END) { 2321 if (slot->flags & PLATFORM_DATA_STARTED) { 2322 slot->flags &= ~PLATFORM_DATA_STARTED; 2323 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2324 } else 2325 sdhci_finish_data(slot); 2326 } 2327 done: 2328 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2329 if (slot->flags & PLATFORM_DATA_STARTED) { 2330 slot->flags &= ~PLATFORM_DATA_STARTED; 2331 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2332 } else 2333 sdhci_finish_data(slot); 2334 } 2335 } 2336 2337 static void 2338 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) 2339 { 2340 2341 if (!slot->curcmd) { 2342 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2343 "there is no active command.\n", acmd_err); 2344 sdhci_dumpregs(slot); 2345 return; 2346 } 2347 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err); 2348 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD); 2349 } 2350 2351 void 2352 sdhci_generic_intr(struct sdhci_slot *slot) 2353 { 2354 uint32_t intmask, present; 2355 uint16_t val16; 2356 2357 SDHCI_LOCK(slot); 2358 /* Read slot interrupt status. */ 2359 intmask = RD4(slot, SDHCI_INT_STATUS); 2360 if (intmask == 0 || intmask == 0xffffffff) { 2361 SDHCI_UNLOCK(slot); 2362 return; 2363 } 2364 if (__predict_false(sdhci_debug > 2)) 2365 slot_printf(slot, "Interrupt %#x\n", intmask); 2366 2367 /* Handle tuning error interrupt. */ 2368 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2369 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR); 2370 slot_printf(slot, "Tuning error indicated\n"); 2371 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2372 if (slot->curcmd) { 2373 slot->curcmd->error = MMC_ERR_BADCRC; 2374 sdhci_finish_command(slot); 2375 } 2376 } 2377 /* Handle re-tuning interrupt. */ 2378 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2379 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2380 /* Handle card presence interrupts. */ 2381 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2382 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2383 slot->intmask &= 2384 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2385 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2386 SDHCI_INT_CARD_INSERT; 2387 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2388 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2389 WR4(slot, SDHCI_INT_STATUS, intmask & 2390 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2391 sdhci_handle_card_present_locked(slot, present); 2392 } 2393 /* Handle command interrupts. */ 2394 if (intmask & SDHCI_INT_CMD_MASK) { 2395 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2396 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2397 } 2398 /* Handle data interrupts. */ 2399 if (intmask & SDHCI_INT_DATA_MASK) { 2400 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2401 /* Don't call data_irq in case of errored command. */ 2402 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2403 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2404 } 2405 /* Handle AutoCMD12 error interrupt. */ 2406 if (intmask & SDHCI_INT_ACMD12ERR) { 2407 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */ 2408 val16 = RD2(slot, SDHCI_ACMD12_ERR); 2409 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2410 sdhci_acmd_irq(slot, val16); 2411 } 2412 /* Handle bus power interrupt. */ 2413 if (intmask & SDHCI_INT_BUS_POWER) { 2414 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2415 slot_printf(slot, "Card is consuming too much power!\n"); 2416 } 2417 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2418 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2419 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2420 /* The rest is unknown. */ 2421 if (intmask) { 2422 WR4(slot, SDHCI_INT_STATUS, intmask); 2423 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2424 intmask); 2425 sdhci_dumpregs(slot); 2426 } 2427 2428 SDHCI_UNLOCK(slot); 2429 } 2430 2431 int 2432 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2433 uintptr_t *result) 2434 { 2435 const struct sdhci_slot *slot = device_get_ivars(child); 2436 2437 switch (which) { 2438 default: 2439 return (EINVAL); 2440 case MMCBR_IVAR_BUS_MODE: 2441 *result = slot->host.ios.bus_mode; 2442 break; 2443 case MMCBR_IVAR_BUS_WIDTH: 2444 *result = slot->host.ios.bus_width; 2445 break; 2446 case MMCBR_IVAR_CHIP_SELECT: 2447 *result = slot->host.ios.chip_select; 2448 break; 2449 case MMCBR_IVAR_CLOCK: 2450 *result = slot->host.ios.clock; 2451 break; 2452 case MMCBR_IVAR_F_MIN: 2453 *result = slot->host.f_min; 2454 break; 2455 case MMCBR_IVAR_F_MAX: 2456 *result = slot->host.f_max; 2457 break; 2458 case MMCBR_IVAR_HOST_OCR: 2459 *result = slot->host.host_ocr; 2460 break; 2461 case MMCBR_IVAR_MODE: 2462 *result = slot->host.mode; 2463 break; 2464 case MMCBR_IVAR_OCR: 2465 *result = slot->host.ocr; 2466 break; 2467 case MMCBR_IVAR_POWER_MODE: 2468 *result = slot->host.ios.power_mode; 2469 break; 2470 case MMCBR_IVAR_VDD: 2471 *result = slot->host.ios.vdd; 2472 break; 2473 case MMCBR_IVAR_RETUNE_REQ: 2474 if (slot->opt & SDHCI_TUNING_ENABLED) { 2475 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2476 *result = retune_req_reset; 2477 break; 2478 } 2479 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2480 *result = retune_req_normal; 2481 break; 2482 } 2483 } 2484 *result = retune_req_none; 2485 break; 2486 case MMCBR_IVAR_VCCQ: 2487 *result = slot->host.ios.vccq; 2488 break; 2489 case MMCBR_IVAR_CAPS: 2490 *result = slot->host.caps; 2491 break; 2492 case MMCBR_IVAR_TIMING: 2493 *result = slot->host.ios.timing; 2494 break; 2495 case MMCBR_IVAR_MAX_DATA: 2496 /* 2497 * Re-tuning modes 1 and 2 restrict the maximum data length 2498 * per read/write command to 4 MiB. 2499 */ 2500 if (slot->opt & SDHCI_TUNING_ENABLED && 2501 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2502 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2503 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2504 break; 2505 } 2506 *result = 65535; 2507 break; 2508 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2509 /* 2510 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2511 */ 2512 *result = 1000000; 2513 break; 2514 } 2515 return (0); 2516 } 2517 2518 int 2519 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2520 uintptr_t value) 2521 { 2522 struct sdhci_slot *slot = device_get_ivars(child); 2523 uint32_t clock, max_clock; 2524 int i; 2525 2526 if (sdhci_debug > 1) 2527 slot_printf(slot, "%s: var=%d\n", __func__, which); 2528 switch (which) { 2529 default: 2530 return (EINVAL); 2531 case MMCBR_IVAR_BUS_MODE: 2532 slot->host.ios.bus_mode = value; 2533 break; 2534 case MMCBR_IVAR_BUS_WIDTH: 2535 slot->host.ios.bus_width = value; 2536 break; 2537 case MMCBR_IVAR_CHIP_SELECT: 2538 slot->host.ios.chip_select = value; 2539 break; 2540 case MMCBR_IVAR_CLOCK: 2541 if (value > 0) { 2542 max_clock = slot->max_clk; 2543 clock = max_clock; 2544 2545 if (slot->version < SDHCI_SPEC_300) { 2546 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2547 i <<= 1) { 2548 if (clock <= value) 2549 break; 2550 clock >>= 1; 2551 } 2552 } else { 2553 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2554 i += 2) { 2555 if (clock <= value) 2556 break; 2557 clock = max_clock / (i + 2); 2558 } 2559 } 2560 2561 slot->host.ios.clock = clock; 2562 } else 2563 slot->host.ios.clock = 0; 2564 break; 2565 case MMCBR_IVAR_MODE: 2566 slot->host.mode = value; 2567 break; 2568 case MMCBR_IVAR_OCR: 2569 slot->host.ocr = value; 2570 break; 2571 case MMCBR_IVAR_POWER_MODE: 2572 slot->host.ios.power_mode = value; 2573 break; 2574 case MMCBR_IVAR_VDD: 2575 slot->host.ios.vdd = value; 2576 break; 2577 case MMCBR_IVAR_VCCQ: 2578 slot->host.ios.vccq = value; 2579 break; 2580 case MMCBR_IVAR_TIMING: 2581 slot->host.ios.timing = value; 2582 break; 2583 case MMCBR_IVAR_CAPS: 2584 case MMCBR_IVAR_HOST_OCR: 2585 case MMCBR_IVAR_F_MIN: 2586 case MMCBR_IVAR_F_MAX: 2587 case MMCBR_IVAR_MAX_DATA: 2588 case MMCBR_IVAR_RETUNE_REQ: 2589 return (EINVAL); 2590 } 2591 return (0); 2592 } 2593 2594 #ifdef MMCCAM 2595 void 2596 sdhci_start_slot(struct sdhci_slot *slot) 2597 { 2598 2599 if ((slot->devq = cam_simq_alloc(1)) == NULL) 2600 goto fail; 2601 2602 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2603 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2604 "sdhci_slot", slot, device_get_unit(slot->bus), 2605 &slot->sim_mtx, 1, 1, slot->devq); 2606 2607 if (slot->sim == NULL) { 2608 cam_simq_free(slot->devq); 2609 slot_printf(slot, "cannot allocate CAM SIM\n"); 2610 goto fail; 2611 } 2612 2613 mtx_lock(&slot->sim_mtx); 2614 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2615 slot_printf(slot, "cannot register SCSI pass-through bus\n"); 2616 cam_sim_free(slot->sim, FALSE); 2617 cam_simq_free(slot->devq); 2618 mtx_unlock(&slot->sim_mtx); 2619 goto fail; 2620 } 2621 mtx_unlock(&slot->sim_mtx); 2622 2623 /* End CAM-specific init */ 2624 slot->card_present = 0; 2625 sdhci_card_task(slot, 0); 2626 return; 2627 2628 fail: 2629 if (slot->sim != NULL) { 2630 mtx_lock(&slot->sim_mtx); 2631 xpt_bus_deregister(cam_sim_path(slot->sim)); 2632 cam_sim_free(slot->sim, FALSE); 2633 mtx_unlock(&slot->sim_mtx); 2634 } 2635 2636 if (slot->devq != NULL) 2637 cam_simq_free(slot->devq); 2638 } 2639 2640 void 2641 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2642 { 2643 struct sdhci_slot *slot; 2644 2645 slot = cam_sim_softc(sim); 2646 if (slot == NULL) { 2647 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2648 xpt_done(ccb); 2649 return; 2650 } 2651 2652 mtx_assert(&slot->sim_mtx, MA_OWNED); 2653 2654 switch (ccb->ccb_h.func_code) { 2655 case XPT_PATH_INQ: 2656 mmc_path_inq(&ccb->cpi, "Deglitch Networks", sim, maxphys); 2657 break; 2658 2659 case XPT_MMC_GET_TRAN_SETTINGS: 2660 case XPT_GET_TRAN_SETTINGS: 2661 { 2662 struct ccb_trans_settings *cts = &ccb->cts; 2663 uint32_t max_data; 2664 2665 if (sdhci_debug > 1) 2666 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2667 2668 cts->protocol = PROTO_MMCSD; 2669 cts->protocol_version = 1; 2670 cts->transport = XPORT_MMCSD; 2671 cts->transport_version = 1; 2672 cts->xport_specific.valid = 0; 2673 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2674 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2675 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2676 cts->proto_specific.mmc.host_caps = slot->host.caps; 2677 /* 2678 * Re-tuning modes 1 and 2 restrict the maximum data length 2679 * per read/write command to 4 MiB. 2680 */ 2681 if (slot->opt & SDHCI_TUNING_ENABLED && 2682 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2683 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2684 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2685 } else { 2686 max_data = 65535; 2687 } 2688 cts->proto_specific.mmc.host_max_data = max_data; 2689 2690 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2691 ccb->ccb_h.status = CAM_REQ_CMP; 2692 break; 2693 } 2694 case XPT_MMC_SET_TRAN_SETTINGS: 2695 case XPT_SET_TRAN_SETTINGS: 2696 if (sdhci_debug > 1) 2697 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2698 sdhci_cam_settran_settings(slot, ccb); 2699 ccb->ccb_h.status = CAM_REQ_CMP; 2700 break; 2701 case XPT_RESET_BUS: 2702 if (sdhci_debug > 1) 2703 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2704 ccb->ccb_h.status = CAM_REQ_CMP; 2705 break; 2706 case XPT_MMC_IO: 2707 /* 2708 * Here is the HW-dependent part of 2709 * sending the command to the underlying h/w 2710 * At some point in the future an interrupt comes. 2711 * Then the request will be marked as completed. 2712 */ 2713 if (__predict_false(sdhci_debug > 1)) 2714 slot_printf(slot, "Got XPT_MMC_IO\n"); 2715 ccb->ccb_h.status = CAM_REQ_INPROG; 2716 2717 sdhci_cam_request(cam_sim_softc(sim), ccb); 2718 return; 2719 default: 2720 ccb->ccb_h.status = CAM_REQ_INVALID; 2721 break; 2722 } 2723 xpt_done(ccb); 2724 return; 2725 } 2726 2727 void 2728 sdhci_cam_poll(struct cam_sim *sim) 2729 { 2730 sdhci_generic_intr(cam_sim_softc(sim)); 2731 } 2732 2733 static int 2734 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 2735 int proposed_clock) 2736 { 2737 int max_clock, clock, i; 2738 2739 if (proposed_clock == 0) 2740 return 0; 2741 max_clock = slot->max_clk; 2742 clock = max_clock; 2743 2744 if (slot->version < SDHCI_SPEC_300) { 2745 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) { 2746 if (clock <= proposed_clock) 2747 break; 2748 clock >>= 1; 2749 } 2750 } else { 2751 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) { 2752 if (clock <= proposed_clock) 2753 break; 2754 clock = max_clock / (i + 2); 2755 } 2756 } 2757 return clock; 2758 } 2759 2760 static int 2761 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2762 { 2763 struct mmc_ios *ios; 2764 const struct mmc_ios *new_ios; 2765 const struct ccb_trans_settings_mmc *cts; 2766 2767 ios = &slot->host.ios; 2768 cts = &ccb->cts.proto_specific.mmc; 2769 new_ios = &cts->ios; 2770 2771 /* Update only requested fields */ 2772 if (cts->ios_valid & MMC_CLK) { 2773 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2774 if (sdhci_debug > 1) 2775 slot_printf(slot, "Clock => %d\n", ios->clock); 2776 } 2777 if (cts->ios_valid & MMC_VDD) { 2778 ios->vdd = new_ios->vdd; 2779 if (sdhci_debug > 1) 2780 slot_printf(slot, "VDD => %d\n", ios->vdd); 2781 } 2782 if (cts->ios_valid & MMC_CS) { 2783 ios->chip_select = new_ios->chip_select; 2784 if (sdhci_debug > 1) 2785 slot_printf(slot, "CS => %d\n", ios->chip_select); 2786 } 2787 if (cts->ios_valid & MMC_BW) { 2788 ios->bus_width = new_ios->bus_width; 2789 if (sdhci_debug > 1) 2790 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2791 } 2792 if (cts->ios_valid & MMC_PM) { 2793 ios->power_mode = new_ios->power_mode; 2794 if (sdhci_debug > 1) 2795 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2796 } 2797 if (cts->ios_valid & MMC_BT) { 2798 ios->timing = new_ios->timing; 2799 if (sdhci_debug > 1) 2800 slot_printf(slot, "Timing => %d\n", ios->timing); 2801 } 2802 if (cts->ios_valid & MMC_BM) { 2803 ios->bus_mode = new_ios->bus_mode; 2804 if (sdhci_debug > 1) 2805 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2806 } 2807 if (cts->ios_valid & MMC_VCCQ) { 2808 ios->vccq = new_ios->vccq; 2809 if (sdhci_debug > 1) 2810 slot_printf(slot, "VCCQ => %d\n", ios->vccq); 2811 } 2812 2813 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2814 return (sdhci_cam_update_ios(slot)); 2815 } 2816 2817 static int 2818 sdhci_cam_update_ios(struct sdhci_slot *slot) 2819 { 2820 struct mmc_ios *ios = &slot->host.ios; 2821 2822 if (sdhci_debug > 1) 2823 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2824 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2825 SDHCI_LOCK(slot); 2826 /* Do full reset on bus power down to clear from any state. */ 2827 if (ios->power_mode == power_off) { 2828 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2829 sdhci_init(slot); 2830 } 2831 /* Configure the bus. */ 2832 sdhci_set_clock(slot, ios->clock); 2833 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2834 if (ios->bus_width == bus_width_8) { 2835 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2836 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2837 } else if (ios->bus_width == bus_width_4) { 2838 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2839 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2840 } else if (ios->bus_width == bus_width_1) { 2841 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2842 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2843 } else { 2844 panic("Invalid bus width: %d", ios->bus_width); 2845 } 2846 if (ios->timing == bus_timing_hs && 2847 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2848 slot->hostctrl |= SDHCI_CTRL_HISPD; 2849 else 2850 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2851 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2852 /* Some controllers like reset after bus changes. */ 2853 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2854 SDHCI_RESET(slot->bus, slot, 2855 SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2856 2857 SDHCI_UNLOCK(slot); 2858 return (0); 2859 } 2860 2861 static int 2862 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2863 { 2864 const struct ccb_mmcio *mmcio; 2865 2866 mmcio = &ccb->mmcio; 2867 2868 SDHCI_LOCK(slot); 2869 /* if (slot->req != NULL) { 2870 SDHCI_UNLOCK(slot); 2871 return (EBUSY); 2872 } 2873 */ 2874 if (__predict_false(sdhci_debug > 1)) { 2875 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x " 2876 "blksz=%zu blkcnt=%zu\n", 2877 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2878 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2879 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0, 2880 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0, 2881 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0); 2882 } 2883 if (mmcio->cmd.data != NULL) { 2884 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2885 panic("data->len = %d, data->flags = %d -- something is b0rked", 2886 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2887 } 2888 slot->ccb = ccb; 2889 slot->flags = 0; 2890 sdhci_start(slot); 2891 SDHCI_UNLOCK(slot); 2892 return (0); 2893 } 2894 #endif /* MMCCAM */ 2895 2896 MODULE_VERSION(sdhci, SDHCI_VERSION); 2897