1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 59 "Debug level"); 60 61 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 62 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 64 #define RD_MULTI_4(slot, off, ptr, count) \ 65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 66 67 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 68 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 70 #define WR_MULTI_4(slot, off, ptr, count) \ 71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 72 73 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 74 static void sdhci_start(struct sdhci_slot *slot); 75 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 76 77 static void sdhci_card_poll(void *); 78 static void sdhci_card_task(void *, int); 79 80 /* helper routines */ 81 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 82 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 83 #define SDHCI_LOCK_INIT(_slot) \ 84 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 85 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 86 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 87 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 88 89 #define SDHCI_DEFAULT_MAX_FREQ 50 90 91 #define SDHCI_200_MAX_DIVIDER 256 92 #define SDHCI_300_MAX_DIVIDER 2046 93 94 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 95 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 96 97 /* 98 * Broadcom BCM577xx Controller Constants 99 */ 100 /* Maximum divider supported by the default clock source. */ 101 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 102 /* Alternative clock's base frequency. */ 103 #define BCM577XX_ALT_CLOCK_BASE 63000000 104 105 #define BCM577XX_HOST_CONTROL 0x198 106 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 107 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 108 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 109 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 110 111 static void 112 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 113 { 114 115 if (error != 0) { 116 printf("getaddr: error %d\n", error); 117 return; 118 } 119 *(bus_addr_t *)arg = segs[0].ds_addr; 120 } 121 122 static int 123 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 124 { 125 va_list ap; 126 int retval; 127 128 retval = printf("%s-slot%d: ", 129 device_get_nameunit(slot->bus), slot->num); 130 131 va_start(ap, fmt); 132 retval += vprintf(fmt, ap); 133 va_end(ap); 134 return (retval); 135 } 136 137 static void 138 sdhci_dumpregs(struct sdhci_slot *slot) 139 { 140 141 slot_printf(slot, 142 "============== REGISTER DUMP ==============\n"); 143 144 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 145 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 146 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 147 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 148 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 149 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 150 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 151 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 152 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 153 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 154 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 155 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 156 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 157 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 158 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 159 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 160 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 161 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 162 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 163 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 164 165 slot_printf(slot, 166 "===========================================\n"); 167 } 168 169 static void 170 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 171 { 172 int timeout; 173 uint32_t clock; 174 175 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 176 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 177 return; 178 } 179 180 /* Some controllers need this kick or reset won't work. */ 181 if ((mask & SDHCI_RESET_ALL) == 0 && 182 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 183 /* This is to force an update */ 184 clock = slot->clock; 185 slot->clock = 0; 186 sdhci_set_clock(slot, clock); 187 } 188 189 if (mask & SDHCI_RESET_ALL) { 190 slot->clock = 0; 191 slot->power = 0; 192 } 193 194 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 195 196 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 197 /* 198 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 199 * specification. The reset bit has internal propagation delay, 200 * so a fast read after write returns 0 even if reset process is 201 * in progress. The workaround is to poll for 1 before polling 202 * for 0. In the worst case, if we miss seeing it asserted the 203 * time we spent waiting is enough to ensure the reset finishes. 204 */ 205 timeout = 10000; 206 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 207 if (timeout <= 0) 208 break; 209 timeout--; 210 DELAY(1); 211 } 212 } 213 214 /* Wait max 100 ms */ 215 timeout = 10000; 216 /* Controller clears the bits when it's done */ 217 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 218 if (timeout <= 0) { 219 slot_printf(slot, "Reset 0x%x never completed.\n", 220 mask); 221 sdhci_dumpregs(slot); 222 return; 223 } 224 timeout--; 225 DELAY(10); 226 } 227 } 228 229 static void 230 sdhci_init(struct sdhci_slot *slot) 231 { 232 233 sdhci_reset(slot, SDHCI_RESET_ALL); 234 235 /* Enable interrupts. */ 236 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 238 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 239 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 240 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 241 SDHCI_INT_ACMD12ERR; 242 243 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 244 !(slot->opt & SDHCI_NON_REMOVABLE)) { 245 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 246 } 247 248 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 249 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 250 } 251 252 static void 253 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 254 { 255 uint32_t clk_base; 256 uint32_t clk_sel; 257 uint32_t res; 258 uint16_t clk; 259 uint16_t div; 260 int timeout; 261 262 if (clock == slot->clock) 263 return; 264 slot->clock = clock; 265 266 /* Turn off the clock. */ 267 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 268 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 269 /* If no clock requested - leave it so. */ 270 if (clock == 0) 271 return; 272 273 /* Determine the clock base frequency */ 274 clk_base = slot->max_clk; 275 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 276 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 277 BCM577XX_CTRL_CLKSEL_MASK; 278 279 /* 280 * Select clock source appropriate for the requested frequency. 281 */ 282 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 283 clk_base = BCM577XX_ALT_CLOCK_BASE; 284 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 285 BCM577XX_CTRL_CLKSEL_SHIFT); 286 } else { 287 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 288 BCM577XX_CTRL_CLKSEL_SHIFT); 289 } 290 291 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 292 } 293 294 /* Recalculate timeout clock frequency based on the new sd clock. */ 295 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 296 slot->timeout_clk = slot->clock / 1000; 297 298 if (slot->version < SDHCI_SPEC_300) { 299 /* Looking for highest freq <= clock. */ 300 res = clk_base; 301 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 302 if (res <= clock) 303 break; 304 res >>= 1; 305 } 306 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 307 div >>= 1; 308 } 309 else { 310 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 311 if (clock >= clk_base) 312 div = 0; 313 else { 314 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 315 if ((clk_base / div) <= clock) 316 break; 317 } 318 } 319 div >>= 1; 320 } 321 322 if (bootverbose || sdhci_debug) 323 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 324 div, clock, clk_base); 325 326 /* Now we have got divider, set it. */ 327 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 328 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 329 << SDHCI_DIVIDER_HI_SHIFT; 330 331 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 332 /* Enable clock. */ 333 clk |= SDHCI_CLOCK_INT_EN; 334 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 335 /* Wait up to 10 ms until it stabilize. */ 336 timeout = 10; 337 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 338 & SDHCI_CLOCK_INT_STABLE)) { 339 if (timeout == 0) { 340 slot_printf(slot, 341 "Internal clock never stabilised.\n"); 342 sdhci_dumpregs(slot); 343 return; 344 } 345 timeout--; 346 DELAY(1000); 347 } 348 /* Pass clock signal to the bus. */ 349 clk |= SDHCI_CLOCK_CARD_EN; 350 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 351 } 352 353 static void 354 sdhci_set_power(struct sdhci_slot *slot, u_char power) 355 { 356 uint8_t pwr; 357 358 if (slot->power == power) 359 return; 360 361 slot->power = power; 362 363 /* Turn off the power. */ 364 pwr = 0; 365 WR1(slot, SDHCI_POWER_CONTROL, pwr); 366 /* If power down requested - leave it so. */ 367 if (power == 0) 368 return; 369 /* Set voltage. */ 370 switch (1 << power) { 371 case MMC_OCR_LOW_VOLTAGE: 372 pwr |= SDHCI_POWER_180; 373 break; 374 case MMC_OCR_290_300: 375 case MMC_OCR_300_310: 376 pwr |= SDHCI_POWER_300; 377 break; 378 case MMC_OCR_320_330: 379 case MMC_OCR_330_340: 380 pwr |= SDHCI_POWER_330; 381 break; 382 } 383 WR1(slot, SDHCI_POWER_CONTROL, pwr); 384 /* Turn on the power. */ 385 pwr |= SDHCI_POWER_ON; 386 WR1(slot, SDHCI_POWER_CONTROL, pwr); 387 388 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 389 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 390 DELAY(10); 391 WR1(slot, SDHCI_POWER_CONTROL, pwr); 392 DELAY(300); 393 } 394 } 395 396 static void 397 sdhci_read_block_pio(struct sdhci_slot *slot) 398 { 399 uint32_t data; 400 char *buffer; 401 size_t left; 402 403 buffer = slot->curcmd->data->data; 404 buffer += slot->offset; 405 /* Transfer one block at a time. */ 406 left = min(512, slot->curcmd->data->len - slot->offset); 407 slot->offset += left; 408 409 /* If we are too fast, broken controllers return zeroes. */ 410 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 411 DELAY(10); 412 /* Handle unaligned and aligned buffer cases. */ 413 if ((intptr_t)buffer & 3) { 414 while (left > 3) { 415 data = RD4(slot, SDHCI_BUFFER); 416 buffer[0] = data; 417 buffer[1] = (data >> 8); 418 buffer[2] = (data >> 16); 419 buffer[3] = (data >> 24); 420 buffer += 4; 421 left -= 4; 422 } 423 } else { 424 RD_MULTI_4(slot, SDHCI_BUFFER, 425 (uint32_t *)buffer, left >> 2); 426 left &= 3; 427 } 428 /* Handle uneven size case. */ 429 if (left > 0) { 430 data = RD4(slot, SDHCI_BUFFER); 431 while (left > 0) { 432 *(buffer++) = data; 433 data >>= 8; 434 left--; 435 } 436 } 437 } 438 439 static void 440 sdhci_write_block_pio(struct sdhci_slot *slot) 441 { 442 uint32_t data = 0; 443 char *buffer; 444 size_t left; 445 446 buffer = slot->curcmd->data->data; 447 buffer += slot->offset; 448 /* Transfer one block at a time. */ 449 left = min(512, slot->curcmd->data->len - slot->offset); 450 slot->offset += left; 451 452 /* Handle unaligned and aligned buffer cases. */ 453 if ((intptr_t)buffer & 3) { 454 while (left > 3) { 455 data = buffer[0] + 456 (buffer[1] << 8) + 457 (buffer[2] << 16) + 458 (buffer[3] << 24); 459 left -= 4; 460 buffer += 4; 461 WR4(slot, SDHCI_BUFFER, data); 462 } 463 } else { 464 WR_MULTI_4(slot, SDHCI_BUFFER, 465 (uint32_t *)buffer, left >> 2); 466 left &= 3; 467 } 468 /* Handle uneven size case. */ 469 if (left > 0) { 470 while (left > 0) { 471 data <<= 8; 472 data += *(buffer++); 473 left--; 474 } 475 WR4(slot, SDHCI_BUFFER, data); 476 } 477 } 478 479 static void 480 sdhci_transfer_pio(struct sdhci_slot *slot) 481 { 482 483 /* Read as many blocks as possible. */ 484 if (slot->curcmd->data->flags & MMC_DATA_READ) { 485 while (RD4(slot, SDHCI_PRESENT_STATE) & 486 SDHCI_DATA_AVAILABLE) { 487 sdhci_read_block_pio(slot); 488 if (slot->offset >= slot->curcmd->data->len) 489 break; 490 } 491 } else { 492 while (RD4(slot, SDHCI_PRESENT_STATE) & 493 SDHCI_SPACE_AVAILABLE) { 494 sdhci_write_block_pio(slot); 495 if (slot->offset >= slot->curcmd->data->len) 496 break; 497 } 498 } 499 } 500 501 static void 502 sdhci_card_task(void *arg, int pending __unused) 503 { 504 struct sdhci_slot *slot = arg; 505 device_t d; 506 507 SDHCI_LOCK(slot); 508 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 509 if (slot->dev == NULL) { 510 /* If card is present - attach mmc bus. */ 511 if (bootverbose || sdhci_debug) 512 slot_printf(slot, "Card inserted\n"); 513 slot->dev = device_add_child(slot->bus, "mmc", -1); 514 device_set_ivars(slot->dev, slot); 515 SDHCI_UNLOCK(slot); 516 device_probe_and_attach(slot->dev); 517 } else 518 SDHCI_UNLOCK(slot); 519 } else { 520 if (slot->dev != NULL) { 521 /* If no card present - detach mmc bus. */ 522 if (bootverbose || sdhci_debug) 523 slot_printf(slot, "Card removed\n"); 524 d = slot->dev; 525 slot->dev = NULL; 526 SDHCI_UNLOCK(slot); 527 device_delete_child(slot->bus, d); 528 } else 529 SDHCI_UNLOCK(slot); 530 } 531 } 532 533 static void 534 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 535 { 536 bool was_present; 537 538 /* 539 * If there was no card and now there is one, schedule the task to 540 * create the child device after a short delay. The delay is to 541 * debounce the card insert (sometimes the card detect pin stabilizes 542 * before the other pins have made good contact). 543 * 544 * If there was a card present and now it's gone, immediately schedule 545 * the task to delete the child device. No debouncing -- gone is gone, 546 * because once power is removed, a full card re-init is needed, and 547 * that happens by deleting and recreating the child device. 548 */ 549 was_present = slot->dev != NULL; 550 if (!was_present && is_present) { 551 taskqueue_enqueue_timeout(taskqueue_swi_giant, 552 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 553 } else if (was_present && !is_present) { 554 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 555 } 556 } 557 558 void 559 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 560 { 561 562 SDHCI_LOCK(slot); 563 sdhci_handle_card_present_locked(slot, is_present); 564 SDHCI_UNLOCK(slot); 565 } 566 567 static void 568 sdhci_card_poll(void *arg) 569 { 570 struct sdhci_slot *slot = arg; 571 572 sdhci_handle_card_present(slot, 573 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 574 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 575 sdhci_card_poll, slot); 576 } 577 578 int 579 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 580 { 581 uint32_t caps, freq; 582 int err; 583 584 SDHCI_LOCK_INIT(slot); 585 slot->num = num; 586 slot->bus = dev; 587 588 /* Allocate DMA tag. */ 589 err = bus_dma_tag_create(bus_get_dma_tag(dev), 590 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 591 BUS_SPACE_MAXADDR, NULL, NULL, 592 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 593 BUS_DMA_ALLOCNOW, NULL, NULL, 594 &slot->dmatag); 595 if (err != 0) { 596 device_printf(dev, "Can't create DMA tag\n"); 597 SDHCI_LOCK_DESTROY(slot); 598 return (err); 599 } 600 /* Allocate DMA memory. */ 601 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 602 BUS_DMA_NOWAIT, &slot->dmamap); 603 if (err != 0) { 604 device_printf(dev, "Can't alloc DMA memory\n"); 605 SDHCI_LOCK_DESTROY(slot); 606 return (err); 607 } 608 /* Map the memory. */ 609 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 610 (void *)slot->dmamem, DMA_BLOCK_SIZE, 611 sdhci_getaddr, &slot->paddr, 0); 612 if (err != 0 || slot->paddr == 0) { 613 device_printf(dev, "Can't load DMA memory\n"); 614 SDHCI_LOCK_DESTROY(slot); 615 if (err) 616 return (err); 617 else 618 return (EFAULT); 619 } 620 621 /* Initialize slot. */ 622 sdhci_init(slot); 623 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 624 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 625 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 626 caps = slot->caps; 627 else 628 caps = RD4(slot, SDHCI_CAPABILITIES); 629 /* Calculate base clock frequency. */ 630 if (slot->version >= SDHCI_SPEC_300) 631 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 632 SDHCI_CLOCK_BASE_SHIFT; 633 else 634 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 635 SDHCI_CLOCK_BASE_SHIFT; 636 if (freq != 0) 637 slot->max_clk = freq * 1000000; 638 /* 639 * If the frequency wasn't in the capabilities and the hardware driver 640 * hasn't already set max_clk we're probably not going to work right 641 * with an assumption, so complain about it. 642 */ 643 if (slot->max_clk == 0) { 644 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 645 device_printf(dev, "Hardware doesn't specify base clock " 646 "frequency, using %dMHz as default.\n", 647 SDHCI_DEFAULT_MAX_FREQ); 648 } 649 /* Calculate/set timeout clock frequency. */ 650 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 651 slot->timeout_clk = slot->max_clk / 1000; 652 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 653 slot->timeout_clk = 1000; 654 } else { 655 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 656 SDHCI_TIMEOUT_CLK_SHIFT; 657 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 658 slot->timeout_clk *= 1000; 659 } 660 /* 661 * If the frequency wasn't in the capabilities and the hardware driver 662 * hasn't already set timeout_clk we'll probably work okay using the 663 * max timeout, but still mention it. 664 */ 665 if (slot->timeout_clk == 0) { 666 device_printf(dev, "Hardware doesn't specify timeout clock " 667 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 668 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 669 } 670 671 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 672 slot->host.f_max = slot->max_clk; 673 slot->host.host_ocr = 0; 674 if (caps & SDHCI_CAN_VDD_330) 675 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 676 if (caps & SDHCI_CAN_VDD_300) 677 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 678 if (caps & SDHCI_CAN_VDD_180) 679 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 680 if (slot->host.host_ocr == 0) { 681 device_printf(dev, "Hardware doesn't report any " 682 "support voltages.\n"); 683 } 684 slot->host.caps = MMC_CAP_4_BIT_DATA; 685 if (caps & SDHCI_CAN_DO_8BITBUS) 686 slot->host.caps |= MMC_CAP_8_BIT_DATA; 687 if (caps & SDHCI_CAN_DO_HISPD) 688 slot->host.caps |= MMC_CAP_HSPEED; 689 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 690 slot->host.caps |= MMC_CAP_BOOT_NOACC; 691 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 692 slot->host.caps |= MMC_CAP_WAIT_WHILE_BUSY; 693 /* Decide if we have usable DMA. */ 694 if (caps & SDHCI_CAN_DO_DMA) 695 slot->opt |= SDHCI_HAVE_DMA; 696 697 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 698 slot->opt &= ~SDHCI_HAVE_DMA; 699 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 700 slot->opt |= SDHCI_HAVE_DMA; 701 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 702 slot->opt |= SDHCI_NON_REMOVABLE; 703 704 /* 705 * Use platform-provided transfer backend 706 * with PIO as a fallback mechanism 707 */ 708 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 709 slot->opt &= ~SDHCI_HAVE_DMA; 710 711 if (bootverbose || sdhci_debug) { 712 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 713 slot->max_clk / 1000000, 714 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 715 (slot->host.caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 716 ((slot->host.caps & MMC_CAP_4_BIT_DATA) ? "4bits" : 717 "1bit"), 718 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 719 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 720 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 721 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 722 sdhci_dumpregs(slot); 723 } 724 725 slot->timeout = 10; 726 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 727 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 728 "timeout", CTLFLAG_RW, &slot->timeout, 0, 729 "Maximum timeout for SDHCI transfers (in secs)"); 730 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 731 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 732 sdhci_card_task, slot); 733 callout_init(&slot->card_poll_callout, 1); 734 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 735 736 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 737 !(slot->opt & SDHCI_NON_REMOVABLE)) { 738 callout_reset(&slot->card_poll_callout, 739 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 740 } 741 742 return (0); 743 } 744 745 void 746 sdhci_start_slot(struct sdhci_slot *slot) 747 { 748 749 sdhci_card_task(slot, 0); 750 } 751 752 int 753 sdhci_cleanup_slot(struct sdhci_slot *slot) 754 { 755 device_t d; 756 757 callout_drain(&slot->timeout_callout); 758 callout_drain(&slot->card_poll_callout); 759 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 760 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 761 762 SDHCI_LOCK(slot); 763 d = slot->dev; 764 slot->dev = NULL; 765 SDHCI_UNLOCK(slot); 766 if (d != NULL) 767 device_delete_child(slot->bus, d); 768 769 SDHCI_LOCK(slot); 770 sdhci_reset(slot, SDHCI_RESET_ALL); 771 SDHCI_UNLOCK(slot); 772 bus_dmamap_unload(slot->dmatag, slot->dmamap); 773 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 774 bus_dma_tag_destroy(slot->dmatag); 775 776 SDHCI_LOCK_DESTROY(slot); 777 778 return (0); 779 } 780 781 int 782 sdhci_generic_suspend(struct sdhci_slot *slot) 783 { 784 785 sdhci_reset(slot, SDHCI_RESET_ALL); 786 787 return (0); 788 } 789 790 int 791 sdhci_generic_resume(struct sdhci_slot *slot) 792 { 793 794 sdhci_init(slot); 795 796 return (0); 797 } 798 799 uint32_t 800 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 801 { 802 803 if (slot->version >= SDHCI_SPEC_300) 804 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 805 else 806 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 807 } 808 809 bool 810 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 811 { 812 813 if (slot->opt & SDHCI_NON_REMOVABLE) 814 return true; 815 816 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 817 } 818 819 int 820 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 821 { 822 struct sdhci_slot *slot = device_get_ivars(reqdev); 823 struct mmc_ios *ios = &slot->host.ios; 824 825 SDHCI_LOCK(slot); 826 /* Do full reset on bus power down to clear from any state. */ 827 if (ios->power_mode == power_off) { 828 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 829 sdhci_init(slot); 830 } 831 /* Configure the bus. */ 832 sdhci_set_clock(slot, ios->clock); 833 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 834 if (ios->bus_width == bus_width_8) { 835 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 836 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 837 } else if (ios->bus_width == bus_width_4) { 838 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 839 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 840 } else if (ios->bus_width == bus_width_1) { 841 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 842 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 843 } else { 844 panic("Invalid bus width: %d", ios->bus_width); 845 } 846 if (ios->timing == bus_timing_hs && 847 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 848 slot->hostctrl |= SDHCI_CTRL_HISPD; 849 else 850 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 851 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 852 /* Some controllers like reset after bus changes. */ 853 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 854 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 855 856 SDHCI_UNLOCK(slot); 857 return (0); 858 } 859 860 static void 861 sdhci_req_done(struct sdhci_slot *slot) 862 { 863 struct mmc_request *req; 864 865 if (slot->req != NULL && slot->curcmd != NULL) { 866 callout_stop(&slot->timeout_callout); 867 req = slot->req; 868 slot->req = NULL; 869 slot->curcmd = NULL; 870 req->done(req); 871 } 872 } 873 874 static void 875 sdhci_timeout(void *arg) 876 { 877 struct sdhci_slot *slot = arg; 878 879 if (slot->curcmd != NULL) { 880 slot_printf(slot, " Controller timeout\n"); 881 sdhci_dumpregs(slot); 882 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 883 slot->curcmd->error = MMC_ERR_TIMEOUT; 884 sdhci_req_done(slot); 885 } else { 886 slot_printf(slot, " Spurious timeout - no active command\n"); 887 } 888 } 889 890 static void 891 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 892 { 893 uint16_t mode; 894 895 if (data == NULL) 896 return; 897 898 mode = SDHCI_TRNS_BLK_CNT_EN; 899 if (data->len > 512) 900 mode |= SDHCI_TRNS_MULTI; 901 if (data->flags & MMC_DATA_READ) 902 mode |= SDHCI_TRNS_READ; 903 if (slot->req->stop) 904 mode |= SDHCI_TRNS_ACMD12; 905 if (slot->flags & SDHCI_USE_DMA) 906 mode |= SDHCI_TRNS_DMA; 907 908 WR2(slot, SDHCI_TRANSFER_MODE, mode); 909 } 910 911 static void 912 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 913 { 914 int flags, timeout; 915 uint32_t mask; 916 917 slot->curcmd = cmd; 918 slot->cmd_done = 0; 919 920 cmd->error = MMC_ERR_NONE; 921 922 /* This flags combination is not supported by controller. */ 923 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 924 slot_printf(slot, "Unsupported response type!\n"); 925 cmd->error = MMC_ERR_FAILED; 926 sdhci_req_done(slot); 927 return; 928 } 929 930 /* 931 * Do not issue command if there is no card, clock or power. 932 * Controller will not detect timeout without clock active. 933 */ 934 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 935 slot->power == 0 || 936 slot->clock == 0) { 937 cmd->error = MMC_ERR_FAILED; 938 sdhci_req_done(slot); 939 return; 940 } 941 /* Always wait for free CMD bus. */ 942 mask = SDHCI_CMD_INHIBIT; 943 /* Wait for free DAT if we have data or busy signal. */ 944 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 945 mask |= SDHCI_DAT_INHIBIT; 946 /* We shouldn't wait for DAT for stop commands. */ 947 if (cmd == slot->req->stop) 948 mask &= ~SDHCI_DAT_INHIBIT; 949 /* 950 * Wait for bus no more then 250 ms. Typically there will be no wait 951 * here at all, but when writing a crash dump we may be bypassing the 952 * host platform's interrupt handler, and in some cases that handler 953 * may be working around hardware quirks such as not respecting r1b 954 * busy indications. In those cases, this wait-loop serves the purpose 955 * of waiting for the prior command and data transfers to be done, and 956 * SD cards are allowed to take up to 250ms for write and erase ops. 957 * (It's usually more like 20-30ms in the real world.) 958 */ 959 timeout = 250; 960 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 961 if (timeout == 0) { 962 slot_printf(slot, "Controller never released " 963 "inhibit bit(s).\n"); 964 sdhci_dumpregs(slot); 965 cmd->error = MMC_ERR_FAILED; 966 sdhci_req_done(slot); 967 return; 968 } 969 timeout--; 970 DELAY(1000); 971 } 972 973 /* Prepare command flags. */ 974 if (!(cmd->flags & MMC_RSP_PRESENT)) 975 flags = SDHCI_CMD_RESP_NONE; 976 else if (cmd->flags & MMC_RSP_136) 977 flags = SDHCI_CMD_RESP_LONG; 978 else if (cmd->flags & MMC_RSP_BUSY) 979 flags = SDHCI_CMD_RESP_SHORT_BUSY; 980 else 981 flags = SDHCI_CMD_RESP_SHORT; 982 if (cmd->flags & MMC_RSP_CRC) 983 flags |= SDHCI_CMD_CRC; 984 if (cmd->flags & MMC_RSP_OPCODE) 985 flags |= SDHCI_CMD_INDEX; 986 if (cmd->data) 987 flags |= SDHCI_CMD_DATA; 988 if (cmd->opcode == MMC_STOP_TRANSMISSION) 989 flags |= SDHCI_CMD_TYPE_ABORT; 990 /* Prepare data. */ 991 sdhci_start_data(slot, cmd->data); 992 /* 993 * Interrupt aggregation: To reduce total number of interrupts 994 * group response interrupt with data interrupt when possible. 995 * If there going to be data interrupt, mask response one. 996 */ 997 if (slot->data_done == 0) { 998 WR4(slot, SDHCI_SIGNAL_ENABLE, 999 slot->intmask &= ~SDHCI_INT_RESPONSE); 1000 } 1001 /* Set command argument. */ 1002 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1003 /* Set data transfer mode. */ 1004 sdhci_set_transfer_mode(slot, cmd->data); 1005 /* Start command. */ 1006 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1007 /* Start timeout callout. */ 1008 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1009 sdhci_timeout, slot); 1010 } 1011 1012 static void 1013 sdhci_finish_command(struct sdhci_slot *slot) 1014 { 1015 int i; 1016 uint32_t val; 1017 uint8_t extra; 1018 1019 slot->cmd_done = 1; 1020 /* 1021 * Interrupt aggregation: Restore command interrupt. 1022 * Main restore point for the case when command interrupt 1023 * happened first. 1024 */ 1025 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1026 /* In case of error - reset host and return. */ 1027 if (slot->curcmd->error) { 1028 sdhci_reset(slot, SDHCI_RESET_CMD); 1029 sdhci_reset(slot, SDHCI_RESET_DATA); 1030 sdhci_start(slot); 1031 return; 1032 } 1033 /* If command has response - fetch it. */ 1034 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1035 if (slot->curcmd->flags & MMC_RSP_136) { 1036 /* CRC is stripped so we need one byte shift. */ 1037 extra = 0; 1038 for (i = 0; i < 4; i++) { 1039 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1040 if (slot->quirks & 1041 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1042 slot->curcmd->resp[3 - i] = val; 1043 else { 1044 slot->curcmd->resp[3 - i] = 1045 (val << 8) | extra; 1046 extra = val >> 24; 1047 } 1048 } 1049 } else 1050 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1051 } 1052 /* If data ready - finish. */ 1053 if (slot->data_done) 1054 sdhci_start(slot); 1055 } 1056 1057 static void 1058 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1059 { 1060 uint32_t target_timeout, current_timeout; 1061 uint8_t div; 1062 1063 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1064 slot->data_done = 1; 1065 return; 1066 } 1067 1068 slot->data_done = 0; 1069 1070 /* Calculate and set data timeout.*/ 1071 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1072 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1073 div = 0xE; 1074 } else { 1075 target_timeout = 1000000; 1076 div = 0; 1077 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1078 while (current_timeout < target_timeout && div < 0xE) { 1079 ++div; 1080 current_timeout <<= 1; 1081 } 1082 /* Compensate for an off-by-one error in the CaFe chip.*/ 1083 if (div < 0xE && 1084 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1085 ++div; 1086 } 1087 } 1088 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1089 1090 if (data == NULL) 1091 return; 1092 1093 /* Use DMA if possible. */ 1094 if ((slot->opt & SDHCI_HAVE_DMA)) 1095 slot->flags |= SDHCI_USE_DMA; 1096 /* If data is small, broken DMA may return zeroes instead of data, */ 1097 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1098 (data->len <= 512)) 1099 slot->flags &= ~SDHCI_USE_DMA; 1100 /* Some controllers require even block sizes. */ 1101 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1102 ((data->len) & 0x3)) 1103 slot->flags &= ~SDHCI_USE_DMA; 1104 /* Load DMA buffer. */ 1105 if (slot->flags & SDHCI_USE_DMA) { 1106 if (data->flags & MMC_DATA_READ) 1107 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1108 BUS_DMASYNC_PREREAD); 1109 else { 1110 memcpy(slot->dmamem, data->data, 1111 (data->len < DMA_BLOCK_SIZE) ? 1112 data->len : DMA_BLOCK_SIZE); 1113 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1114 BUS_DMASYNC_PREWRITE); 1115 } 1116 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1117 /* Interrupt aggregation: Mask border interrupt 1118 * for the last page and unmask else. */ 1119 if (data->len == DMA_BLOCK_SIZE) 1120 slot->intmask &= ~SDHCI_INT_DMA_END; 1121 else 1122 slot->intmask |= SDHCI_INT_DMA_END; 1123 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1124 } 1125 /* Current data offset for both PIO and DMA. */ 1126 slot->offset = 0; 1127 /* Set block size and request IRQ on 4K border. */ 1128 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1129 (data->len < 512) ? data->len : 512)); 1130 /* Set block count. */ 1131 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1132 } 1133 1134 void 1135 sdhci_finish_data(struct sdhci_slot *slot) 1136 { 1137 struct mmc_data *data = slot->curcmd->data; 1138 size_t left; 1139 1140 /* Interrupt aggregation: Restore command interrupt. 1141 * Auxiliary restore point for the case when data interrupt 1142 * happened first. */ 1143 if (!slot->cmd_done) { 1144 WR4(slot, SDHCI_SIGNAL_ENABLE, 1145 slot->intmask |= SDHCI_INT_RESPONSE); 1146 } 1147 /* Unload rest of data from DMA buffer. */ 1148 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1149 if (data->flags & MMC_DATA_READ) { 1150 left = data->len - slot->offset; 1151 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1152 BUS_DMASYNC_POSTREAD); 1153 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1154 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1155 } else 1156 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1157 BUS_DMASYNC_POSTWRITE); 1158 } 1159 slot->data_done = 1; 1160 /* If there was error - reset the host. */ 1161 if (slot->curcmd->error) { 1162 sdhci_reset(slot, SDHCI_RESET_CMD); 1163 sdhci_reset(slot, SDHCI_RESET_DATA); 1164 sdhci_start(slot); 1165 return; 1166 } 1167 /* If we already have command response - finish. */ 1168 if (slot->cmd_done) 1169 sdhci_start(slot); 1170 } 1171 1172 static void 1173 sdhci_start(struct sdhci_slot *slot) 1174 { 1175 struct mmc_request *req; 1176 1177 req = slot->req; 1178 if (req == NULL) 1179 return; 1180 1181 if (!(slot->flags & CMD_STARTED)) { 1182 slot->flags |= CMD_STARTED; 1183 sdhci_start_command(slot, req->cmd); 1184 return; 1185 } 1186 /* We don't need this until using Auto-CMD12 feature 1187 if (!(slot->flags & STOP_STARTED) && req->stop) { 1188 slot->flags |= STOP_STARTED; 1189 sdhci_start_command(slot, req->stop); 1190 return; 1191 } 1192 */ 1193 if (sdhci_debug > 1) 1194 slot_printf(slot, "result: %d\n", req->cmd->error); 1195 if (!req->cmd->error && 1196 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1197 sdhci_reset(slot, SDHCI_RESET_CMD); 1198 sdhci_reset(slot, SDHCI_RESET_DATA); 1199 } 1200 1201 sdhci_req_done(slot); 1202 } 1203 1204 int 1205 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1206 struct mmc_request *req) 1207 { 1208 struct sdhci_slot *slot = device_get_ivars(reqdev); 1209 1210 SDHCI_LOCK(slot); 1211 if (slot->req != NULL) { 1212 SDHCI_UNLOCK(slot); 1213 return (EBUSY); 1214 } 1215 if (sdhci_debug > 1) { 1216 slot_printf(slot, 1217 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1218 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1219 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1220 (req->cmd->data)?req->cmd->data->flags:0); 1221 } 1222 slot->req = req; 1223 slot->flags = 0; 1224 sdhci_start(slot); 1225 SDHCI_UNLOCK(slot); 1226 if (dumping) { 1227 while (slot->req != NULL) { 1228 sdhci_generic_intr(slot); 1229 DELAY(10); 1230 } 1231 } 1232 return (0); 1233 } 1234 1235 int 1236 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1237 { 1238 struct sdhci_slot *slot = device_get_ivars(reqdev); 1239 uint32_t val; 1240 1241 SDHCI_LOCK(slot); 1242 val = RD4(slot, SDHCI_PRESENT_STATE); 1243 SDHCI_UNLOCK(slot); 1244 return (!(val & SDHCI_WRITE_PROTECT)); 1245 } 1246 1247 int 1248 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1249 { 1250 struct sdhci_slot *slot = device_get_ivars(reqdev); 1251 int err = 0; 1252 1253 SDHCI_LOCK(slot); 1254 while (slot->bus_busy) 1255 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1256 slot->bus_busy++; 1257 /* Activate led. */ 1258 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1259 SDHCI_UNLOCK(slot); 1260 return (err); 1261 } 1262 1263 int 1264 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1265 { 1266 struct sdhci_slot *slot = device_get_ivars(reqdev); 1267 1268 SDHCI_LOCK(slot); 1269 /* Deactivate led. */ 1270 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1271 slot->bus_busy--; 1272 SDHCI_UNLOCK(slot); 1273 wakeup(slot); 1274 return (0); 1275 } 1276 1277 static void 1278 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1279 { 1280 1281 if (!slot->curcmd) { 1282 slot_printf(slot, "Got command interrupt 0x%08x, but " 1283 "there is no active command.\n", intmask); 1284 sdhci_dumpregs(slot); 1285 return; 1286 } 1287 if (intmask & SDHCI_INT_TIMEOUT) 1288 slot->curcmd->error = MMC_ERR_TIMEOUT; 1289 else if (intmask & SDHCI_INT_CRC) 1290 slot->curcmd->error = MMC_ERR_BADCRC; 1291 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1292 slot->curcmd->error = MMC_ERR_FIFO; 1293 1294 sdhci_finish_command(slot); 1295 } 1296 1297 static void 1298 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1299 { 1300 struct mmc_data *data; 1301 size_t left; 1302 1303 if (!slot->curcmd) { 1304 slot_printf(slot, "Got data interrupt 0x%08x, but " 1305 "there is no active command.\n", intmask); 1306 sdhci_dumpregs(slot); 1307 return; 1308 } 1309 if (slot->curcmd->data == NULL && 1310 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1311 slot_printf(slot, "Got data interrupt 0x%08x, but " 1312 "there is no active data operation.\n", 1313 intmask); 1314 sdhci_dumpregs(slot); 1315 return; 1316 } 1317 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1318 slot->curcmd->error = MMC_ERR_TIMEOUT; 1319 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1320 slot->curcmd->error = MMC_ERR_BADCRC; 1321 if (slot->curcmd->data == NULL && 1322 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1323 SDHCI_INT_DMA_END))) { 1324 slot_printf(slot, "Got data interrupt 0x%08x, but " 1325 "there is busy-only command.\n", intmask); 1326 sdhci_dumpregs(slot); 1327 slot->curcmd->error = MMC_ERR_INVALID; 1328 } 1329 if (slot->curcmd->error) { 1330 /* No need to continue after any error. */ 1331 goto done; 1332 } 1333 1334 /* Handle PIO interrupt. */ 1335 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1336 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1337 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1338 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1339 &intmask); 1340 slot->flags |= PLATFORM_DATA_STARTED; 1341 } else 1342 sdhci_transfer_pio(slot); 1343 } 1344 /* Handle DMA border. */ 1345 if (intmask & SDHCI_INT_DMA_END) { 1346 data = slot->curcmd->data; 1347 1348 /* Unload DMA buffer... */ 1349 left = data->len - slot->offset; 1350 if (data->flags & MMC_DATA_READ) { 1351 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1352 BUS_DMASYNC_POSTREAD); 1353 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1354 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1355 } else { 1356 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1357 BUS_DMASYNC_POSTWRITE); 1358 } 1359 /* ... and reload it again. */ 1360 slot->offset += DMA_BLOCK_SIZE; 1361 left = data->len - slot->offset; 1362 if (data->flags & MMC_DATA_READ) { 1363 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1364 BUS_DMASYNC_PREREAD); 1365 } else { 1366 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1367 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1368 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1369 BUS_DMASYNC_PREWRITE); 1370 } 1371 /* Interrupt aggregation: Mask border interrupt 1372 * for the last page. */ 1373 if (left == DMA_BLOCK_SIZE) { 1374 slot->intmask &= ~SDHCI_INT_DMA_END; 1375 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1376 } 1377 /* Restart DMA. */ 1378 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1379 } 1380 /* We have got all data. */ 1381 if (intmask & SDHCI_INT_DATA_END) { 1382 if (slot->flags & PLATFORM_DATA_STARTED) { 1383 slot->flags &= ~PLATFORM_DATA_STARTED; 1384 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1385 } else 1386 sdhci_finish_data(slot); 1387 } 1388 done: 1389 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1390 if (slot->flags & PLATFORM_DATA_STARTED) { 1391 slot->flags &= ~PLATFORM_DATA_STARTED; 1392 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1393 } else 1394 sdhci_finish_data(slot); 1395 } 1396 } 1397 1398 static void 1399 sdhci_acmd_irq(struct sdhci_slot *slot) 1400 { 1401 uint16_t err; 1402 1403 err = RD4(slot, SDHCI_ACMD12_ERR); 1404 if (!slot->curcmd) { 1405 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1406 "there is no active command.\n", err); 1407 sdhci_dumpregs(slot); 1408 return; 1409 } 1410 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1411 sdhci_reset(slot, SDHCI_RESET_CMD); 1412 } 1413 1414 void 1415 sdhci_generic_intr(struct sdhci_slot *slot) 1416 { 1417 uint32_t intmask, present; 1418 1419 SDHCI_LOCK(slot); 1420 /* Read slot interrupt status. */ 1421 intmask = RD4(slot, SDHCI_INT_STATUS); 1422 if (intmask == 0 || intmask == 0xffffffff) { 1423 SDHCI_UNLOCK(slot); 1424 return; 1425 } 1426 if (sdhci_debug > 2) 1427 slot_printf(slot, "Interrupt %#x\n", intmask); 1428 1429 /* Handle card presence interrupts. */ 1430 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1431 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1432 slot->intmask &= 1433 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1434 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1435 SDHCI_INT_CARD_INSERT; 1436 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1437 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1438 WR4(slot, SDHCI_INT_STATUS, intmask & 1439 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1440 sdhci_handle_card_present_locked(slot, present); 1441 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1442 } 1443 /* Handle command interrupts. */ 1444 if (intmask & SDHCI_INT_CMD_MASK) { 1445 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1446 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1447 } 1448 /* Handle data interrupts. */ 1449 if (intmask & SDHCI_INT_DATA_MASK) { 1450 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1451 /* Don't call data_irq in case of errored command. */ 1452 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1453 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1454 } 1455 /* Handle AutoCMD12 error interrupt. */ 1456 if (intmask & SDHCI_INT_ACMD12ERR) { 1457 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1458 sdhci_acmd_irq(slot); 1459 } 1460 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1461 intmask &= ~SDHCI_INT_ACMD12ERR; 1462 intmask &= ~SDHCI_INT_ERROR; 1463 /* Handle bus power interrupt. */ 1464 if (intmask & SDHCI_INT_BUS_POWER) { 1465 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1466 slot_printf(slot, 1467 "Card is consuming too much power!\n"); 1468 intmask &= ~SDHCI_INT_BUS_POWER; 1469 } 1470 /* The rest is unknown. */ 1471 if (intmask) { 1472 WR4(slot, SDHCI_INT_STATUS, intmask); 1473 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1474 intmask); 1475 sdhci_dumpregs(slot); 1476 } 1477 1478 SDHCI_UNLOCK(slot); 1479 } 1480 1481 int 1482 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1483 uintptr_t *result) 1484 { 1485 struct sdhci_slot *slot = device_get_ivars(child); 1486 1487 switch (which) { 1488 default: 1489 return (EINVAL); 1490 case MMCBR_IVAR_BUS_MODE: 1491 *result = slot->host.ios.bus_mode; 1492 break; 1493 case MMCBR_IVAR_BUS_WIDTH: 1494 *result = slot->host.ios.bus_width; 1495 break; 1496 case MMCBR_IVAR_CHIP_SELECT: 1497 *result = slot->host.ios.chip_select; 1498 break; 1499 case MMCBR_IVAR_CLOCK: 1500 *result = slot->host.ios.clock; 1501 break; 1502 case MMCBR_IVAR_F_MIN: 1503 *result = slot->host.f_min; 1504 break; 1505 case MMCBR_IVAR_F_MAX: 1506 *result = slot->host.f_max; 1507 break; 1508 case MMCBR_IVAR_HOST_OCR: 1509 *result = slot->host.host_ocr; 1510 break; 1511 case MMCBR_IVAR_MODE: 1512 *result = slot->host.mode; 1513 break; 1514 case MMCBR_IVAR_OCR: 1515 *result = slot->host.ocr; 1516 break; 1517 case MMCBR_IVAR_POWER_MODE: 1518 *result = slot->host.ios.power_mode; 1519 break; 1520 case MMCBR_IVAR_VDD: 1521 *result = slot->host.ios.vdd; 1522 break; 1523 case MMCBR_IVAR_CAPS: 1524 *result = slot->host.caps; 1525 break; 1526 case MMCBR_IVAR_TIMING: 1527 *result = slot->host.ios.timing; 1528 break; 1529 case MMCBR_IVAR_MAX_DATA: 1530 *result = 65535; 1531 break; 1532 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1533 /* 1534 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1535 */ 1536 *result = 1000000; 1537 break; 1538 } 1539 return (0); 1540 } 1541 1542 int 1543 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1544 uintptr_t value) 1545 { 1546 struct sdhci_slot *slot = device_get_ivars(child); 1547 uint32_t clock, max_clock; 1548 int i; 1549 1550 switch (which) { 1551 default: 1552 return (EINVAL); 1553 case MMCBR_IVAR_BUS_MODE: 1554 slot->host.ios.bus_mode = value; 1555 break; 1556 case MMCBR_IVAR_BUS_WIDTH: 1557 slot->host.ios.bus_width = value; 1558 break; 1559 case MMCBR_IVAR_CHIP_SELECT: 1560 slot->host.ios.chip_select = value; 1561 break; 1562 case MMCBR_IVAR_CLOCK: 1563 if (value > 0) { 1564 max_clock = slot->max_clk; 1565 clock = max_clock; 1566 1567 if (slot->version < SDHCI_SPEC_300) { 1568 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1569 i <<= 1) { 1570 if (clock <= value) 1571 break; 1572 clock >>= 1; 1573 } 1574 } else { 1575 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1576 i += 2) { 1577 if (clock <= value) 1578 break; 1579 clock = max_clock / (i + 2); 1580 } 1581 } 1582 1583 slot->host.ios.clock = clock; 1584 } else 1585 slot->host.ios.clock = 0; 1586 break; 1587 case MMCBR_IVAR_MODE: 1588 slot->host.mode = value; 1589 break; 1590 case MMCBR_IVAR_OCR: 1591 slot->host.ocr = value; 1592 break; 1593 case MMCBR_IVAR_POWER_MODE: 1594 slot->host.ios.power_mode = value; 1595 break; 1596 case MMCBR_IVAR_VDD: 1597 slot->host.ios.vdd = value; 1598 break; 1599 case MMCBR_IVAR_TIMING: 1600 slot->host.ios.timing = value; 1601 break; 1602 case MMCBR_IVAR_CAPS: 1603 case MMCBR_IVAR_HOST_OCR: 1604 case MMCBR_IVAR_F_MIN: 1605 case MMCBR_IVAR_F_MAX: 1606 case MMCBR_IVAR_MAX_DATA: 1607 return (EINVAL); 1608 } 1609 return (0); 1610 } 1611 1612 MODULE_VERSION(sdhci, 1); 1613