1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/kobj.h> 39 #include <sys/libkern.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/resource.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #include <dev/mmc/bridge.h> 54 #include <dev/mmc/mmcreg.h> 55 #include <dev/mmc/mmcbrvar.h> 56 57 #include <dev/sdhci/sdhci.h> 58 59 #include <cam/cam.h> 60 #include <cam/cam_ccb.h> 61 #include <cam/cam_debug.h> 62 #include <cam/cam_sim.h> 63 #include <cam/cam_xpt_sim.h> 64 65 #include "mmcbr_if.h" 66 #include "sdhci_if.h" 67 68 #include "opt_mmccam.h" 69 70 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 71 72 static int sdhci_debug = 0; 73 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 74 "Debug level"); 75 u_int sdhci_quirk_clear = 0; 76 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 77 0, "Mask of quirks to clear"); 78 u_int sdhci_quirk_set = 0; 79 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 80 "Mask of quirks to set"); 81 82 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 83 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 84 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 85 #define RD_MULTI_4(slot, off, ptr, count) \ 86 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 87 88 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 89 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 90 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 91 #define WR_MULTI_4(slot, off, ptr, count) \ 92 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 93 94 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err); 95 static void sdhci_card_poll(void *arg); 96 static void sdhci_card_task(void *arg, int pending); 97 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask); 98 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask); 99 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 100 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot, 101 bool is_present); 102 static void sdhci_finish_command(struct sdhci_slot *slot); 103 static void sdhci_init(struct sdhci_slot *slot); 104 static void sdhci_read_block_pio(struct sdhci_slot *slot); 105 static void sdhci_req_done(struct sdhci_slot *slot); 106 static void sdhci_req_wakeup(struct mmc_request *req); 107 static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask); 108 static void sdhci_retune(void *arg); 109 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 110 static void sdhci_set_power(struct sdhci_slot *slot, u_char power); 111 static void sdhci_set_transfer_mode(struct sdhci_slot *slot, 112 const struct mmc_data *data); 113 static void sdhci_start(struct sdhci_slot *slot); 114 static void sdhci_timeout(void *arg); 115 static void sdhci_start_command(struct sdhci_slot *slot, 116 struct mmc_command *cmd); 117 static void sdhci_start_data(struct sdhci_slot *slot, 118 const struct mmc_data *data); 119 static void sdhci_write_block_pio(struct sdhci_slot *slot); 120 static void sdhci_transfer_pio(struct sdhci_slot *slot); 121 122 #ifdef MMCCAM 123 /* CAM-related */ 124 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 125 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 126 int proposed_clock); 127 static void sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb); 128 static void sdhci_cam_poll(struct cam_sim *sim); 129 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 130 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 131 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 132 #endif 133 134 /* helper routines */ 135 static int sdhci_dma_alloc(struct sdhci_slot *slot); 136 static void sdhci_dma_free(struct sdhci_slot *slot); 137 static void sdhci_dumpregs(struct sdhci_slot *slot); 138 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 139 int error); 140 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 141 __printflike(2, 3); 142 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot); 143 144 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 145 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 146 #define SDHCI_LOCK_INIT(_slot) \ 147 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 148 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 149 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 150 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 151 152 #define SDHCI_DEFAULT_MAX_FREQ 50 153 154 #define SDHCI_200_MAX_DIVIDER 256 155 #define SDHCI_300_MAX_DIVIDER 2046 156 157 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 158 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 159 160 /* 161 * Broadcom BCM577xx Controller Constants 162 */ 163 /* Maximum divider supported by the default clock source. */ 164 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 165 /* Alternative clock's base frequency. */ 166 #define BCM577XX_ALT_CLOCK_BASE 63000000 167 168 #define BCM577XX_HOST_CONTROL 0x198 169 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 170 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 171 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 172 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 173 174 static void 175 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 176 { 177 178 if (error != 0) { 179 printf("getaddr: error %d\n", error); 180 return; 181 } 182 *(bus_addr_t *)arg = segs[0].ds_addr; 183 } 184 185 static int 186 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) 187 { 188 va_list ap; 189 int retval; 190 191 retval = printf("%s-slot%d: ", 192 device_get_nameunit(slot->bus), slot->num); 193 194 va_start(ap, fmt); 195 retval += vprintf(fmt, ap); 196 va_end(ap); 197 return (retval); 198 } 199 200 static void 201 sdhci_dumpregs(struct sdhci_slot *slot) 202 { 203 204 slot_printf(slot, 205 "============== REGISTER DUMP ==============\n"); 206 207 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 208 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 209 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 210 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 211 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 212 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 213 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 214 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 215 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 216 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 217 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 218 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 219 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 220 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 221 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 222 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 223 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 224 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 225 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 226 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 227 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 228 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 229 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 230 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 231 232 slot_printf(slot, 233 "===========================================\n"); 234 } 235 236 static void 237 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 238 { 239 int timeout; 240 uint32_t clock; 241 242 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 243 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 244 return; 245 } 246 247 /* Some controllers need this kick or reset won't work. */ 248 if ((mask & SDHCI_RESET_ALL) == 0 && 249 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 250 /* This is to force an update */ 251 clock = slot->clock; 252 slot->clock = 0; 253 sdhci_set_clock(slot, clock); 254 } 255 256 if (mask & SDHCI_RESET_ALL) { 257 slot->clock = 0; 258 slot->power = 0; 259 } 260 261 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 262 263 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 264 /* 265 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 266 * specification. The reset bit has internal propagation delay, 267 * so a fast read after write returns 0 even if reset process is 268 * in progress. The workaround is to poll for 1 before polling 269 * for 0. In the worst case, if we miss seeing it asserted the 270 * time we spent waiting is enough to ensure the reset finishes. 271 */ 272 timeout = 10000; 273 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 274 if (timeout <= 0) 275 break; 276 timeout--; 277 DELAY(1); 278 } 279 } 280 281 /* Wait max 100 ms */ 282 timeout = 10000; 283 /* Controller clears the bits when it's done */ 284 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 285 if (timeout <= 0) { 286 slot_printf(slot, "Reset 0x%x never completed.\n", 287 mask); 288 sdhci_dumpregs(slot); 289 return; 290 } 291 timeout--; 292 DELAY(10); 293 } 294 } 295 296 static uint32_t 297 sdhci_tuning_intmask(const struct sdhci_slot *slot) 298 { 299 uint32_t intmask; 300 301 intmask = 0; 302 if (slot->opt & SDHCI_TUNING_ENABLED) { 303 intmask |= SDHCI_INT_TUNEERR; 304 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 305 slot->retune_mode == SDHCI_RETUNE_MODE_3) 306 intmask |= SDHCI_INT_RETUNE; 307 } 308 return (intmask); 309 } 310 311 static void 312 sdhci_init(struct sdhci_slot *slot) 313 { 314 315 sdhci_reset(slot, SDHCI_RESET_ALL); 316 317 /* Enable interrupts. */ 318 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 319 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 320 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 321 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 322 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 323 SDHCI_INT_ACMD12ERR; 324 325 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 326 !(slot->opt & SDHCI_NON_REMOVABLE)) { 327 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 328 } 329 330 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 331 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 332 } 333 334 static void 335 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 336 { 337 uint32_t clk_base; 338 uint32_t clk_sel; 339 uint32_t res; 340 uint16_t clk; 341 uint16_t div; 342 int timeout; 343 344 if (clock == slot->clock) 345 return; 346 slot->clock = clock; 347 348 /* Turn off the clock. */ 349 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 350 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 351 /* If no clock requested - leave it so. */ 352 if (clock == 0) 353 return; 354 355 /* Determine the clock base frequency */ 356 clk_base = slot->max_clk; 357 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 358 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 359 BCM577XX_CTRL_CLKSEL_MASK; 360 361 /* 362 * Select clock source appropriate for the requested frequency. 363 */ 364 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 365 clk_base = BCM577XX_ALT_CLOCK_BASE; 366 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 367 BCM577XX_CTRL_CLKSEL_SHIFT); 368 } else { 369 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 370 BCM577XX_CTRL_CLKSEL_SHIFT); 371 } 372 373 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 374 } 375 376 /* Recalculate timeout clock frequency based on the new sd clock. */ 377 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 378 slot->timeout_clk = slot->clock / 1000; 379 380 if (slot->version < SDHCI_SPEC_300) { 381 /* Looking for highest freq <= clock. */ 382 res = clk_base; 383 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 384 if (res <= clock) 385 break; 386 res >>= 1; 387 } 388 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 389 div >>= 1; 390 } else { 391 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 392 if (clock >= clk_base) 393 div = 0; 394 else { 395 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 396 if ((clk_base / div) <= clock) 397 break; 398 } 399 } 400 div >>= 1; 401 } 402 403 if (bootverbose || sdhci_debug) 404 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 405 div, clock, clk_base); 406 407 /* Now we have got divider, set it. */ 408 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 409 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 410 << SDHCI_DIVIDER_HI_SHIFT; 411 412 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 413 /* Enable clock. */ 414 clk |= SDHCI_CLOCK_INT_EN; 415 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 416 /* Wait up to 10 ms until it stabilize. */ 417 timeout = 10; 418 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 419 & SDHCI_CLOCK_INT_STABLE)) { 420 if (timeout == 0) { 421 slot_printf(slot, 422 "Internal clock never stabilised.\n"); 423 sdhci_dumpregs(slot); 424 return; 425 } 426 timeout--; 427 DELAY(1000); 428 } 429 /* Pass clock signal to the bus. */ 430 clk |= SDHCI_CLOCK_CARD_EN; 431 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 432 } 433 434 static void 435 sdhci_set_power(struct sdhci_slot *slot, u_char power) 436 { 437 int i; 438 uint8_t pwr; 439 440 if (slot->power == power) 441 return; 442 443 slot->power = power; 444 445 /* Turn off the power. */ 446 pwr = 0; 447 WR1(slot, SDHCI_POWER_CONTROL, pwr); 448 /* If power down requested - leave it so. */ 449 if (power == 0) 450 return; 451 /* Set voltage. */ 452 switch (1 << power) { 453 case MMC_OCR_LOW_VOLTAGE: 454 pwr |= SDHCI_POWER_180; 455 break; 456 case MMC_OCR_290_300: 457 case MMC_OCR_300_310: 458 pwr |= SDHCI_POWER_300; 459 break; 460 case MMC_OCR_320_330: 461 case MMC_OCR_330_340: 462 pwr |= SDHCI_POWER_330; 463 break; 464 } 465 WR1(slot, SDHCI_POWER_CONTROL, pwr); 466 /* 467 * Turn on VDD1 power. Note that at least some Intel controllers can 468 * fail to enable bus power on the first try after transiting from D3 469 * to D0, so we give them up to 2 ms. 470 */ 471 pwr |= SDHCI_POWER_ON; 472 for (i = 0; i < 20; i++) { 473 WR1(slot, SDHCI_POWER_CONTROL, pwr); 474 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 475 break; 476 DELAY(100); 477 } 478 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 479 slot_printf(slot, "Bus power failed to enable"); 480 481 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 482 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 483 DELAY(10); 484 WR1(slot, SDHCI_POWER_CONTROL, pwr); 485 DELAY(300); 486 } 487 } 488 489 static void 490 sdhci_read_block_pio(struct sdhci_slot *slot) 491 { 492 uint32_t data; 493 char *buffer; 494 size_t left; 495 496 buffer = slot->curcmd->data->data; 497 buffer += slot->offset; 498 /* Transfer one block at a time. */ 499 #ifdef MMCCAM 500 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) 501 left = min(slot->curcmd->data->block_size, 502 slot->curcmd->data->len - slot->offset); 503 else 504 #endif 505 left = min(512, slot->curcmd->data->len - slot->offset); 506 slot->offset += left; 507 508 /* If we are too fast, broken controllers return zeroes. */ 509 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 510 DELAY(10); 511 /* Handle unaligned and aligned buffer cases. */ 512 if ((intptr_t)buffer & 3) { 513 while (left > 3) { 514 data = RD4(slot, SDHCI_BUFFER); 515 buffer[0] = data; 516 buffer[1] = (data >> 8); 517 buffer[2] = (data >> 16); 518 buffer[3] = (data >> 24); 519 buffer += 4; 520 left -= 4; 521 } 522 } else { 523 RD_MULTI_4(slot, SDHCI_BUFFER, 524 (uint32_t *)buffer, left >> 2); 525 left &= 3; 526 } 527 /* Handle uneven size case. */ 528 if (left > 0) { 529 data = RD4(slot, SDHCI_BUFFER); 530 while (left > 0) { 531 *(buffer++) = data; 532 data >>= 8; 533 left--; 534 } 535 } 536 } 537 538 static void 539 sdhci_write_block_pio(struct sdhci_slot *slot) 540 { 541 uint32_t data = 0; 542 char *buffer; 543 size_t left; 544 545 buffer = slot->curcmd->data->data; 546 buffer += slot->offset; 547 /* Transfer one block at a time. */ 548 #ifdef MMCCAM 549 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) { 550 left = min(slot->curcmd->data->block_size, 551 slot->curcmd->data->len - slot->offset); 552 } else 553 #endif 554 left = min(512, slot->curcmd->data->len - slot->offset); 555 slot->offset += left; 556 557 /* Handle unaligned and aligned buffer cases. */ 558 if ((intptr_t)buffer & 3) { 559 while (left > 3) { 560 data = buffer[0] + 561 (buffer[1] << 8) + 562 (buffer[2] << 16) + 563 (buffer[3] << 24); 564 left -= 4; 565 buffer += 4; 566 WR4(slot, SDHCI_BUFFER, data); 567 } 568 } else { 569 WR_MULTI_4(slot, SDHCI_BUFFER, 570 (uint32_t *)buffer, left >> 2); 571 left &= 3; 572 } 573 /* Handle uneven size case. */ 574 if (left > 0) { 575 while (left > 0) { 576 data <<= 8; 577 data += *(buffer++); 578 left--; 579 } 580 WR4(slot, SDHCI_BUFFER, data); 581 } 582 } 583 584 static void 585 sdhci_transfer_pio(struct sdhci_slot *slot) 586 { 587 588 /* Read as many blocks as possible. */ 589 if (slot->curcmd->data->flags & MMC_DATA_READ) { 590 while (RD4(slot, SDHCI_PRESENT_STATE) & 591 SDHCI_DATA_AVAILABLE) { 592 sdhci_read_block_pio(slot); 593 if (slot->offset >= slot->curcmd->data->len) 594 break; 595 } 596 } else { 597 while (RD4(slot, SDHCI_PRESENT_STATE) & 598 SDHCI_SPACE_AVAILABLE) { 599 sdhci_write_block_pio(slot); 600 if (slot->offset >= slot->curcmd->data->len) 601 break; 602 } 603 } 604 } 605 606 static void 607 sdhci_card_task(void *arg, int pending __unused) 608 { 609 struct sdhci_slot *slot = arg; 610 device_t d; 611 612 SDHCI_LOCK(slot); 613 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 614 #ifdef MMCCAM 615 if (slot->card_present == 0) { 616 #else 617 if (slot->dev == NULL) { 618 #endif 619 /* If card is present - attach mmc bus. */ 620 if (bootverbose || sdhci_debug) 621 slot_printf(slot, "Card inserted\n"); 622 #ifdef MMCCAM 623 slot->card_present = 1; 624 union ccb *ccb; 625 uint32_t pathid; 626 pathid = cam_sim_path(slot->sim); 627 ccb = xpt_alloc_ccb_nowait(); 628 if (ccb == NULL) { 629 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 630 SDHCI_UNLOCK(slot); 631 return; 632 } 633 634 /* 635 * We create a rescan request for BUS:0:0, since the card 636 * will be at lun 0. 637 */ 638 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 639 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 640 slot_printf(slot, "Unable to create path for rescan\n"); 641 SDHCI_UNLOCK(slot); 642 xpt_free_ccb(ccb); 643 return; 644 } 645 SDHCI_UNLOCK(slot); 646 xpt_rescan(ccb); 647 #else 648 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 649 SDHCI_UNLOCK(slot); 650 if (d) { 651 device_set_ivars(d, slot); 652 (void)device_probe_and_attach(d); 653 } 654 #endif 655 } else 656 SDHCI_UNLOCK(slot); 657 } else { 658 #ifdef MMCCAM 659 if (slot->card_present == 1) { 660 #else 661 if (slot->dev != NULL) { 662 #endif 663 /* If no card present - detach mmc bus. */ 664 if (bootverbose || sdhci_debug) 665 slot_printf(slot, "Card removed\n"); 666 d = slot->dev; 667 slot->dev = NULL; 668 #ifdef MMCCAM 669 slot->card_present = 0; 670 union ccb *ccb; 671 uint32_t pathid; 672 pathid = cam_sim_path(slot->sim); 673 ccb = xpt_alloc_ccb_nowait(); 674 if (ccb == NULL) { 675 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 676 SDHCI_UNLOCK(slot); 677 return; 678 } 679 680 /* 681 * We create a rescan request for BUS:0:0, since the card 682 * will be at lun 0. 683 */ 684 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 685 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 686 slot_printf(slot, "Unable to create path for rescan\n"); 687 SDHCI_UNLOCK(slot); 688 xpt_free_ccb(ccb); 689 return; 690 } 691 SDHCI_UNLOCK(slot); 692 xpt_rescan(ccb); 693 #else 694 slot->intmask &= ~sdhci_tuning_intmask(slot); 695 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 696 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 697 slot->opt &= ~SDHCI_TUNING_ENABLED; 698 SDHCI_UNLOCK(slot); 699 callout_drain(&slot->retune_callout); 700 device_delete_child(slot->bus, d); 701 #endif 702 } else 703 SDHCI_UNLOCK(slot); 704 } 705 } 706 707 static void 708 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 709 { 710 bool was_present; 711 712 /* 713 * If there was no card and now there is one, schedule the task to 714 * create the child device after a short delay. The delay is to 715 * debounce the card insert (sometimes the card detect pin stabilizes 716 * before the other pins have made good contact). 717 * 718 * If there was a card present and now it's gone, immediately schedule 719 * the task to delete the child device. No debouncing -- gone is gone, 720 * because once power is removed, a full card re-init is needed, and 721 * that happens by deleting and recreating the child device. 722 */ 723 #ifdef MMCCAM 724 was_present = slot->card_present; 725 #else 726 was_present = slot->dev != NULL; 727 #endif 728 if (!was_present && is_present) { 729 taskqueue_enqueue_timeout(taskqueue_swi_giant, 730 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 731 } else if (was_present && !is_present) { 732 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 733 } 734 } 735 736 void 737 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 738 { 739 740 SDHCI_LOCK(slot); 741 sdhci_handle_card_present_locked(slot, is_present); 742 SDHCI_UNLOCK(slot); 743 } 744 745 static void 746 sdhci_card_poll(void *arg) 747 { 748 struct sdhci_slot *slot = arg; 749 750 sdhci_handle_card_present(slot, 751 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 752 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 753 sdhci_card_poll, slot); 754 } 755 756 static int 757 sdhci_dma_alloc(struct sdhci_slot *slot) 758 { 759 int err; 760 761 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) { 762 if (MAXPHYS <= 1024 * 4) 763 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K; 764 else if (MAXPHYS <= 1024 * 8) 765 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K; 766 else if (MAXPHYS <= 1024 * 16) 767 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K; 768 else if (MAXPHYS <= 1024 * 32) 769 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K; 770 else if (MAXPHYS <= 1024 * 64) 771 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K; 772 else if (MAXPHYS <= 1024 * 128) 773 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K; 774 else if (MAXPHYS <= 1024 * 256) 775 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K; 776 else 777 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K; 778 } 779 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary); 780 781 /* 782 * Allocate the DMA tag for an SDMA bounce buffer. 783 * Note that the SDHCI specification doesn't state any alignment 784 * constraint for the SDMA system address. However, controllers 785 * typically ignore the SDMA boundary bits in SDHCI_DMA_ADDRESS when 786 * forming the actual address of data, requiring the SDMA buffer to 787 * be aligned to the SDMA boundary. 788 */ 789 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz, 790 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 791 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW, 792 NULL, NULL, &slot->dmatag); 793 if (err != 0) { 794 slot_printf(slot, "Can't create DMA tag for SDMA\n"); 795 return (err); 796 } 797 /* Allocate DMA memory for the SDMA bounce buffer. */ 798 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 799 BUS_DMA_NOWAIT, &slot->dmamap); 800 if (err != 0) { 801 slot_printf(slot, "Can't alloc DMA memory for SDMA\n"); 802 bus_dma_tag_destroy(slot->dmatag); 803 return (err); 804 } 805 /* Map the memory of the SDMA bounce buffer. */ 806 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 807 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr, 808 &slot->paddr, 0); 809 if (err != 0 || slot->paddr == 0) { 810 slot_printf(slot, "Can't load DMA memory for SDMA\n"); 811 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 812 bus_dma_tag_destroy(slot->dmatag); 813 if (err) 814 return (err); 815 else 816 return (EFAULT); 817 } 818 819 return (0); 820 } 821 822 static void 823 sdhci_dma_free(struct sdhci_slot *slot) 824 { 825 826 bus_dmamap_unload(slot->dmatag, slot->dmamap); 827 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 828 bus_dma_tag_destroy(slot->dmatag); 829 } 830 831 int 832 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 833 { 834 kobjop_desc_t kobj_desc; 835 kobj_method_t *kobj_method; 836 uint32_t caps, caps2, freq, host_caps; 837 int err; 838 839 SDHCI_LOCK_INIT(slot); 840 841 slot->num = num; 842 slot->bus = dev; 843 844 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 845 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 846 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 847 caps = slot->caps; 848 caps2 = slot->caps2; 849 } else { 850 caps = RD4(slot, SDHCI_CAPABILITIES); 851 if (slot->version >= SDHCI_SPEC_300) 852 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 853 else 854 caps2 = 0; 855 } 856 if (slot->version >= SDHCI_SPEC_300) { 857 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 858 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 859 slot_printf(slot, 860 "Driver doesn't support shared bus slots\n"); 861 SDHCI_LOCK_DESTROY(slot); 862 return (ENXIO); 863 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 864 SDHCI_SLOTTYPE_EMBEDDED) { 865 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 866 } 867 } 868 /* Calculate base clock frequency. */ 869 if (slot->version >= SDHCI_SPEC_300) 870 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 871 SDHCI_CLOCK_BASE_SHIFT; 872 else 873 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 874 SDHCI_CLOCK_BASE_SHIFT; 875 if (freq != 0) 876 slot->max_clk = freq * 1000000; 877 /* 878 * If the frequency wasn't in the capabilities and the hardware driver 879 * hasn't already set max_clk we're probably not going to work right 880 * with an assumption, so complain about it. 881 */ 882 if (slot->max_clk == 0) { 883 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 884 slot_printf(slot, "Hardware doesn't specify base clock " 885 "frequency, using %dMHz as default.\n", 886 SDHCI_DEFAULT_MAX_FREQ); 887 } 888 /* Calculate/set timeout clock frequency. */ 889 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 890 slot->timeout_clk = slot->max_clk / 1000; 891 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 892 slot->timeout_clk = 1000; 893 } else { 894 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 895 SDHCI_TIMEOUT_CLK_SHIFT; 896 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 897 slot->timeout_clk *= 1000; 898 } 899 /* 900 * If the frequency wasn't in the capabilities and the hardware driver 901 * hasn't already set timeout_clk we'll probably work okay using the 902 * max timeout, but still mention it. 903 */ 904 if (slot->timeout_clk == 0) { 905 slot_printf(slot, "Hardware doesn't specify timeout clock " 906 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 907 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 908 } 909 910 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 911 slot->host.f_max = slot->max_clk; 912 slot->host.host_ocr = 0; 913 if (caps & SDHCI_CAN_VDD_330) 914 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 915 if (caps & SDHCI_CAN_VDD_300) 916 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 917 /* 1.8V VDD is not supposed to be used for removable cards. */ 918 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) 919 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 920 if (slot->host.host_ocr == 0) { 921 slot_printf(slot, "Hardware doesn't report any " 922 "support voltages.\n"); 923 } 924 925 host_caps = MMC_CAP_4_BIT_DATA; 926 if (caps & SDHCI_CAN_DO_8BITBUS) 927 host_caps |= MMC_CAP_8_BIT_DATA; 928 if (caps & SDHCI_CAN_DO_HISPD) 929 host_caps |= MMC_CAP_HSPEED; 930 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 931 host_caps |= MMC_CAP_BOOT_NOACC; 932 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 933 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 934 935 /* Determine supported UHS-I and eMMC modes. */ 936 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 937 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 938 if (caps2 & SDHCI_CAN_SDR104) { 939 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 940 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 941 host_caps |= MMC_CAP_MMC_HS200; 942 } else if (caps2 & SDHCI_CAN_SDR50) 943 host_caps |= MMC_CAP_UHS_SDR50; 944 if (caps2 & SDHCI_CAN_DDR50 && 945 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 946 host_caps |= MMC_CAP_UHS_DDR50; 947 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 948 host_caps |= MMC_CAP_MMC_DDR52; 949 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 950 caps2 & SDHCI_CAN_MMC_HS400) 951 host_caps |= MMC_CAP_MMC_HS400; 952 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 && 953 caps2 & SDHCI_CAN_SDR104) 954 host_caps |= MMC_CAP_MMC_HS400; 955 956 /* 957 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 958 * default NULL implementation. 959 */ 960 kobj_desc = &sdhci_set_uhs_timing_desc; 961 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 962 kobj_desc); 963 if (kobj_method == &kobj_desc->deflt) 964 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 965 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 966 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 967 968 #define SDHCI_CAP_MODES_TUNING(caps2) \ 969 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 970 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 971 MMC_CAP_MMC_HS400) 972 973 /* 974 * Disable UHS-I and eMMC modes that require (re-)tuning if either 975 * the tune or re-tune method is the default NULL implementation. 976 */ 977 kobj_desc = &mmcbr_tune_desc; 978 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 979 kobj_desc); 980 if (kobj_method == &kobj_desc->deflt) 981 goto no_tuning; 982 kobj_desc = &mmcbr_retune_desc; 983 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 984 kobj_desc); 985 if (kobj_method == &kobj_desc->deflt) { 986 no_tuning: 987 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 988 } 989 990 /* Allocate tuning structures and determine tuning parameters. */ 991 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 992 slot->opt |= SDHCI_TUNING_SUPPORTED; 993 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 994 M_WAITOK); 995 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 996 M_WAITOK); 997 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 998 M_WAITOK); 999 if (caps2 & SDHCI_TUNE_SDR50) 1000 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 1001 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 1002 SDHCI_RETUNE_MODES_SHIFT; 1003 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 1004 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 1005 SDHCI_RETUNE_CNT_SHIFT; 1006 if (slot->retune_count > 0xb) { 1007 slot_printf(slot, "Unknown re-tuning count " 1008 "%x, using 1 sec\n", slot->retune_count); 1009 slot->retune_count = 1; 1010 } else if (slot->retune_count != 0) 1011 slot->retune_count = 1012 1 << (slot->retune_count - 1); 1013 } 1014 } 1015 1016 #undef SDHCI_CAP_MODES_TUNING 1017 1018 /* Determine supported VCCQ signaling levels. */ 1019 host_caps |= MMC_CAP_SIGNALING_330; 1020 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1021 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 1022 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 1023 MMC_CAP_MMC_HS400_180)) 1024 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 1025 1026 /* 1027 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 1028 * default NULL implementation. Disable 1.2 V support if it's the 1029 * generic SDHCI implementation. 1030 */ 1031 kobj_desc = &mmcbr_switch_vccq_desc; 1032 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 1033 kobj_desc); 1034 if (kobj_method == &kobj_desc->deflt) 1035 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 1036 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 1037 host_caps &= ~MMC_CAP_SIGNALING_120; 1038 1039 /* Determine supported driver types (type B is always mandatory). */ 1040 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 1041 host_caps |= MMC_CAP_DRIVER_TYPE_A; 1042 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 1043 host_caps |= MMC_CAP_DRIVER_TYPE_C; 1044 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 1045 host_caps |= MMC_CAP_DRIVER_TYPE_D; 1046 slot->host.caps = host_caps; 1047 1048 /* Decide if we have usable DMA. */ 1049 if (caps & SDHCI_CAN_DO_DMA) 1050 slot->opt |= SDHCI_HAVE_DMA; 1051 1052 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 1053 slot->opt &= ~SDHCI_HAVE_DMA; 1054 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 1055 slot->opt |= SDHCI_HAVE_DMA; 1056 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 1057 slot->opt |= SDHCI_NON_REMOVABLE; 1058 1059 /* 1060 * Use platform-provided transfer backend 1061 * with PIO as a fallback mechanism 1062 */ 1063 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 1064 slot->opt &= ~SDHCI_HAVE_DMA; 1065 1066 if (slot->opt & SDHCI_HAVE_DMA) { 1067 err = sdhci_dma_alloc(slot); 1068 if (err != 0) { 1069 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1070 free(slot->tune_req, M_DEVBUF); 1071 free(slot->tune_cmd, M_DEVBUF); 1072 free(slot->tune_data, M_DEVBUF); 1073 } 1074 SDHCI_LOCK_DESTROY(slot); 1075 return (err); 1076 } 1077 } 1078 1079 if (bootverbose || sdhci_debug) { 1080 slot_printf(slot, 1081 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 1082 slot->max_clk / 1000000, 1083 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 1084 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 1085 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 1086 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 1087 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 1088 ((caps & SDHCI_CAN_VDD_180) && 1089 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 1090 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 1091 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 1092 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 1093 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 1094 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 1095 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 1096 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 1097 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 1098 "removable"); 1099 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 1100 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 1101 slot_printf(slot, "eMMC:%s%s%s%s\n", 1102 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 1103 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 1104 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 1105 ((host_caps & 1106 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 1107 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 1108 " HS400ES" : ""); 1109 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1110 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 1111 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 1112 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 1113 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 1114 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 1115 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 1116 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 1117 if (slot->opt & SDHCI_TUNING_SUPPORTED) 1118 slot_printf(slot, "Re-tuning count %d secs, mode %d\n", 1119 slot->retune_count, slot->retune_mode + 1); 1120 sdhci_dumpregs(slot); 1121 } 1122 1123 slot->timeout = 10; 1124 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1125 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1126 "timeout", CTLFLAG_RW, &slot->timeout, 0, 1127 "Maximum timeout for SDHCI transfers (in secs)"); 1128 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1129 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1130 sdhci_card_task, slot); 1131 callout_init(&slot->card_poll_callout, 1); 1132 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1133 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1134 1135 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1136 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1137 callout_reset(&slot->card_poll_callout, 1138 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1139 } 1140 1141 sdhci_init(slot); 1142 1143 return (0); 1144 } 1145 1146 #ifndef MMCCAM 1147 void 1148 sdhci_start_slot(struct sdhci_slot *slot) 1149 { 1150 1151 sdhci_card_task(slot, 0); 1152 } 1153 #endif 1154 1155 int 1156 sdhci_cleanup_slot(struct sdhci_slot *slot) 1157 { 1158 device_t d; 1159 1160 callout_drain(&slot->timeout_callout); 1161 callout_drain(&slot->card_poll_callout); 1162 callout_drain(&slot->retune_callout); 1163 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1164 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1165 1166 SDHCI_LOCK(slot); 1167 d = slot->dev; 1168 slot->dev = NULL; 1169 SDHCI_UNLOCK(slot); 1170 if (d != NULL) 1171 device_delete_child(slot->bus, d); 1172 1173 SDHCI_LOCK(slot); 1174 sdhci_reset(slot, SDHCI_RESET_ALL); 1175 SDHCI_UNLOCK(slot); 1176 if (slot->opt & SDHCI_HAVE_DMA) 1177 sdhci_dma_free(slot); 1178 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1179 free(slot->tune_req, M_DEVBUF); 1180 free(slot->tune_cmd, M_DEVBUF); 1181 free(slot->tune_data, M_DEVBUF); 1182 } 1183 1184 SDHCI_LOCK_DESTROY(slot); 1185 1186 return (0); 1187 } 1188 1189 int 1190 sdhci_generic_suspend(struct sdhci_slot *slot) 1191 { 1192 1193 /* 1194 * We expect the MMC layer to issue initial tuning after resume. 1195 * Otherwise, we'd need to indicate re-tuning including circuit reset 1196 * being required at least for re-tuning modes 1 and 2 ourselves. 1197 */ 1198 callout_drain(&slot->retune_callout); 1199 SDHCI_LOCK(slot); 1200 slot->opt &= ~SDHCI_TUNING_ENABLED; 1201 sdhci_reset(slot, SDHCI_RESET_ALL); 1202 SDHCI_UNLOCK(slot); 1203 1204 return (0); 1205 } 1206 1207 int 1208 sdhci_generic_resume(struct sdhci_slot *slot) 1209 { 1210 1211 SDHCI_LOCK(slot); 1212 sdhci_init(slot); 1213 SDHCI_UNLOCK(slot); 1214 1215 return (0); 1216 } 1217 1218 uint32_t 1219 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1220 { 1221 1222 if (slot->version >= SDHCI_SPEC_300) 1223 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1224 else 1225 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1226 } 1227 1228 bool 1229 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1230 { 1231 1232 if (slot->opt & SDHCI_NON_REMOVABLE) 1233 return true; 1234 1235 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1236 } 1237 1238 void 1239 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1240 { 1241 const struct mmc_ios *ios; 1242 uint16_t hostctrl2; 1243 1244 if (slot->version < SDHCI_SPEC_300) 1245 return; 1246 1247 SDHCI_ASSERT_LOCKED(slot); 1248 ios = &slot->host.ios; 1249 sdhci_set_clock(slot, 0); 1250 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1251 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1252 if (ios->clock > SD_SDR50_MAX) { 1253 if (ios->timing == bus_timing_mmc_hs400 || 1254 ios->timing == bus_timing_mmc_hs400es) 1255 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1256 else 1257 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1258 } 1259 else if (ios->clock > SD_SDR25_MAX) 1260 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1261 else if (ios->clock > SD_SDR12_MAX) { 1262 if (ios->timing == bus_timing_uhs_ddr50 || 1263 ios->timing == bus_timing_mmc_ddr52) 1264 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1265 else 1266 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1267 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1268 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1269 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1270 sdhci_set_clock(slot, ios->clock); 1271 } 1272 1273 int 1274 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1275 { 1276 struct sdhci_slot *slot = device_get_ivars(reqdev); 1277 struct mmc_ios *ios = &slot->host.ios; 1278 1279 SDHCI_LOCK(slot); 1280 /* Do full reset on bus power down to clear from any state. */ 1281 if (ios->power_mode == power_off) { 1282 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1283 sdhci_init(slot); 1284 } 1285 /* Configure the bus. */ 1286 sdhci_set_clock(slot, ios->clock); 1287 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1288 if (ios->bus_width == bus_width_8) { 1289 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1290 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1291 } else if (ios->bus_width == bus_width_4) { 1292 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1293 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1294 } else if (ios->bus_width == bus_width_1) { 1295 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1296 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1297 } else { 1298 panic("Invalid bus width: %d", ios->bus_width); 1299 } 1300 if (ios->clock > SD_SDR12_MAX && 1301 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1302 slot->hostctrl |= SDHCI_CTRL_HISPD; 1303 else 1304 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1305 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1306 SDHCI_SET_UHS_TIMING(brdev, slot); 1307 /* Some controllers like reset after bus changes. */ 1308 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1309 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1310 1311 SDHCI_UNLOCK(slot); 1312 return (0); 1313 } 1314 1315 int 1316 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1317 { 1318 struct sdhci_slot *slot = device_get_ivars(reqdev); 1319 enum mmc_vccq vccq; 1320 int err; 1321 uint16_t hostctrl2; 1322 1323 if (slot->version < SDHCI_SPEC_300) 1324 return (0); 1325 1326 err = 0; 1327 vccq = slot->host.ios.vccq; 1328 SDHCI_LOCK(slot); 1329 sdhci_set_clock(slot, 0); 1330 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1331 switch (vccq) { 1332 case vccq_330: 1333 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1334 goto done; 1335 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1336 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1337 DELAY(5000); 1338 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1339 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1340 goto done; 1341 err = EAGAIN; 1342 break; 1343 case vccq_180: 1344 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1345 err = EINVAL; 1346 goto done; 1347 } 1348 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1349 goto done; 1350 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1351 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1352 DELAY(5000); 1353 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1354 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1355 goto done; 1356 err = EAGAIN; 1357 break; 1358 default: 1359 slot_printf(slot, 1360 "Attempt to set unsupported signaling voltage\n"); 1361 err = EINVAL; 1362 break; 1363 } 1364 done: 1365 sdhci_set_clock(slot, slot->host.ios.clock); 1366 SDHCI_UNLOCK(slot); 1367 return (err); 1368 } 1369 1370 int 1371 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1372 { 1373 struct sdhci_slot *slot = device_get_ivars(reqdev); 1374 const struct mmc_ios *ios = &slot->host.ios; 1375 struct mmc_command *tune_cmd; 1376 struct mmc_data *tune_data; 1377 uint32_t opcode; 1378 int err; 1379 1380 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1381 return (0); 1382 1383 slot->retune_ticks = slot->retune_count * hz; 1384 opcode = MMC_SEND_TUNING_BLOCK; 1385 SDHCI_LOCK(slot); 1386 switch (ios->timing) { 1387 case bus_timing_mmc_hs400: 1388 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1389 SDHCI_UNLOCK(slot); 1390 return (EINVAL); 1391 case bus_timing_mmc_hs200: 1392 /* 1393 * In HS400 mode, controllers use the data strobe line to 1394 * latch data from the devices so periodic re-tuning isn't 1395 * expected to be required. 1396 */ 1397 if (hs400) 1398 slot->retune_ticks = 0; 1399 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1400 break; 1401 case bus_timing_uhs_ddr50: 1402 case bus_timing_uhs_sdr104: 1403 break; 1404 case bus_timing_uhs_sdr50: 1405 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1406 break; 1407 /* FALLTHROUGH */ 1408 default: 1409 SDHCI_UNLOCK(slot); 1410 return (0); 1411 } 1412 1413 tune_cmd = slot->tune_cmd; 1414 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1415 tune_cmd->opcode = opcode; 1416 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1417 tune_data = tune_cmd->data = slot->tune_data; 1418 memset(tune_data, 0, sizeof(*tune_data)); 1419 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1420 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1421 MMC_TUNING_LEN; 1422 tune_data->flags = MMC_DATA_READ; 1423 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1424 1425 slot->opt &= ~SDHCI_TUNING_ENABLED; 1426 err = sdhci_exec_tuning(slot, true); 1427 if (err == 0) { 1428 slot->opt |= SDHCI_TUNING_ENABLED; 1429 slot->intmask |= sdhci_tuning_intmask(slot); 1430 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1431 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1432 if (slot->retune_ticks) { 1433 callout_reset(&slot->retune_callout, slot->retune_ticks, 1434 sdhci_retune, slot); 1435 } 1436 } 1437 SDHCI_UNLOCK(slot); 1438 return (err); 1439 } 1440 1441 int 1442 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1443 { 1444 struct sdhci_slot *slot = device_get_ivars(reqdev); 1445 int err; 1446 1447 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1448 return (0); 1449 1450 /* HS400 must be tuned in HS200 mode. */ 1451 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1452 return (EINVAL); 1453 1454 SDHCI_LOCK(slot); 1455 err = sdhci_exec_tuning(slot, reset); 1456 /* 1457 * There are two ways sdhci_exec_tuning() can fail: 1458 * EBUSY should not actually happen when requests are only issued 1459 * with the host properly acquired, and 1460 * EIO re-tuning failed (but it did work initially). 1461 * 1462 * In both cases, we should retry at later point if periodic re-tuning 1463 * is enabled. Note that due to slot->retune_req not being cleared in 1464 * these failure cases, the MMC layer should trigger another attempt at 1465 * re-tuning with the next request anyway, though. 1466 */ 1467 if (slot->retune_ticks) { 1468 callout_reset(&slot->retune_callout, slot->retune_ticks, 1469 sdhci_retune, slot); 1470 } 1471 SDHCI_UNLOCK(slot); 1472 return (err); 1473 } 1474 1475 static int 1476 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1477 { 1478 struct mmc_request *tune_req; 1479 struct mmc_command *tune_cmd; 1480 int i; 1481 uint32_t intmask; 1482 uint16_t hostctrl2; 1483 u_char opt; 1484 1485 SDHCI_ASSERT_LOCKED(slot); 1486 if (slot->req != NULL) 1487 return (EBUSY); 1488 1489 /* Tuning doesn't work with DMA enabled. */ 1490 opt = slot->opt; 1491 slot->opt = opt & ~SDHCI_HAVE_DMA; 1492 1493 /* 1494 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1495 * kind of interrupt we receive in response to a tuning request. 1496 */ 1497 intmask = slot->intmask; 1498 slot->intmask = SDHCI_INT_DATA_AVAIL; 1499 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL); 1500 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1501 1502 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1503 if (reset) 1504 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1505 else 1506 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1507 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1508 1509 tune_req = slot->tune_req; 1510 tune_cmd = slot->tune_cmd; 1511 for (i = 0; i < MMC_TUNING_MAX; i++) { 1512 memset(tune_req, 0, sizeof(*tune_req)); 1513 tune_req->cmd = tune_cmd; 1514 tune_req->done = sdhci_req_wakeup; 1515 tune_req->done_data = slot; 1516 slot->req = tune_req; 1517 slot->flags = 0; 1518 sdhci_start(slot); 1519 while (!(tune_req->flags & MMC_REQ_DONE)) 1520 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1521 if (!(tune_req->flags & MMC_TUNE_DONE)) 1522 break; 1523 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1524 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1525 break; 1526 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1527 DELAY(1000); 1528 } 1529 1530 /* 1531 * Restore DMA usage and interrupts. 1532 * Note that the interrupt aggregation code might have cleared 1533 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask 1534 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE 1535 * doesn't lose these. 1536 */ 1537 slot->opt = opt; 1538 slot->intmask = intmask; 1539 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END | 1540 SDHCI_INT_RESPONSE); 1541 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1542 1543 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1544 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1545 slot->retune_req = 0; 1546 return (0); 1547 } 1548 1549 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1550 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1551 SDHCI_CTRL2_SAMPLING_CLOCK)); 1552 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1553 return (EIO); 1554 } 1555 1556 static void 1557 sdhci_retune(void *arg) 1558 { 1559 struct sdhci_slot *slot = arg; 1560 1561 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1562 } 1563 1564 #ifdef MMCCAM 1565 static void 1566 sdhci_req_done(struct sdhci_slot *slot) 1567 { 1568 union ccb *ccb; 1569 1570 if (__predict_false(sdhci_debug > 1)) 1571 slot_printf(slot, "%s\n", __func__); 1572 if (slot->ccb != NULL && slot->curcmd != NULL) { 1573 callout_stop(&slot->timeout_callout); 1574 ccb = slot->ccb; 1575 slot->ccb = NULL; 1576 slot->curcmd = NULL; 1577 1578 /* Tell CAM the request is finished */ 1579 struct ccb_mmcio *mmcio; 1580 mmcio = &ccb->mmcio; 1581 1582 ccb->ccb_h.status = 1583 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1584 xpt_done(ccb); 1585 } 1586 } 1587 #else 1588 static void 1589 sdhci_req_done(struct sdhci_slot *slot) 1590 { 1591 struct mmc_request *req; 1592 1593 if (slot->req != NULL && slot->curcmd != NULL) { 1594 callout_stop(&slot->timeout_callout); 1595 req = slot->req; 1596 slot->req = NULL; 1597 slot->curcmd = NULL; 1598 req->done(req); 1599 } 1600 } 1601 #endif 1602 1603 static void 1604 sdhci_req_wakeup(struct mmc_request *req) 1605 { 1606 struct sdhci_slot *slot; 1607 1608 slot = req->done_data; 1609 req->flags |= MMC_REQ_DONE; 1610 wakeup(req); 1611 } 1612 1613 static void 1614 sdhci_timeout(void *arg) 1615 { 1616 struct sdhci_slot *slot = arg; 1617 1618 if (slot->curcmd != NULL) { 1619 slot_printf(slot, "Controller timeout\n"); 1620 sdhci_dumpregs(slot); 1621 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1622 slot->curcmd->error = MMC_ERR_TIMEOUT; 1623 sdhci_req_done(slot); 1624 } else { 1625 slot_printf(slot, "Spurious timeout - no active command\n"); 1626 } 1627 } 1628 1629 static void 1630 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data) 1631 { 1632 uint16_t mode; 1633 1634 if (data == NULL) 1635 return; 1636 1637 mode = SDHCI_TRNS_BLK_CNT_EN; 1638 if (data->len > 512 || data->block_count > 1) { 1639 mode |= SDHCI_TRNS_MULTI; 1640 if (data->block_count == 0 && __predict_true( 1641 #ifdef MMCCAM 1642 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION && 1643 #else 1644 slot->req->stop != NULL && 1645 #endif 1646 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP))) 1647 mode |= SDHCI_TRNS_ACMD12; 1648 } 1649 if (data->flags & MMC_DATA_READ) 1650 mode |= SDHCI_TRNS_READ; 1651 if (slot->flags & SDHCI_USE_DMA) 1652 mode |= SDHCI_TRNS_DMA; 1653 1654 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1655 } 1656 1657 static void 1658 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1659 { 1660 int flags, timeout; 1661 uint32_t mask; 1662 1663 slot->curcmd = cmd; 1664 slot->cmd_done = 0; 1665 1666 cmd->error = MMC_ERR_NONE; 1667 1668 /* This flags combination is not supported by controller. */ 1669 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1670 slot_printf(slot, "Unsupported response type!\n"); 1671 cmd->error = MMC_ERR_FAILED; 1672 sdhci_req_done(slot); 1673 return; 1674 } 1675 1676 /* 1677 * Do not issue command if there is no card, clock or power. 1678 * Controller will not detect timeout without clock active. 1679 */ 1680 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1681 slot->power == 0 || 1682 slot->clock == 0) { 1683 slot_printf(slot, 1684 "Cannot issue a command (power=%d clock=%d)", 1685 slot->power, slot->clock); 1686 cmd->error = MMC_ERR_FAILED; 1687 sdhci_req_done(slot); 1688 return; 1689 } 1690 /* Always wait for free CMD bus. */ 1691 mask = SDHCI_CMD_INHIBIT; 1692 /* Wait for free DAT if we have data or busy signal. */ 1693 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1694 mask |= SDHCI_DAT_INHIBIT; 1695 /* 1696 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1697 * that these latter are also special in that SDHCI_CMD_DATA should 1698 * be set below but no actual data is ever read from the controller. 1699 */ 1700 #ifdef MMCCAM 1701 if (cmd == &slot->ccb->mmcio.stop || 1702 #else 1703 if (cmd == slot->req->stop || 1704 #endif 1705 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1706 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1707 mask &= ~SDHCI_DAT_INHIBIT; 1708 /* 1709 * Wait for bus no more then 250 ms. Typically there will be no wait 1710 * here at all, but when writing a crash dump we may be bypassing the 1711 * host platform's interrupt handler, and in some cases that handler 1712 * may be working around hardware quirks such as not respecting r1b 1713 * busy indications. In those cases, this wait-loop serves the purpose 1714 * of waiting for the prior command and data transfers to be done, and 1715 * SD cards are allowed to take up to 250ms for write and erase ops. 1716 * (It's usually more like 20-30ms in the real world.) 1717 */ 1718 timeout = 250; 1719 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1720 if (timeout == 0) { 1721 slot_printf(slot, "Controller never released " 1722 "inhibit bit(s).\n"); 1723 sdhci_dumpregs(slot); 1724 cmd->error = MMC_ERR_FAILED; 1725 sdhci_req_done(slot); 1726 return; 1727 } 1728 timeout--; 1729 DELAY(1000); 1730 } 1731 1732 /* Prepare command flags. */ 1733 if (!(cmd->flags & MMC_RSP_PRESENT)) 1734 flags = SDHCI_CMD_RESP_NONE; 1735 else if (cmd->flags & MMC_RSP_136) 1736 flags = SDHCI_CMD_RESP_LONG; 1737 else if (cmd->flags & MMC_RSP_BUSY) 1738 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1739 else 1740 flags = SDHCI_CMD_RESP_SHORT; 1741 if (cmd->flags & MMC_RSP_CRC) 1742 flags |= SDHCI_CMD_CRC; 1743 if (cmd->flags & MMC_RSP_OPCODE) 1744 flags |= SDHCI_CMD_INDEX; 1745 if (cmd->data != NULL) 1746 flags |= SDHCI_CMD_DATA; 1747 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1748 flags |= SDHCI_CMD_TYPE_ABORT; 1749 /* Prepare data. */ 1750 sdhci_start_data(slot, cmd->data); 1751 /* 1752 * Interrupt aggregation: To reduce total number of interrupts 1753 * group response interrupt with data interrupt when possible. 1754 * If there going to be data interrupt, mask response one. 1755 */ 1756 if (slot->data_done == 0) { 1757 WR4(slot, SDHCI_SIGNAL_ENABLE, 1758 slot->intmask &= ~SDHCI_INT_RESPONSE); 1759 } 1760 /* Set command argument. */ 1761 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1762 /* Set data transfer mode. */ 1763 sdhci_set_transfer_mode(slot, cmd->data); 1764 if (__predict_false(sdhci_debug > 1)) 1765 slot_printf(slot, "Starting command!\n"); 1766 /* Start command. */ 1767 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1768 /* Start timeout callout. */ 1769 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1770 sdhci_timeout, slot); 1771 } 1772 1773 static void 1774 sdhci_finish_command(struct sdhci_slot *slot) 1775 { 1776 int i; 1777 uint32_t val; 1778 uint8_t extra; 1779 1780 if (__predict_false(sdhci_debug > 1)) 1781 slot_printf(slot, "%s: called, err %d flags %d\n", 1782 __func__, slot->curcmd->error, slot->curcmd->flags); 1783 slot->cmd_done = 1; 1784 /* 1785 * Interrupt aggregation: Restore command interrupt. 1786 * Main restore point for the case when command interrupt 1787 * happened first. 1788 */ 1789 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1790 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1791 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1792 SDHCI_INT_RESPONSE); 1793 /* In case of error - reset host and return. */ 1794 if (slot->curcmd->error) { 1795 if (slot->curcmd->error == MMC_ERR_BADCRC) 1796 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1797 sdhci_reset(slot, SDHCI_RESET_CMD); 1798 sdhci_reset(slot, SDHCI_RESET_DATA); 1799 sdhci_start(slot); 1800 return; 1801 } 1802 /* If command has response - fetch it. */ 1803 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1804 if (slot->curcmd->flags & MMC_RSP_136) { 1805 /* CRC is stripped so we need one byte shift. */ 1806 extra = 0; 1807 for (i = 0; i < 4; i++) { 1808 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1809 if (slot->quirks & 1810 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1811 slot->curcmd->resp[3 - i] = val; 1812 else { 1813 slot->curcmd->resp[3 - i] = 1814 (val << 8) | extra; 1815 extra = val >> 24; 1816 } 1817 } 1818 } else 1819 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1820 } 1821 if (__predict_false(sdhci_debug > 1)) 1822 printf("Resp: %02x %02x %02x %02x\n", 1823 slot->curcmd->resp[0], slot->curcmd->resp[1], 1824 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1825 1826 /* If data ready - finish. */ 1827 if (slot->data_done) 1828 sdhci_start(slot); 1829 } 1830 1831 static void 1832 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data) 1833 { 1834 uint32_t blkcnt, blksz, current_timeout, sdma_bbufsz, target_timeout; 1835 uint8_t div; 1836 1837 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1838 slot->data_done = 1; 1839 return; 1840 } 1841 1842 slot->data_done = 0; 1843 1844 /* Calculate and set data timeout.*/ 1845 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1846 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1847 div = 0xE; 1848 } else { 1849 target_timeout = 1000000; 1850 div = 0; 1851 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1852 while (current_timeout < target_timeout && div < 0xE) { 1853 ++div; 1854 current_timeout <<= 1; 1855 } 1856 /* Compensate for an off-by-one error in the CaFe chip.*/ 1857 if (div < 0xE && 1858 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1859 ++div; 1860 } 1861 } 1862 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1863 1864 if (data == NULL) 1865 return; 1866 1867 /* Use DMA if possible. */ 1868 if ((slot->opt & SDHCI_HAVE_DMA)) 1869 slot->flags |= SDHCI_USE_DMA; 1870 /* If data is small, broken DMA may return zeroes instead of data. */ 1871 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1872 (data->len <= 512)) 1873 slot->flags &= ~SDHCI_USE_DMA; 1874 /* Some controllers require even block sizes. */ 1875 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1876 ((data->len) & 0x3)) 1877 slot->flags &= ~SDHCI_USE_DMA; 1878 /* Load DMA buffer. */ 1879 if (slot->flags & SDHCI_USE_DMA) { 1880 sdma_bbufsz = slot->sdma_bbufsz; 1881 if (data->flags & MMC_DATA_READ) 1882 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1883 BUS_DMASYNC_PREREAD); 1884 else { 1885 memcpy(slot->dmamem, data->data, ulmin(data->len, 1886 sdma_bbufsz)); 1887 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1888 BUS_DMASYNC_PREWRITE); 1889 } 1890 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1891 /* 1892 * Interrupt aggregation: Mask border interrupt for the last 1893 * bounce buffer and unmask otherwise. 1894 */ 1895 if (data->len == sdma_bbufsz) 1896 slot->intmask &= ~SDHCI_INT_DMA_END; 1897 else 1898 slot->intmask |= SDHCI_INT_DMA_END; 1899 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1900 } 1901 /* Current data offset for both PIO and DMA. */ 1902 slot->offset = 0; 1903 #ifdef MMCCAM 1904 if (data->flags & MMC_DATA_BLOCK_SIZE) { 1905 /* Set block size and request border interrupts on the SDMA boundary. */ 1906 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size); 1907 blkcnt = data->block_count; 1908 if (__predict_false(sdhci_debug > 0)) 1909 slot_printf(slot, "SDIO Custom block params: blksz: " 1910 "%#10x, blk cnt: %#10x\n", blksz, blkcnt); 1911 } else 1912 #endif 1913 { 1914 /* Set block size and request border interrupts on the SDMA boundary. */ 1915 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512)); 1916 blkcnt = howmany(data->len, 512); 1917 } 1918 1919 WR2(slot, SDHCI_BLOCK_SIZE, blksz); 1920 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt); 1921 if (__predict_false(sdhci_debug > 1)) 1922 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 1923 blksz, blkcnt); 1924 } 1925 1926 void 1927 sdhci_finish_data(struct sdhci_slot *slot) 1928 { 1929 struct mmc_data *data = slot->curcmd->data; 1930 size_t left; 1931 1932 /* Interrupt aggregation: Restore command interrupt. 1933 * Auxiliary restore point for the case when data interrupt 1934 * happened first. */ 1935 if (!slot->cmd_done) { 1936 WR4(slot, SDHCI_SIGNAL_ENABLE, 1937 slot->intmask |= SDHCI_INT_RESPONSE); 1938 } 1939 /* Unload rest of data from DMA buffer. */ 1940 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1941 slot->curcmd->data != NULL) { 1942 if (data->flags & MMC_DATA_READ) { 1943 left = data->len - slot->offset; 1944 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1945 BUS_DMASYNC_POSTREAD); 1946 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1947 ulmin(left, slot->sdma_bbufsz)); 1948 } else 1949 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1950 BUS_DMASYNC_POSTWRITE); 1951 } 1952 slot->data_done = 1; 1953 /* If there was error - reset the host. */ 1954 if (slot->curcmd->error) { 1955 if (slot->curcmd->error == MMC_ERR_BADCRC) 1956 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1957 sdhci_reset(slot, SDHCI_RESET_CMD); 1958 sdhci_reset(slot, SDHCI_RESET_DATA); 1959 sdhci_start(slot); 1960 return; 1961 } 1962 /* If we already have command response - finish. */ 1963 if (slot->cmd_done) 1964 sdhci_start(slot); 1965 } 1966 1967 #ifdef MMCCAM 1968 static void 1969 sdhci_start(struct sdhci_slot *slot) 1970 { 1971 union ccb *ccb; 1972 struct ccb_mmcio *mmcio; 1973 1974 ccb = slot->ccb; 1975 if (ccb == NULL) 1976 return; 1977 1978 mmcio = &ccb->mmcio; 1979 if (!(slot->flags & CMD_STARTED)) { 1980 slot->flags |= CMD_STARTED; 1981 sdhci_start_command(slot, &mmcio->cmd); 1982 return; 1983 } 1984 1985 /* 1986 * Old stack doesn't use this! 1987 * Enabling this code causes significant performance degradation 1988 * and IRQ storms on BBB, Wandboard behaves fine. 1989 * Not using this code does no harm... 1990 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1991 slot->flags |= STOP_STARTED; 1992 sdhci_start_command(slot, &mmcio->stop); 1993 return; 1994 } 1995 */ 1996 if (__predict_false(sdhci_debug > 1)) 1997 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1998 if (mmcio->cmd.error == 0 && 1999 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 2000 sdhci_reset(slot, SDHCI_RESET_CMD); 2001 sdhci_reset(slot, SDHCI_RESET_DATA); 2002 } 2003 2004 sdhci_req_done(slot); 2005 } 2006 #else 2007 static void 2008 sdhci_start(struct sdhci_slot *slot) 2009 { 2010 const struct mmc_request *req; 2011 2012 req = slot->req; 2013 if (req == NULL) 2014 return; 2015 2016 if (!(slot->flags & CMD_STARTED)) { 2017 slot->flags |= CMD_STARTED; 2018 sdhci_start_command(slot, req->cmd); 2019 return; 2020 } 2021 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 2022 !(slot->flags & STOP_STARTED) && req->stop) { 2023 slot->flags |= STOP_STARTED; 2024 sdhci_start_command(slot, req->stop); 2025 return; 2026 } 2027 if (__predict_false(sdhci_debug > 1)) 2028 slot_printf(slot, "result: %d\n", req->cmd->error); 2029 if (!req->cmd->error && 2030 ((slot->curcmd == req->stop && 2031 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 2032 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2033 sdhci_reset(slot, SDHCI_RESET_CMD); 2034 sdhci_reset(slot, SDHCI_RESET_DATA); 2035 } 2036 2037 sdhci_req_done(slot); 2038 } 2039 #endif 2040 2041 int 2042 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 2043 struct mmc_request *req) 2044 { 2045 struct sdhci_slot *slot = device_get_ivars(reqdev); 2046 2047 SDHCI_LOCK(slot); 2048 if (slot->req != NULL) { 2049 SDHCI_UNLOCK(slot); 2050 return (EBUSY); 2051 } 2052 if (__predict_false(sdhci_debug > 1)) { 2053 slot_printf(slot, 2054 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2055 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 2056 (req->cmd->data)?(u_int)req->cmd->data->len:0, 2057 (req->cmd->data)?req->cmd->data->flags:0); 2058 } 2059 slot->req = req; 2060 slot->flags = 0; 2061 sdhci_start(slot); 2062 SDHCI_UNLOCK(slot); 2063 if (dumping) { 2064 while (slot->req != NULL) { 2065 sdhci_generic_intr(slot); 2066 DELAY(10); 2067 } 2068 } 2069 return (0); 2070 } 2071 2072 int 2073 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 2074 { 2075 struct sdhci_slot *slot = device_get_ivars(reqdev); 2076 uint32_t val; 2077 2078 SDHCI_LOCK(slot); 2079 val = RD4(slot, SDHCI_PRESENT_STATE); 2080 SDHCI_UNLOCK(slot); 2081 return (!(val & SDHCI_WRITE_PROTECT)); 2082 } 2083 2084 int 2085 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 2086 { 2087 struct sdhci_slot *slot = device_get_ivars(reqdev); 2088 int err = 0; 2089 2090 SDHCI_LOCK(slot); 2091 while (slot->bus_busy) 2092 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 2093 slot->bus_busy++; 2094 /* Activate led. */ 2095 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 2096 SDHCI_UNLOCK(slot); 2097 return (err); 2098 } 2099 2100 int 2101 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 2102 { 2103 struct sdhci_slot *slot = device_get_ivars(reqdev); 2104 2105 SDHCI_LOCK(slot); 2106 /* Deactivate led. */ 2107 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 2108 slot->bus_busy--; 2109 SDHCI_UNLOCK(slot); 2110 wakeup(slot); 2111 return (0); 2112 } 2113 2114 static void 2115 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2116 { 2117 2118 if (!slot->curcmd) { 2119 slot_printf(slot, "Got command interrupt 0x%08x, but " 2120 "there is no active command.\n", intmask); 2121 sdhci_dumpregs(slot); 2122 return; 2123 } 2124 if (intmask & SDHCI_INT_TIMEOUT) 2125 slot->curcmd->error = MMC_ERR_TIMEOUT; 2126 else if (intmask & SDHCI_INT_CRC) 2127 slot->curcmd->error = MMC_ERR_BADCRC; 2128 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2129 slot->curcmd->error = MMC_ERR_FIFO; 2130 2131 sdhci_finish_command(slot); 2132 } 2133 2134 static void 2135 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2136 { 2137 struct mmc_data *data; 2138 size_t left; 2139 uint32_t sdma_bbufsz; 2140 2141 if (!slot->curcmd) { 2142 slot_printf(slot, "Got data interrupt 0x%08x, but " 2143 "there is no active command.\n", intmask); 2144 sdhci_dumpregs(slot); 2145 return; 2146 } 2147 if (slot->curcmd->data == NULL && 2148 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2149 slot_printf(slot, "Got data interrupt 0x%08x, but " 2150 "there is no active data operation.\n", 2151 intmask); 2152 sdhci_dumpregs(slot); 2153 return; 2154 } 2155 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2156 slot->curcmd->error = MMC_ERR_TIMEOUT; 2157 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2158 slot->curcmd->error = MMC_ERR_BADCRC; 2159 if (slot->curcmd->data == NULL && 2160 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2161 SDHCI_INT_DMA_END))) { 2162 slot_printf(slot, "Got data interrupt 0x%08x, but " 2163 "there is busy-only command.\n", intmask); 2164 sdhci_dumpregs(slot); 2165 slot->curcmd->error = MMC_ERR_INVALID; 2166 } 2167 if (slot->curcmd->error) { 2168 /* No need to continue after any error. */ 2169 goto done; 2170 } 2171 2172 /* Handle tuning completion interrupt. */ 2173 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2174 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2175 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2176 slot->req->flags |= MMC_TUNE_DONE; 2177 sdhci_finish_command(slot); 2178 sdhci_finish_data(slot); 2179 return; 2180 } 2181 /* Handle PIO interrupt. */ 2182 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2183 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2184 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2185 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2186 &intmask); 2187 slot->flags |= PLATFORM_DATA_STARTED; 2188 } else 2189 sdhci_transfer_pio(slot); 2190 } 2191 /* Handle DMA border. */ 2192 if (intmask & SDHCI_INT_DMA_END) { 2193 data = slot->curcmd->data; 2194 sdma_bbufsz = slot->sdma_bbufsz; 2195 2196 /* Unload DMA buffer ... */ 2197 left = data->len - slot->offset; 2198 if (data->flags & MMC_DATA_READ) { 2199 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2200 BUS_DMASYNC_POSTREAD); 2201 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2202 ulmin(left, sdma_bbufsz)); 2203 } else { 2204 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2205 BUS_DMASYNC_POSTWRITE); 2206 } 2207 /* ... and reload it again. */ 2208 slot->offset += sdma_bbufsz; 2209 left = data->len - slot->offset; 2210 if (data->flags & MMC_DATA_READ) { 2211 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2212 BUS_DMASYNC_PREREAD); 2213 } else { 2214 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2215 ulmin(left, sdma_bbufsz)); 2216 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2217 BUS_DMASYNC_PREWRITE); 2218 } 2219 /* 2220 * Interrupt aggregation: Mask border interrupt for the last 2221 * bounce buffer. 2222 */ 2223 if (left == sdma_bbufsz) { 2224 slot->intmask &= ~SDHCI_INT_DMA_END; 2225 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2226 } 2227 /* Restart DMA. */ 2228 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2229 } 2230 /* We have got all data. */ 2231 if (intmask & SDHCI_INT_DATA_END) { 2232 if (slot->flags & PLATFORM_DATA_STARTED) { 2233 slot->flags &= ~PLATFORM_DATA_STARTED; 2234 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2235 } else 2236 sdhci_finish_data(slot); 2237 } 2238 done: 2239 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2240 if (slot->flags & PLATFORM_DATA_STARTED) { 2241 slot->flags &= ~PLATFORM_DATA_STARTED; 2242 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2243 } else 2244 sdhci_finish_data(slot); 2245 } 2246 } 2247 2248 static void 2249 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) 2250 { 2251 2252 if (!slot->curcmd) { 2253 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2254 "there is no active command.\n", acmd_err); 2255 sdhci_dumpregs(slot); 2256 return; 2257 } 2258 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err); 2259 sdhci_reset(slot, SDHCI_RESET_CMD); 2260 } 2261 2262 void 2263 sdhci_generic_intr(struct sdhci_slot *slot) 2264 { 2265 uint32_t intmask, present; 2266 uint16_t val16; 2267 2268 SDHCI_LOCK(slot); 2269 /* Read slot interrupt status. */ 2270 intmask = RD4(slot, SDHCI_INT_STATUS); 2271 if (intmask == 0 || intmask == 0xffffffff) { 2272 SDHCI_UNLOCK(slot); 2273 return; 2274 } 2275 if (__predict_false(sdhci_debug > 2)) 2276 slot_printf(slot, "Interrupt %#x\n", intmask); 2277 2278 /* Handle tuning error interrupt. */ 2279 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2280 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR); 2281 slot_printf(slot, "Tuning error indicated\n"); 2282 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2283 if (slot->curcmd) { 2284 slot->curcmd->error = MMC_ERR_BADCRC; 2285 sdhci_finish_command(slot); 2286 } 2287 } 2288 /* Handle re-tuning interrupt. */ 2289 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2290 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2291 /* Handle card presence interrupts. */ 2292 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2293 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2294 slot->intmask &= 2295 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2296 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2297 SDHCI_INT_CARD_INSERT; 2298 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2299 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2300 WR4(slot, SDHCI_INT_STATUS, intmask & 2301 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2302 sdhci_handle_card_present_locked(slot, present); 2303 } 2304 /* Handle command interrupts. */ 2305 if (intmask & SDHCI_INT_CMD_MASK) { 2306 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2307 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2308 } 2309 /* Handle data interrupts. */ 2310 if (intmask & SDHCI_INT_DATA_MASK) { 2311 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2312 /* Don't call data_irq in case of errored command. */ 2313 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2314 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2315 } 2316 /* Handle AutoCMD12 error interrupt. */ 2317 if (intmask & SDHCI_INT_ACMD12ERR) { 2318 /* Clearing SDHCI_INT_ACMD12ERR may clear SDHCI_ACMD12_ERR. */ 2319 val16 = RD2(slot, SDHCI_ACMD12_ERR); 2320 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2321 sdhci_acmd_irq(slot, val16); 2322 } 2323 /* Handle bus power interrupt. */ 2324 if (intmask & SDHCI_INT_BUS_POWER) { 2325 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2326 slot_printf(slot, "Card is consuming too much power!\n"); 2327 } 2328 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2329 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2330 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2331 /* The rest is unknown. */ 2332 if (intmask) { 2333 WR4(slot, SDHCI_INT_STATUS, intmask); 2334 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2335 intmask); 2336 sdhci_dumpregs(slot); 2337 } 2338 2339 SDHCI_UNLOCK(slot); 2340 } 2341 2342 int 2343 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2344 uintptr_t *result) 2345 { 2346 const struct sdhci_slot *slot = device_get_ivars(child); 2347 2348 switch (which) { 2349 default: 2350 return (EINVAL); 2351 case MMCBR_IVAR_BUS_MODE: 2352 *result = slot->host.ios.bus_mode; 2353 break; 2354 case MMCBR_IVAR_BUS_WIDTH: 2355 *result = slot->host.ios.bus_width; 2356 break; 2357 case MMCBR_IVAR_CHIP_SELECT: 2358 *result = slot->host.ios.chip_select; 2359 break; 2360 case MMCBR_IVAR_CLOCK: 2361 *result = slot->host.ios.clock; 2362 break; 2363 case MMCBR_IVAR_F_MIN: 2364 *result = slot->host.f_min; 2365 break; 2366 case MMCBR_IVAR_F_MAX: 2367 *result = slot->host.f_max; 2368 break; 2369 case MMCBR_IVAR_HOST_OCR: 2370 *result = slot->host.host_ocr; 2371 break; 2372 case MMCBR_IVAR_MODE: 2373 *result = slot->host.mode; 2374 break; 2375 case MMCBR_IVAR_OCR: 2376 *result = slot->host.ocr; 2377 break; 2378 case MMCBR_IVAR_POWER_MODE: 2379 *result = slot->host.ios.power_mode; 2380 break; 2381 case MMCBR_IVAR_VDD: 2382 *result = slot->host.ios.vdd; 2383 break; 2384 case MMCBR_IVAR_RETUNE_REQ: 2385 if (slot->opt & SDHCI_TUNING_ENABLED) { 2386 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2387 *result = retune_req_reset; 2388 break; 2389 } 2390 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2391 *result = retune_req_normal; 2392 break; 2393 } 2394 } 2395 *result = retune_req_none; 2396 break; 2397 case MMCBR_IVAR_VCCQ: 2398 *result = slot->host.ios.vccq; 2399 break; 2400 case MMCBR_IVAR_CAPS: 2401 *result = slot->host.caps; 2402 break; 2403 case MMCBR_IVAR_TIMING: 2404 *result = slot->host.ios.timing; 2405 break; 2406 case MMCBR_IVAR_MAX_DATA: 2407 /* 2408 * Re-tuning modes 1 and 2 restrict the maximum data length 2409 * per read/write command to 4 MiB. 2410 */ 2411 if (slot->opt & SDHCI_TUNING_ENABLED && 2412 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2413 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2414 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2415 break; 2416 } 2417 *result = 65535; 2418 break; 2419 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2420 /* 2421 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2422 */ 2423 *result = 1000000; 2424 break; 2425 } 2426 return (0); 2427 } 2428 2429 int 2430 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2431 uintptr_t value) 2432 { 2433 struct sdhci_slot *slot = device_get_ivars(child); 2434 uint32_t clock, max_clock; 2435 int i; 2436 2437 if (sdhci_debug > 1) 2438 slot_printf(slot, "%s: var=%d\n", __func__, which); 2439 switch (which) { 2440 default: 2441 return (EINVAL); 2442 case MMCBR_IVAR_BUS_MODE: 2443 slot->host.ios.bus_mode = value; 2444 break; 2445 case MMCBR_IVAR_BUS_WIDTH: 2446 slot->host.ios.bus_width = value; 2447 break; 2448 case MMCBR_IVAR_CHIP_SELECT: 2449 slot->host.ios.chip_select = value; 2450 break; 2451 case MMCBR_IVAR_CLOCK: 2452 if (value > 0) { 2453 max_clock = slot->max_clk; 2454 clock = max_clock; 2455 2456 if (slot->version < SDHCI_SPEC_300) { 2457 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2458 i <<= 1) { 2459 if (clock <= value) 2460 break; 2461 clock >>= 1; 2462 } 2463 } else { 2464 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2465 i += 2) { 2466 if (clock <= value) 2467 break; 2468 clock = max_clock / (i + 2); 2469 } 2470 } 2471 2472 slot->host.ios.clock = clock; 2473 } else 2474 slot->host.ios.clock = 0; 2475 break; 2476 case MMCBR_IVAR_MODE: 2477 slot->host.mode = value; 2478 break; 2479 case MMCBR_IVAR_OCR: 2480 slot->host.ocr = value; 2481 break; 2482 case MMCBR_IVAR_POWER_MODE: 2483 slot->host.ios.power_mode = value; 2484 break; 2485 case MMCBR_IVAR_VDD: 2486 slot->host.ios.vdd = value; 2487 break; 2488 case MMCBR_IVAR_VCCQ: 2489 slot->host.ios.vccq = value; 2490 break; 2491 case MMCBR_IVAR_TIMING: 2492 slot->host.ios.timing = value; 2493 break; 2494 case MMCBR_IVAR_CAPS: 2495 case MMCBR_IVAR_HOST_OCR: 2496 case MMCBR_IVAR_F_MIN: 2497 case MMCBR_IVAR_F_MAX: 2498 case MMCBR_IVAR_MAX_DATA: 2499 case MMCBR_IVAR_RETUNE_REQ: 2500 return (EINVAL); 2501 } 2502 return (0); 2503 } 2504 2505 #ifdef MMCCAM 2506 void 2507 sdhci_start_slot(struct sdhci_slot *slot) 2508 { 2509 2510 if ((slot->devq = cam_simq_alloc(1)) == NULL) 2511 goto fail; 2512 2513 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2514 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2515 "sdhci_slot", slot, device_get_unit(slot->bus), 2516 &slot->sim_mtx, 1, 1, slot->devq); 2517 2518 if (slot->sim == NULL) { 2519 cam_simq_free(slot->devq); 2520 slot_printf(slot, "cannot allocate CAM SIM\n"); 2521 goto fail; 2522 } 2523 2524 mtx_lock(&slot->sim_mtx); 2525 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2526 slot_printf(slot, "cannot register SCSI pass-through bus\n"); 2527 cam_sim_free(slot->sim, FALSE); 2528 cam_simq_free(slot->devq); 2529 mtx_unlock(&slot->sim_mtx); 2530 goto fail; 2531 } 2532 mtx_unlock(&slot->sim_mtx); 2533 2534 /* End CAM-specific init */ 2535 slot->card_present = 0; 2536 sdhci_card_task(slot, 0); 2537 return; 2538 2539 fail: 2540 if (slot->sim != NULL) { 2541 mtx_lock(&slot->sim_mtx); 2542 xpt_bus_deregister(cam_sim_path(slot->sim)); 2543 cam_sim_free(slot->sim, FALSE); 2544 mtx_unlock(&slot->sim_mtx); 2545 } 2546 2547 if (slot->devq != NULL) 2548 cam_simq_free(slot->devq); 2549 } 2550 2551 static void 2552 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2553 { 2554 struct sdhci_slot *slot; 2555 2556 slot = cam_sim_softc(sim); 2557 2558 sdhci_cam_request(slot, ccb); 2559 } 2560 2561 void 2562 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2563 { 2564 struct sdhci_slot *slot; 2565 2566 slot = cam_sim_softc(sim); 2567 if (slot == NULL) { 2568 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2569 xpt_done(ccb); 2570 return; 2571 } 2572 2573 mtx_assert(&slot->sim_mtx, MA_OWNED); 2574 2575 switch (ccb->ccb_h.func_code) { 2576 case XPT_PATH_INQ: 2577 { 2578 struct ccb_pathinq *cpi; 2579 2580 cpi = &ccb->cpi; 2581 cpi->version_num = 1; 2582 cpi->hba_inquiry = 0; 2583 cpi->target_sprt = 0; 2584 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2585 cpi->hba_eng_cnt = 0; 2586 cpi->max_target = 0; 2587 cpi->max_lun = 0; 2588 cpi->initiator_id = 1; 2589 cpi->maxio = MAXPHYS; 2590 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2591 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2592 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2593 cpi->unit_number = cam_sim_unit(sim); 2594 cpi->bus_id = cam_sim_bus(sim); 2595 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2596 cpi->protocol = PROTO_MMCSD; 2597 cpi->protocol_version = SCSI_REV_0; 2598 cpi->transport = XPORT_MMCSD; 2599 cpi->transport_version = 0; 2600 2601 cpi->ccb_h.status = CAM_REQ_CMP; 2602 break; 2603 } 2604 case XPT_GET_TRAN_SETTINGS: 2605 { 2606 struct ccb_trans_settings *cts = &ccb->cts; 2607 uint32_t max_data; 2608 2609 if (sdhci_debug > 1) 2610 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2611 2612 cts->protocol = PROTO_MMCSD; 2613 cts->protocol_version = 1; 2614 cts->transport = XPORT_MMCSD; 2615 cts->transport_version = 1; 2616 cts->xport_specific.valid = 0; 2617 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2618 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2619 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2620 cts->proto_specific.mmc.host_caps = slot->host.caps; 2621 /* 2622 * Re-tuning modes 1 and 2 restrict the maximum data length 2623 * per read/write command to 4 MiB. 2624 */ 2625 if (slot->opt & SDHCI_TUNING_ENABLED && 2626 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2627 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2628 max_data = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2629 } else { 2630 max_data = 65535; 2631 } 2632 cts->proto_specific.mmc.host_max_data = max_data; 2633 2634 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2635 ccb->ccb_h.status = CAM_REQ_CMP; 2636 break; 2637 } 2638 case XPT_SET_TRAN_SETTINGS: 2639 { 2640 if (sdhci_debug > 1) 2641 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2642 sdhci_cam_settran_settings(slot, ccb); 2643 ccb->ccb_h.status = CAM_REQ_CMP; 2644 break; 2645 } 2646 case XPT_RESET_BUS: 2647 if (sdhci_debug > 1) 2648 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2649 ccb->ccb_h.status = CAM_REQ_CMP; 2650 break; 2651 case XPT_MMC_IO: 2652 /* 2653 * Here is the HW-dependent part of 2654 * sending the command to the underlying h/w 2655 * At some point in the future an interrupt comes. 2656 * Then the request will be marked as completed. 2657 */ 2658 if (__predict_false(sdhci_debug > 1)) 2659 slot_printf(slot, "Got XPT_MMC_IO\n"); 2660 ccb->ccb_h.status = CAM_REQ_INPROG; 2661 2662 sdhci_cam_handle_mmcio(sim, ccb); 2663 return; 2664 /* NOTREACHED */ 2665 break; 2666 default: 2667 ccb->ccb_h.status = CAM_REQ_INVALID; 2668 break; 2669 } 2670 xpt_done(ccb); 2671 return; 2672 } 2673 2674 void 2675 sdhci_cam_poll(struct cam_sim *sim) 2676 { 2677 return; 2678 } 2679 2680 static int 2681 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, 2682 int proposed_clock) 2683 { 2684 int max_clock, clock, i; 2685 2686 if (proposed_clock == 0) 2687 return 0; 2688 max_clock = slot->max_clk; 2689 clock = max_clock; 2690 2691 if (slot->version < SDHCI_SPEC_300) { 2692 for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) { 2693 if (clock <= proposed_clock) 2694 break; 2695 clock >>= 1; 2696 } 2697 } else { 2698 for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) { 2699 if (clock <= proposed_clock) 2700 break; 2701 clock = max_clock / (i + 2); 2702 } 2703 } 2704 return clock; 2705 } 2706 2707 static int 2708 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2709 { 2710 struct mmc_ios *ios; 2711 const struct mmc_ios *new_ios; 2712 const struct ccb_trans_settings_mmc *cts; 2713 2714 ios = &slot->host.ios; 2715 cts = &ccb->cts.proto_specific.mmc; 2716 new_ios = &cts->ios; 2717 2718 /* Update only requested fields */ 2719 if (cts->ios_valid & MMC_CLK) { 2720 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2721 slot_printf(slot, "Clock => %d\n", ios->clock); 2722 } 2723 if (cts->ios_valid & MMC_VDD) { 2724 ios->vdd = new_ios->vdd; 2725 slot_printf(slot, "VDD => %d\n", ios->vdd); 2726 } 2727 if (cts->ios_valid & MMC_CS) { 2728 ios->chip_select = new_ios->chip_select; 2729 slot_printf(slot, "CS => %d\n", ios->chip_select); 2730 } 2731 if (cts->ios_valid & MMC_BW) { 2732 ios->bus_width = new_ios->bus_width; 2733 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2734 } 2735 if (cts->ios_valid & MMC_PM) { 2736 ios->power_mode = new_ios->power_mode; 2737 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2738 } 2739 if (cts->ios_valid & MMC_BT) { 2740 ios->timing = new_ios->timing; 2741 slot_printf(slot, "Timing => %d\n", ios->timing); 2742 } 2743 if (cts->ios_valid & MMC_BM) { 2744 ios->bus_mode = new_ios->bus_mode; 2745 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2746 } 2747 2748 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2749 return (sdhci_cam_update_ios(slot)); 2750 } 2751 2752 static int 2753 sdhci_cam_update_ios(struct sdhci_slot *slot) 2754 { 2755 struct mmc_ios *ios = &slot->host.ios; 2756 2757 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2758 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2759 SDHCI_LOCK(slot); 2760 /* Do full reset on bus power down to clear from any state. */ 2761 if (ios->power_mode == power_off) { 2762 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2763 sdhci_init(slot); 2764 } 2765 /* Configure the bus. */ 2766 sdhci_set_clock(slot, ios->clock); 2767 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2768 if (ios->bus_width == bus_width_8) { 2769 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2770 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2771 } else if (ios->bus_width == bus_width_4) { 2772 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2773 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2774 } else if (ios->bus_width == bus_width_1) { 2775 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2776 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2777 } else { 2778 panic("Invalid bus width: %d", ios->bus_width); 2779 } 2780 if (ios->timing == bus_timing_hs && 2781 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2782 slot->hostctrl |= SDHCI_CTRL_HISPD; 2783 else 2784 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2785 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2786 /* Some controllers like reset after bus changes. */ 2787 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2788 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2789 2790 SDHCI_UNLOCK(slot); 2791 return (0); 2792 } 2793 2794 static int 2795 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2796 { 2797 const struct ccb_mmcio *mmcio; 2798 2799 mmcio = &ccb->mmcio; 2800 2801 SDHCI_LOCK(slot); 2802 /* if (slot->req != NULL) { 2803 SDHCI_UNLOCK(slot); 2804 return (EBUSY); 2805 } 2806 */ 2807 if (__predict_false(sdhci_debug > 1)) { 2808 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x " 2809 "blksz=%zu blkcnt=%zu\n", 2810 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2811 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2812 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags : 0, 2813 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_size : 0, 2814 mmcio->cmd.data != NULL ? mmcio->cmd.data->block_count : 0); 2815 } 2816 if (mmcio->cmd.data != NULL) { 2817 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2818 panic("data->len = %d, data->flags = %d -- something is b0rked", 2819 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2820 } 2821 slot->ccb = ccb; 2822 slot->flags = 0; 2823 sdhci_start(slot); 2824 SDHCI_UNLOCK(slot); 2825 if (dumping) { 2826 while (slot->ccb != NULL) { 2827 sdhci_generic_intr(slot); 2828 DELAY(10); 2829 } 2830 } 2831 return (0); 2832 } 2833 #endif /* MMCCAM */ 2834 2835 MODULE_VERSION(sdhci, SDHCI_VERSION); 2836