1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/kobj.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/stdarg.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcreg.h> 54 #include <dev/mmc/mmcbrvar.h> 55 56 #include <dev/sdhci/sdhci.h> 57 58 #include <cam/cam.h> 59 #include <cam/cam_ccb.h> 60 #include <cam/cam_debug.h> 61 #include <cam/cam_sim.h> 62 #include <cam/cam_xpt_sim.h> 63 64 #include "mmcbr_if.h" 65 #include "sdhci_if.h" 66 67 #include "opt_mmccam.h" 68 69 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 70 71 static int sdhci_debug = 0; 72 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 73 "Debug level"); 74 u_int sdhci_quirk_clear = 0; 75 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 76 0, "Mask of quirks to clear"); 77 u_int sdhci_quirk_set = 0; 78 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 79 "Mask of quirks to set"); 80 81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 84 #define RD_MULTI_4(slot, off, ptr, count) \ 85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 86 87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 90 #define WR_MULTI_4(slot, off, ptr, count) \ 91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 92 93 static void sdhci_card_poll(void *arg); 94 static void sdhci_card_task(void *arg, int pending); 95 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 96 static void sdhci_req_wakeup(struct mmc_request *req); 97 static void sdhci_retune(void *arg); 98 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 99 static void sdhci_start(struct sdhci_slot *slot); 100 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 101 102 #ifdef MMCCAM 103 /* CAM-related */ 104 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock); 105 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 106 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 107 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 108 static void sdhci_cam_poll(struct cam_sim *sim); 109 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 110 #endif 111 112 /* helper routines */ 113 static void sdhci_dumpregs(struct sdhci_slot *slot); 114 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 115 __printflike(2, 3); 116 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot); 117 118 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 119 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 120 #define SDHCI_LOCK_INIT(_slot) \ 121 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 122 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 123 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 124 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 125 126 #define SDHCI_DEFAULT_MAX_FREQ 50 127 128 #define SDHCI_200_MAX_DIVIDER 256 129 #define SDHCI_300_MAX_DIVIDER 2046 130 131 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 132 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 133 134 /* 135 * Broadcom BCM577xx Controller Constants 136 */ 137 /* Maximum divider supported by the default clock source. */ 138 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 139 /* Alternative clock's base frequency. */ 140 #define BCM577XX_ALT_CLOCK_BASE 63000000 141 142 #define BCM577XX_HOST_CONTROL 0x198 143 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 144 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 145 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 146 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 147 148 static void 149 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 150 { 151 152 if (error != 0) { 153 printf("getaddr: error %d\n", error); 154 return; 155 } 156 *(bus_addr_t *)arg = segs[0].ds_addr; 157 } 158 159 static int 160 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 161 { 162 va_list ap; 163 int retval; 164 165 retval = printf("%s-slot%d: ", 166 device_get_nameunit(slot->bus), slot->num); 167 168 va_start(ap, fmt); 169 retval += vprintf(fmt, ap); 170 va_end(ap); 171 return (retval); 172 } 173 174 static void 175 sdhci_dumpregs(struct sdhci_slot *slot) 176 { 177 178 slot_printf(slot, 179 "============== REGISTER DUMP ==============\n"); 180 181 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 182 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 183 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 184 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 185 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 186 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 187 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 188 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 189 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 190 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 191 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 192 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 193 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 194 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 195 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 196 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 197 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 198 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 199 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 200 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 201 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 202 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 203 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 204 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 205 206 slot_printf(slot, 207 "===========================================\n"); 208 } 209 210 static void 211 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 212 { 213 int timeout; 214 uint32_t clock; 215 216 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 217 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 218 return; 219 } 220 221 /* Some controllers need this kick or reset won't work. */ 222 if ((mask & SDHCI_RESET_ALL) == 0 && 223 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 224 /* This is to force an update */ 225 clock = slot->clock; 226 slot->clock = 0; 227 sdhci_set_clock(slot, clock); 228 } 229 230 if (mask & SDHCI_RESET_ALL) { 231 slot->clock = 0; 232 slot->power = 0; 233 } 234 235 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 236 237 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 238 /* 239 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 240 * specification. The reset bit has internal propagation delay, 241 * so a fast read after write returns 0 even if reset process is 242 * in progress. The workaround is to poll for 1 before polling 243 * for 0. In the worst case, if we miss seeing it asserted the 244 * time we spent waiting is enough to ensure the reset finishes. 245 */ 246 timeout = 10000; 247 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 248 if (timeout <= 0) 249 break; 250 timeout--; 251 DELAY(1); 252 } 253 } 254 255 /* Wait max 100 ms */ 256 timeout = 10000; 257 /* Controller clears the bits when it's done */ 258 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 259 if (timeout <= 0) { 260 slot_printf(slot, "Reset 0x%x never completed.\n", 261 mask); 262 sdhci_dumpregs(slot); 263 return; 264 } 265 timeout--; 266 DELAY(10); 267 } 268 } 269 270 static uint32_t 271 sdhci_tuning_intmask(struct sdhci_slot *slot) 272 { 273 uint32_t intmask; 274 275 intmask = 0; 276 if (slot->opt & SDHCI_TUNING_ENABLED) { 277 intmask |= SDHCI_INT_TUNEERR; 278 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 279 slot->retune_mode == SDHCI_RETUNE_MODE_3) 280 intmask |= SDHCI_INT_RETUNE; 281 } 282 return (intmask); 283 } 284 285 static void 286 sdhci_init(struct sdhci_slot *slot) 287 { 288 289 sdhci_reset(slot, SDHCI_RESET_ALL); 290 291 /* Enable interrupts. */ 292 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 293 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 294 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 295 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 296 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 297 SDHCI_INT_ACMD12ERR; 298 299 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 300 !(slot->opt & SDHCI_NON_REMOVABLE)) { 301 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 302 } 303 304 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 305 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 306 } 307 308 static void 309 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 310 { 311 uint32_t clk_base; 312 uint32_t clk_sel; 313 uint32_t res; 314 uint16_t clk; 315 uint16_t div; 316 int timeout; 317 318 if (clock == slot->clock) 319 return; 320 slot->clock = clock; 321 322 /* Turn off the clock. */ 323 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 324 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 325 /* If no clock requested - leave it so. */ 326 if (clock == 0) 327 return; 328 329 /* Determine the clock base frequency */ 330 clk_base = slot->max_clk; 331 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 332 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 333 BCM577XX_CTRL_CLKSEL_MASK; 334 335 /* 336 * Select clock source appropriate for the requested frequency. 337 */ 338 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 339 clk_base = BCM577XX_ALT_CLOCK_BASE; 340 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 341 BCM577XX_CTRL_CLKSEL_SHIFT); 342 } else { 343 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 344 BCM577XX_CTRL_CLKSEL_SHIFT); 345 } 346 347 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 348 } 349 350 /* Recalculate timeout clock frequency based on the new sd clock. */ 351 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 352 slot->timeout_clk = slot->clock / 1000; 353 354 if (slot->version < SDHCI_SPEC_300) { 355 /* Looking for highest freq <= clock. */ 356 res = clk_base; 357 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 358 if (res <= clock) 359 break; 360 res >>= 1; 361 } 362 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 363 div >>= 1; 364 } else { 365 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 366 if (clock >= clk_base) 367 div = 0; 368 else { 369 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 370 if ((clk_base / div) <= clock) 371 break; 372 } 373 } 374 div >>= 1; 375 } 376 377 if (bootverbose || sdhci_debug) 378 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 379 div, clock, clk_base); 380 381 /* Now we have got divider, set it. */ 382 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 383 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 384 << SDHCI_DIVIDER_HI_SHIFT; 385 386 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 387 /* Enable clock. */ 388 clk |= SDHCI_CLOCK_INT_EN; 389 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 390 /* Wait up to 10 ms until it stabilize. */ 391 timeout = 10; 392 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 393 & SDHCI_CLOCK_INT_STABLE)) { 394 if (timeout == 0) { 395 slot_printf(slot, 396 "Internal clock never stabilised.\n"); 397 sdhci_dumpregs(slot); 398 return; 399 } 400 timeout--; 401 DELAY(1000); 402 } 403 /* Pass clock signal to the bus. */ 404 clk |= SDHCI_CLOCK_CARD_EN; 405 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 406 } 407 408 static void 409 sdhci_set_power(struct sdhci_slot *slot, u_char power) 410 { 411 int i; 412 uint8_t pwr; 413 414 if (slot->power == power) 415 return; 416 417 slot->power = power; 418 419 /* Turn off the power. */ 420 pwr = 0; 421 WR1(slot, SDHCI_POWER_CONTROL, pwr); 422 /* If power down requested - leave it so. */ 423 if (power == 0) 424 return; 425 /* Set voltage. */ 426 switch (1 << power) { 427 case MMC_OCR_LOW_VOLTAGE: 428 pwr |= SDHCI_POWER_180; 429 break; 430 case MMC_OCR_290_300: 431 case MMC_OCR_300_310: 432 pwr |= SDHCI_POWER_300; 433 break; 434 case MMC_OCR_320_330: 435 case MMC_OCR_330_340: 436 pwr |= SDHCI_POWER_330; 437 break; 438 } 439 WR1(slot, SDHCI_POWER_CONTROL, pwr); 440 /* 441 * Turn on VDD1 power. Note that at least some Intel controllers can 442 * fail to enable bus power on the first try after transiting from D3 443 * to D0, so we give them up to 2 ms. 444 */ 445 pwr |= SDHCI_POWER_ON; 446 for (i = 0; i < 20; i++) { 447 WR1(slot, SDHCI_POWER_CONTROL, pwr); 448 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 449 break; 450 DELAY(100); 451 } 452 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 453 slot_printf(slot, "Bus power failed to enable"); 454 455 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 456 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 457 DELAY(10); 458 WR1(slot, SDHCI_POWER_CONTROL, pwr); 459 DELAY(300); 460 } 461 } 462 463 static void 464 sdhci_read_block_pio(struct sdhci_slot *slot) 465 { 466 uint32_t data; 467 char *buffer; 468 size_t left; 469 470 buffer = slot->curcmd->data->data; 471 buffer += slot->offset; 472 /* Transfer one block at a time. */ 473 left = min(512, slot->curcmd->data->len - slot->offset); 474 slot->offset += left; 475 476 /* If we are too fast, broken controllers return zeroes. */ 477 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 478 DELAY(10); 479 /* Handle unaligned and aligned buffer cases. */ 480 if ((intptr_t)buffer & 3) { 481 while (left > 3) { 482 data = RD4(slot, SDHCI_BUFFER); 483 buffer[0] = data; 484 buffer[1] = (data >> 8); 485 buffer[2] = (data >> 16); 486 buffer[3] = (data >> 24); 487 buffer += 4; 488 left -= 4; 489 } 490 } else { 491 RD_MULTI_4(slot, SDHCI_BUFFER, 492 (uint32_t *)buffer, left >> 2); 493 left &= 3; 494 } 495 /* Handle uneven size case. */ 496 if (left > 0) { 497 data = RD4(slot, SDHCI_BUFFER); 498 while (left > 0) { 499 *(buffer++) = data; 500 data >>= 8; 501 left--; 502 } 503 } 504 } 505 506 static void 507 sdhci_write_block_pio(struct sdhci_slot *slot) 508 { 509 uint32_t data = 0; 510 char *buffer; 511 size_t left; 512 513 buffer = slot->curcmd->data->data; 514 buffer += slot->offset; 515 /* Transfer one block at a time. */ 516 left = min(512, slot->curcmd->data->len - slot->offset); 517 slot->offset += left; 518 519 /* Handle unaligned and aligned buffer cases. */ 520 if ((intptr_t)buffer & 3) { 521 while (left > 3) { 522 data = buffer[0] + 523 (buffer[1] << 8) + 524 (buffer[2] << 16) + 525 (buffer[3] << 24); 526 left -= 4; 527 buffer += 4; 528 WR4(slot, SDHCI_BUFFER, data); 529 } 530 } else { 531 WR_MULTI_4(slot, SDHCI_BUFFER, 532 (uint32_t *)buffer, left >> 2); 533 left &= 3; 534 } 535 /* Handle uneven size case. */ 536 if (left > 0) { 537 while (left > 0) { 538 data <<= 8; 539 data += *(buffer++); 540 left--; 541 } 542 WR4(slot, SDHCI_BUFFER, data); 543 } 544 } 545 546 static void 547 sdhci_transfer_pio(struct sdhci_slot *slot) 548 { 549 550 /* Read as many blocks as possible. */ 551 if (slot->curcmd->data->flags & MMC_DATA_READ) { 552 while (RD4(slot, SDHCI_PRESENT_STATE) & 553 SDHCI_DATA_AVAILABLE) { 554 sdhci_read_block_pio(slot); 555 if (slot->offset >= slot->curcmd->data->len) 556 break; 557 } 558 } else { 559 while (RD4(slot, SDHCI_PRESENT_STATE) & 560 SDHCI_SPACE_AVAILABLE) { 561 sdhci_write_block_pio(slot); 562 if (slot->offset >= slot->curcmd->data->len) 563 break; 564 } 565 } 566 } 567 568 static void 569 sdhci_card_task(void *arg, int pending __unused) 570 { 571 struct sdhci_slot *slot = arg; 572 device_t d; 573 574 SDHCI_LOCK(slot); 575 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 576 #ifdef MMCCAM 577 if (slot->card_present == 0) { 578 #else 579 if (slot->dev == NULL) { 580 #endif 581 /* If card is present - attach mmc bus. */ 582 if (bootverbose || sdhci_debug) 583 slot_printf(slot, "Card inserted\n"); 584 #ifdef MMCCAM 585 slot->card_present = 1; 586 union ccb *ccb; 587 uint32_t pathid; 588 pathid = cam_sim_path(slot->sim); 589 ccb = xpt_alloc_ccb_nowait(); 590 if (ccb == NULL) { 591 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 592 SDHCI_UNLOCK(slot); 593 return; 594 } 595 596 /* 597 * We create a rescan request for BUS:0:0, since the card 598 * will be at lun 0. 599 */ 600 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 601 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 602 slot_printf(slot, "Unable to create path for rescan\n"); 603 SDHCI_UNLOCK(slot); 604 xpt_free_ccb(ccb); 605 return; 606 } 607 SDHCI_UNLOCK(slot); 608 xpt_rescan(ccb); 609 #else 610 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 611 SDHCI_UNLOCK(slot); 612 if (d) { 613 device_set_ivars(d, slot); 614 (void)device_probe_and_attach(d); 615 } 616 #endif 617 } else 618 SDHCI_UNLOCK(slot); 619 } else { 620 #ifdef MMCCAM 621 if (slot->card_present == 1) { 622 #else 623 if (slot->dev != NULL) { 624 #endif 625 /* If no card present - detach mmc bus. */ 626 if (bootverbose || sdhci_debug) 627 slot_printf(slot, "Card removed\n"); 628 d = slot->dev; 629 slot->dev = NULL; 630 #ifdef MMCCAM 631 slot->card_present = 0; 632 union ccb *ccb; 633 uint32_t pathid; 634 pathid = cam_sim_path(slot->sim); 635 ccb = xpt_alloc_ccb_nowait(); 636 if (ccb == NULL) { 637 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 638 SDHCI_UNLOCK(slot); 639 return; 640 } 641 642 /* 643 * We create a rescan request for BUS:0:0, since the card 644 * will be at lun 0. 645 */ 646 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 647 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 648 slot_printf(slot, "Unable to create path for rescan\n"); 649 SDHCI_UNLOCK(slot); 650 xpt_free_ccb(ccb); 651 return; 652 } 653 SDHCI_UNLOCK(slot); 654 xpt_rescan(ccb); 655 #else 656 slot->intmask &= ~sdhci_tuning_intmask(slot); 657 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 658 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 659 slot->opt &= ~SDHCI_TUNING_ENABLED; 660 SDHCI_UNLOCK(slot); 661 callout_drain(&slot->retune_callout); 662 device_delete_child(slot->bus, d); 663 #endif 664 } else 665 SDHCI_UNLOCK(slot); 666 } 667 } 668 669 static void 670 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 671 { 672 bool was_present; 673 674 /* 675 * If there was no card and now there is one, schedule the task to 676 * create the child device after a short delay. The delay is to 677 * debounce the card insert (sometimes the card detect pin stabilizes 678 * before the other pins have made good contact). 679 * 680 * If there was a card present and now it's gone, immediately schedule 681 * the task to delete the child device. No debouncing -- gone is gone, 682 * because once power is removed, a full card re-init is needed, and 683 * that happens by deleting and recreating the child device. 684 */ 685 #ifdef MMCCAM 686 was_present = slot->card_present; 687 #else 688 was_present = slot->dev != NULL; 689 #endif 690 if (!was_present && is_present) { 691 taskqueue_enqueue_timeout(taskqueue_swi_giant, 692 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 693 } else if (was_present && !is_present) { 694 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 695 } 696 } 697 698 void 699 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 700 { 701 702 SDHCI_LOCK(slot); 703 sdhci_handle_card_present_locked(slot, is_present); 704 SDHCI_UNLOCK(slot); 705 } 706 707 static void 708 sdhci_card_poll(void *arg) 709 { 710 struct sdhci_slot *slot = arg; 711 712 sdhci_handle_card_present(slot, 713 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 714 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 715 sdhci_card_poll, slot); 716 } 717 718 int 719 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 720 { 721 kobjop_desc_t kobj_desc; 722 kobj_method_t *kobj_method; 723 uint32_t caps, caps2, freq, host_caps; 724 int err; 725 726 SDHCI_LOCK_INIT(slot); 727 728 slot->num = num; 729 slot->bus = dev; 730 731 /* Allocate DMA tag. */ 732 err = bus_dma_tag_create(bus_get_dma_tag(dev), 733 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 734 BUS_SPACE_MAXADDR, NULL, NULL, 735 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 736 BUS_DMA_ALLOCNOW, NULL, NULL, 737 &slot->dmatag); 738 if (err != 0) { 739 device_printf(dev, "Can't create DMA tag\n"); 740 SDHCI_LOCK_DESTROY(slot); 741 return (err); 742 } 743 /* Allocate DMA memory. */ 744 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 745 BUS_DMA_NOWAIT, &slot->dmamap); 746 if (err != 0) { 747 device_printf(dev, "Can't alloc DMA memory\n"); 748 bus_dma_tag_destroy(slot->dmatag); 749 SDHCI_LOCK_DESTROY(slot); 750 return (err); 751 } 752 /* Map the memory. */ 753 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 754 (void *)slot->dmamem, DMA_BLOCK_SIZE, 755 sdhci_getaddr, &slot->paddr, 0); 756 if (err != 0 || slot->paddr == 0) { 757 device_printf(dev, "Can't load DMA memory\n"); 758 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 759 bus_dma_tag_destroy(slot->dmatag); 760 SDHCI_LOCK_DESTROY(slot); 761 if (err) 762 return (err); 763 else 764 return (EFAULT); 765 } 766 767 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 768 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 769 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 770 caps = slot->caps; 771 caps2 = slot->caps2; 772 } else { 773 caps = RD4(slot, SDHCI_CAPABILITIES); 774 if (slot->version >= SDHCI_SPEC_300) 775 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 776 else 777 caps2 = 0; 778 } 779 if (slot->version >= SDHCI_SPEC_300) { 780 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 781 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 782 device_printf(dev, 783 "Driver doesn't support shared bus slots\n"); 784 bus_dmamap_unload(slot->dmatag, slot->dmamap); 785 bus_dmamem_free(slot->dmatag, slot->dmamem, 786 slot->dmamap); 787 bus_dma_tag_destroy(slot->dmatag); 788 SDHCI_LOCK_DESTROY(slot); 789 return (ENXIO); 790 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 791 SDHCI_SLOTTYPE_EMBEDDED) { 792 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 793 } 794 } 795 /* Calculate base clock frequency. */ 796 if (slot->version >= SDHCI_SPEC_300) 797 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 798 SDHCI_CLOCK_BASE_SHIFT; 799 else 800 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 801 SDHCI_CLOCK_BASE_SHIFT; 802 if (freq != 0) 803 slot->max_clk = freq * 1000000; 804 /* 805 * If the frequency wasn't in the capabilities and the hardware driver 806 * hasn't already set max_clk we're probably not going to work right 807 * with an assumption, so complain about it. 808 */ 809 if (slot->max_clk == 0) { 810 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 811 device_printf(dev, "Hardware doesn't specify base clock " 812 "frequency, using %dMHz as default.\n", 813 SDHCI_DEFAULT_MAX_FREQ); 814 } 815 /* Calculate/set timeout clock frequency. */ 816 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 817 slot->timeout_clk = slot->max_clk / 1000; 818 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 819 slot->timeout_clk = 1000; 820 } else { 821 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 822 SDHCI_TIMEOUT_CLK_SHIFT; 823 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 824 slot->timeout_clk *= 1000; 825 } 826 /* 827 * If the frequency wasn't in the capabilities and the hardware driver 828 * hasn't already set timeout_clk we'll probably work okay using the 829 * max timeout, but still mention it. 830 */ 831 if (slot->timeout_clk == 0) { 832 device_printf(dev, "Hardware doesn't specify timeout clock " 833 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 834 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 835 } 836 837 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 838 slot->host.f_max = slot->max_clk; 839 slot->host.host_ocr = 0; 840 if (caps & SDHCI_CAN_VDD_330) 841 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 842 if (caps & SDHCI_CAN_VDD_300) 843 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 844 /* 1.8V VDD is not supposed to be used for removable cards. */ 845 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) 846 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 847 if (slot->host.host_ocr == 0) { 848 device_printf(dev, "Hardware doesn't report any " 849 "support voltages.\n"); 850 } 851 852 host_caps = MMC_CAP_4_BIT_DATA; 853 if (caps & SDHCI_CAN_DO_8BITBUS) 854 host_caps |= MMC_CAP_8_BIT_DATA; 855 if (caps & SDHCI_CAN_DO_HISPD) 856 host_caps |= MMC_CAP_HSPEED; 857 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 858 host_caps |= MMC_CAP_BOOT_NOACC; 859 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 860 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 861 862 /* Determine supported UHS-I and eMMC modes. */ 863 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 864 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 865 if (caps2 & SDHCI_CAN_SDR104) { 866 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 867 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 868 host_caps |= MMC_CAP_MMC_HS200; 869 } else if (caps2 & SDHCI_CAN_SDR50) 870 host_caps |= MMC_CAP_UHS_SDR50; 871 if (caps2 & SDHCI_CAN_DDR50 && 872 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 873 host_caps |= MMC_CAP_UHS_DDR50; 874 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 875 host_caps |= MMC_CAP_MMC_DDR52; 876 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 877 caps2 & SDHCI_CAN_MMC_HS400) 878 host_caps |= MMC_CAP_MMC_HS400; 879 880 /* 881 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 882 * default NULL implementation. 883 */ 884 kobj_desc = &sdhci_set_uhs_timing_desc; 885 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 886 kobj_desc); 887 if (kobj_method == &kobj_desc->deflt) 888 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 889 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 890 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 891 892 #define SDHCI_CAP_MODES_TUNING(caps2) \ 893 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 894 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 895 MMC_CAP_MMC_HS400) 896 897 /* 898 * Disable UHS-I and eMMC modes that require (re-)tuning if either 899 * the tune or re-tune method is the default NULL implementation. 900 */ 901 kobj_desc = &mmcbr_tune_desc; 902 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 903 kobj_desc); 904 if (kobj_method == &kobj_desc->deflt) 905 goto no_tuning; 906 kobj_desc = &mmcbr_retune_desc; 907 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 908 kobj_desc); 909 if (kobj_method == &kobj_desc->deflt) { 910 no_tuning: 911 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 912 } 913 914 /* Allocate tuning structures and determine tuning parameters. */ 915 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 916 slot->opt |= SDHCI_TUNING_SUPPORTED; 917 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 918 M_WAITOK); 919 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 920 M_WAITOK); 921 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 922 M_WAITOK); 923 if (caps2 & SDHCI_TUNE_SDR50) 924 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 925 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 926 SDHCI_RETUNE_MODES_SHIFT; 927 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 928 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 929 SDHCI_RETUNE_CNT_SHIFT; 930 if (slot->retune_count > 0xb) { 931 device_printf(dev, "Unknown re-tuning count " 932 "%x, using 1 sec\n", slot->retune_count); 933 slot->retune_count = 1; 934 } else if (slot->retune_count != 0) 935 slot->retune_count = 936 1 << (slot->retune_count - 1); 937 } 938 } 939 940 #undef SDHCI_CAP_MODES_TUNING 941 942 /* Determine supported VCCQ signaling levels. */ 943 host_caps |= MMC_CAP_SIGNALING_330; 944 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 945 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 946 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 947 MMC_CAP_MMC_HS400_180)) 948 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 949 950 /* 951 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 952 * default NULL implementation. Disable 1.2 V support if it's the 953 * generic SDHCI implementation. 954 */ 955 kobj_desc = &mmcbr_switch_vccq_desc; 956 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 957 kobj_desc); 958 if (kobj_method == &kobj_desc->deflt) 959 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 960 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 961 host_caps &= ~MMC_CAP_SIGNALING_120; 962 963 /* Determine supported driver types (type B is always mandatory). */ 964 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 965 host_caps |= MMC_CAP_DRIVER_TYPE_A; 966 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 967 host_caps |= MMC_CAP_DRIVER_TYPE_C; 968 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 969 host_caps |= MMC_CAP_DRIVER_TYPE_D; 970 slot->host.caps = host_caps; 971 972 /* Decide if we have usable DMA. */ 973 if (caps & SDHCI_CAN_DO_DMA) 974 slot->opt |= SDHCI_HAVE_DMA; 975 976 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 977 slot->opt &= ~SDHCI_HAVE_DMA; 978 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 979 slot->opt |= SDHCI_HAVE_DMA; 980 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 981 slot->opt |= SDHCI_NON_REMOVABLE; 982 983 /* 984 * Use platform-provided transfer backend 985 * with PIO as a fallback mechanism 986 */ 987 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 988 slot->opt &= ~SDHCI_HAVE_DMA; 989 990 if (bootverbose || sdhci_debug) { 991 slot_printf(slot, 992 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 993 slot->max_clk / 1000000, 994 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 995 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 996 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 997 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 998 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 999 ((caps & SDHCI_CAN_VDD_180) && 1000 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 1001 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 1002 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 1003 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 1004 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 1005 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 1006 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 1007 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 1008 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 1009 "removable"); 1010 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 1011 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 1012 slot_printf(slot, "eMMC:%s%s%s%s\n", 1013 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 1014 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 1015 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 1016 ((host_caps & 1017 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 1018 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 1019 " HS400ES" : ""); 1020 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1021 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 1022 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 1023 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 1024 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 1025 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 1026 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 1027 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 1028 if (slot->opt & SDHCI_TUNING_SUPPORTED) 1029 slot_printf(slot, "Re-tuning count %d secs, mode %d\n", 1030 slot->retune_count, slot->retune_mode + 1); 1031 sdhci_dumpregs(slot); 1032 } 1033 1034 slot->timeout = 10; 1035 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1036 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1037 "timeout", CTLFLAG_RW, &slot->timeout, 0, 1038 "Maximum timeout for SDHCI transfers (in secs)"); 1039 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1040 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1041 sdhci_card_task, slot); 1042 callout_init(&slot->card_poll_callout, 1); 1043 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1044 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1045 1046 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1047 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1048 callout_reset(&slot->card_poll_callout, 1049 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1050 } 1051 1052 sdhci_init(slot); 1053 1054 return (0); 1055 } 1056 1057 #ifndef MMCCAM 1058 void 1059 sdhci_start_slot(struct sdhci_slot *slot) 1060 { 1061 1062 sdhci_card_task(slot, 0); 1063 } 1064 #endif 1065 1066 int 1067 sdhci_cleanup_slot(struct sdhci_slot *slot) 1068 { 1069 device_t d; 1070 1071 callout_drain(&slot->timeout_callout); 1072 callout_drain(&slot->card_poll_callout); 1073 callout_drain(&slot->retune_callout); 1074 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1075 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1076 1077 SDHCI_LOCK(slot); 1078 d = slot->dev; 1079 slot->dev = NULL; 1080 SDHCI_UNLOCK(slot); 1081 if (d != NULL) 1082 device_delete_child(slot->bus, d); 1083 1084 SDHCI_LOCK(slot); 1085 sdhci_reset(slot, SDHCI_RESET_ALL); 1086 SDHCI_UNLOCK(slot); 1087 bus_dmamap_unload(slot->dmatag, slot->dmamap); 1088 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 1089 bus_dma_tag_destroy(slot->dmatag); 1090 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1091 free(slot->tune_req, M_DEVBUF); 1092 free(slot->tune_cmd, M_DEVBUF); 1093 free(slot->tune_data, M_DEVBUF); 1094 } 1095 1096 SDHCI_LOCK_DESTROY(slot); 1097 1098 return (0); 1099 } 1100 1101 int 1102 sdhci_generic_suspend(struct sdhci_slot *slot) 1103 { 1104 1105 /* 1106 * We expect the MMC layer to issue initial tuning after resume. 1107 * Otherwise, we'd need to indicate re-tuning including circuit reset 1108 * being required at least for re-tuning modes 1 and 2 ourselves. 1109 */ 1110 callout_drain(&slot->retune_callout); 1111 SDHCI_LOCK(slot); 1112 slot->opt &= ~SDHCI_TUNING_ENABLED; 1113 sdhci_reset(slot, SDHCI_RESET_ALL); 1114 SDHCI_UNLOCK(slot); 1115 1116 return (0); 1117 } 1118 1119 int 1120 sdhci_generic_resume(struct sdhci_slot *slot) 1121 { 1122 1123 SDHCI_LOCK(slot); 1124 sdhci_init(slot); 1125 SDHCI_UNLOCK(slot); 1126 1127 return (0); 1128 } 1129 1130 uint32_t 1131 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1132 { 1133 1134 if (slot->version >= SDHCI_SPEC_300) 1135 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1136 else 1137 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1138 } 1139 1140 bool 1141 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1142 { 1143 1144 if (slot->opt & SDHCI_NON_REMOVABLE) 1145 return true; 1146 1147 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1148 } 1149 1150 void 1151 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1152 { 1153 struct mmc_ios *ios; 1154 uint16_t hostctrl2; 1155 1156 if (slot->version < SDHCI_SPEC_300) 1157 return; 1158 1159 SDHCI_ASSERT_LOCKED(slot); 1160 ios = &slot->host.ios; 1161 sdhci_set_clock(slot, 0); 1162 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1163 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1164 if (ios->clock > SD_SDR50_MAX) { 1165 if (ios->timing == bus_timing_mmc_hs400 || 1166 ios->timing == bus_timing_mmc_hs400es) 1167 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1168 else 1169 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1170 } 1171 else if (ios->clock > SD_SDR25_MAX) 1172 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1173 else if (ios->clock > SD_SDR12_MAX) { 1174 if (ios->timing == bus_timing_uhs_ddr50 || 1175 ios->timing == bus_timing_mmc_ddr52) 1176 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1177 else 1178 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1179 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1180 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1181 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1182 sdhci_set_clock(slot, ios->clock); 1183 } 1184 1185 int 1186 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1187 { 1188 struct sdhci_slot *slot = device_get_ivars(reqdev); 1189 struct mmc_ios *ios = &slot->host.ios; 1190 1191 SDHCI_LOCK(slot); 1192 /* Do full reset on bus power down to clear from any state. */ 1193 if (ios->power_mode == power_off) { 1194 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1195 sdhci_init(slot); 1196 } 1197 /* Configure the bus. */ 1198 sdhci_set_clock(slot, ios->clock); 1199 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1200 if (ios->bus_width == bus_width_8) { 1201 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1202 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1203 } else if (ios->bus_width == bus_width_4) { 1204 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1205 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1206 } else if (ios->bus_width == bus_width_1) { 1207 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1208 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1209 } else { 1210 panic("Invalid bus width: %d", ios->bus_width); 1211 } 1212 if (ios->clock > SD_SDR12_MAX && 1213 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1214 slot->hostctrl |= SDHCI_CTRL_HISPD; 1215 else 1216 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1217 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1218 SDHCI_SET_UHS_TIMING(brdev, slot); 1219 /* Some controllers like reset after bus changes. */ 1220 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1221 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1222 1223 SDHCI_UNLOCK(slot); 1224 return (0); 1225 } 1226 1227 int 1228 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1229 { 1230 struct sdhci_slot *slot = device_get_ivars(reqdev); 1231 enum mmc_vccq vccq; 1232 int err; 1233 uint16_t hostctrl2; 1234 1235 if (slot->version < SDHCI_SPEC_300) 1236 return (0); 1237 1238 err = 0; 1239 vccq = slot->host.ios.vccq; 1240 SDHCI_LOCK(slot); 1241 sdhci_set_clock(slot, 0); 1242 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1243 switch (vccq) { 1244 case vccq_330: 1245 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1246 goto done; 1247 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1248 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1249 DELAY(5000); 1250 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1251 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1252 goto done; 1253 err = EAGAIN; 1254 break; 1255 case vccq_180: 1256 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1257 err = EINVAL; 1258 goto done; 1259 } 1260 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1261 goto done; 1262 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1263 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1264 DELAY(5000); 1265 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1266 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1267 goto done; 1268 err = EAGAIN; 1269 break; 1270 default: 1271 slot_printf(slot, 1272 "Attempt to set unsupported signaling voltage\n"); 1273 err = EINVAL; 1274 break; 1275 } 1276 done: 1277 sdhci_set_clock(slot, slot->host.ios.clock); 1278 SDHCI_UNLOCK(slot); 1279 return (err); 1280 } 1281 1282 int 1283 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1284 { 1285 struct sdhci_slot *slot = device_get_ivars(reqdev); 1286 struct mmc_ios *ios = &slot->host.ios; 1287 struct mmc_command *tune_cmd; 1288 struct mmc_data *tune_data; 1289 uint32_t opcode; 1290 int err; 1291 1292 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1293 return (0); 1294 1295 slot->retune_ticks = slot->retune_count * hz; 1296 opcode = MMC_SEND_TUNING_BLOCK; 1297 SDHCI_LOCK(slot); 1298 switch (ios->timing) { 1299 case bus_timing_mmc_hs400: 1300 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1301 SDHCI_UNLOCK(slot); 1302 return (EINVAL); 1303 case bus_timing_mmc_hs200: 1304 /* 1305 * In HS400 mode, controllers use the data strobe line to 1306 * latch data from the devices so periodic re-tuning isn't 1307 * expected to be required. 1308 */ 1309 if (hs400) 1310 slot->retune_ticks = 0; 1311 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1312 break; 1313 case bus_timing_uhs_ddr50: 1314 case bus_timing_uhs_sdr104: 1315 break; 1316 case bus_timing_uhs_sdr50: 1317 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1318 break; 1319 /* FALLTHROUGH */ 1320 default: 1321 SDHCI_UNLOCK(slot); 1322 return (0); 1323 } 1324 1325 tune_cmd = slot->tune_cmd; 1326 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1327 tune_cmd->opcode = opcode; 1328 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1329 tune_data = tune_cmd->data = slot->tune_data; 1330 memset(tune_data, 0, sizeof(*tune_data)); 1331 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1332 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1333 MMC_TUNING_LEN; 1334 tune_data->flags = MMC_DATA_READ; 1335 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1336 1337 slot->opt &= ~SDHCI_TUNING_ENABLED; 1338 err = sdhci_exec_tuning(slot, true); 1339 if (err == 0) { 1340 slot->opt |= SDHCI_TUNING_ENABLED; 1341 slot->intmask |= sdhci_tuning_intmask(slot); 1342 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1343 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1344 if (slot->retune_ticks) { 1345 callout_reset(&slot->retune_callout, slot->retune_ticks, 1346 sdhci_retune, slot); 1347 } 1348 } 1349 SDHCI_UNLOCK(slot); 1350 return (err); 1351 } 1352 1353 int 1354 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1355 { 1356 struct sdhci_slot *slot = device_get_ivars(reqdev); 1357 int err; 1358 1359 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1360 return (0); 1361 1362 /* HS400 must be tuned in HS200 mode. */ 1363 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1364 return (EINVAL); 1365 1366 SDHCI_LOCK(slot); 1367 err = sdhci_exec_tuning(slot, reset); 1368 /* 1369 * There are two ways sdhci_exec_tuning() can fail: 1370 * EBUSY should not actually happen when requests are only issued 1371 * with the host properly acquired, and 1372 * EIO re-tuning failed (but it did work initially). 1373 * 1374 * In both cases, we should retry at later point if periodic re-tuning 1375 * is enabled. Note that due to slot->retune_req not being cleared in 1376 * these failure cases, the MMC layer should trigger another attempt at 1377 * re-tuning with the next request anyway, though. 1378 */ 1379 if (slot->retune_ticks) { 1380 callout_reset(&slot->retune_callout, slot->retune_ticks, 1381 sdhci_retune, slot); 1382 } 1383 SDHCI_UNLOCK(slot); 1384 return (err); 1385 } 1386 1387 static int 1388 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1389 { 1390 struct mmc_request *tune_req; 1391 struct mmc_command *tune_cmd; 1392 int i; 1393 uint32_t intmask; 1394 uint16_t hostctrl2; 1395 u_char opt; 1396 1397 SDHCI_ASSERT_LOCKED(slot); 1398 if (slot->req != NULL) 1399 return (EBUSY); 1400 1401 /* Tuning doesn't work with DMA enabled. */ 1402 opt = slot->opt; 1403 slot->opt = opt & ~SDHCI_HAVE_DMA; 1404 1405 /* 1406 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1407 * kind of interrupt we receive in response to a tuning request. 1408 */ 1409 intmask = slot->intmask; 1410 slot->intmask = SDHCI_INT_DATA_AVAIL; 1411 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL); 1412 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1413 1414 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1415 if (reset) 1416 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1417 else 1418 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1419 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1420 1421 tune_req = slot->tune_req; 1422 tune_cmd = slot->tune_cmd; 1423 for (i = 0; i < MMC_TUNING_MAX; i++) { 1424 memset(tune_req, 0, sizeof(*tune_req)); 1425 tune_req->cmd = tune_cmd; 1426 tune_req->done = sdhci_req_wakeup; 1427 tune_req->done_data = slot; 1428 slot->req = tune_req; 1429 slot->flags = 0; 1430 sdhci_start(slot); 1431 while (!(tune_req->flags & MMC_REQ_DONE)) 1432 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1433 if (!(tune_req->flags & MMC_TUNE_DONE)) 1434 break; 1435 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1436 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1437 break; 1438 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1439 DELAY(1000); 1440 } 1441 1442 /* 1443 * Restore DMA usage and interrupts. 1444 * Note that the interrupt aggregation code might have cleared 1445 * SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE in slot->intmask 1446 * and SDHCI_SIGNAL_ENABLE respectively so ensure SDHCI_INT_ENABLE 1447 * doesn't lose these. 1448 */ 1449 slot->opt = opt; 1450 slot->intmask = intmask; 1451 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END | 1452 SDHCI_INT_RESPONSE); 1453 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1454 1455 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1456 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1457 slot->retune_req = 0; 1458 return (0); 1459 } 1460 1461 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1462 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1463 SDHCI_CTRL2_SAMPLING_CLOCK)); 1464 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1465 return (EIO); 1466 } 1467 1468 static void 1469 sdhci_retune(void *arg) 1470 { 1471 struct sdhci_slot *slot = arg; 1472 1473 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1474 } 1475 1476 #ifdef MMCCAM 1477 static void 1478 sdhci_req_done(struct sdhci_slot *slot) 1479 { 1480 union ccb *ccb; 1481 1482 if (__predict_false(sdhci_debug > 1)) 1483 slot_printf(slot, "%s\n", __func__); 1484 if (slot->ccb != NULL && slot->curcmd != NULL) { 1485 callout_stop(&slot->timeout_callout); 1486 ccb = slot->ccb; 1487 slot->ccb = NULL; 1488 slot->curcmd = NULL; 1489 1490 /* Tell CAM the request is finished */ 1491 struct ccb_mmcio *mmcio; 1492 mmcio = &ccb->mmcio; 1493 1494 ccb->ccb_h.status = 1495 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1496 xpt_done(ccb); 1497 } 1498 } 1499 #else 1500 static void 1501 sdhci_req_done(struct sdhci_slot *slot) 1502 { 1503 struct mmc_request *req; 1504 1505 if (slot->req != NULL && slot->curcmd != NULL) { 1506 callout_stop(&slot->timeout_callout); 1507 req = slot->req; 1508 slot->req = NULL; 1509 slot->curcmd = NULL; 1510 req->done(req); 1511 } 1512 } 1513 #endif 1514 1515 static void 1516 sdhci_req_wakeup(struct mmc_request *req) 1517 { 1518 struct sdhci_slot *slot; 1519 1520 slot = req->done_data; 1521 req->flags |= MMC_REQ_DONE; 1522 wakeup(req); 1523 } 1524 1525 static void 1526 sdhci_timeout(void *arg) 1527 { 1528 struct sdhci_slot *slot = arg; 1529 1530 if (slot->curcmd != NULL) { 1531 slot_printf(slot, "Controller timeout\n"); 1532 sdhci_dumpregs(slot); 1533 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1534 slot->curcmd->error = MMC_ERR_TIMEOUT; 1535 sdhci_req_done(slot); 1536 } else { 1537 slot_printf(slot, "Spurious timeout - no active command\n"); 1538 } 1539 } 1540 1541 static void 1542 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1543 { 1544 uint16_t mode; 1545 1546 if (data == NULL) 1547 return; 1548 1549 mode = SDHCI_TRNS_BLK_CNT_EN; 1550 if (data->len > 512) 1551 mode |= SDHCI_TRNS_MULTI; 1552 if (data->flags & MMC_DATA_READ) 1553 mode |= SDHCI_TRNS_READ; 1554 #ifdef MMCCAM 1555 struct ccb_mmcio *mmcio; 1556 mmcio = &slot->ccb->mmcio; 1557 if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION 1558 && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1559 mode |= SDHCI_TRNS_ACMD12; 1560 #else 1561 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1562 mode |= SDHCI_TRNS_ACMD12; 1563 #endif 1564 if (slot->flags & SDHCI_USE_DMA) 1565 mode |= SDHCI_TRNS_DMA; 1566 1567 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1568 } 1569 1570 static void 1571 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1572 { 1573 int flags, timeout; 1574 uint32_t mask; 1575 1576 slot->curcmd = cmd; 1577 slot->cmd_done = 0; 1578 1579 cmd->error = MMC_ERR_NONE; 1580 1581 /* This flags combination is not supported by controller. */ 1582 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1583 slot_printf(slot, "Unsupported response type!\n"); 1584 cmd->error = MMC_ERR_FAILED; 1585 sdhci_req_done(slot); 1586 return; 1587 } 1588 1589 /* 1590 * Do not issue command if there is no card, clock or power. 1591 * Controller will not detect timeout without clock active. 1592 */ 1593 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1594 slot->power == 0 || 1595 slot->clock == 0) { 1596 slot_printf(slot, 1597 "Cannot issue a command (power=%d clock=%d)", 1598 slot->power, slot->clock); 1599 cmd->error = MMC_ERR_FAILED; 1600 sdhci_req_done(slot); 1601 return; 1602 } 1603 /* Always wait for free CMD bus. */ 1604 mask = SDHCI_CMD_INHIBIT; 1605 /* Wait for free DAT if we have data or busy signal. */ 1606 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1607 mask |= SDHCI_DAT_INHIBIT; 1608 /* 1609 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1610 * that these latter are also special in that SDHCI_CMD_DATA should 1611 * be set below but no actual data is ever read from the controller. 1612 */ 1613 #ifdef MMCCAM 1614 if (cmd == &slot->ccb->mmcio.stop || 1615 #else 1616 if (cmd == slot->req->stop || 1617 #endif 1618 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1619 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1620 mask &= ~SDHCI_DAT_INHIBIT; 1621 /* 1622 * Wait for bus no more then 250 ms. Typically there will be no wait 1623 * here at all, but when writing a crash dump we may be bypassing the 1624 * host platform's interrupt handler, and in some cases that handler 1625 * may be working around hardware quirks such as not respecting r1b 1626 * busy indications. In those cases, this wait-loop serves the purpose 1627 * of waiting for the prior command and data transfers to be done, and 1628 * SD cards are allowed to take up to 250ms for write and erase ops. 1629 * (It's usually more like 20-30ms in the real world.) 1630 */ 1631 timeout = 250; 1632 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1633 if (timeout == 0) { 1634 slot_printf(slot, "Controller never released " 1635 "inhibit bit(s).\n"); 1636 sdhci_dumpregs(slot); 1637 cmd->error = MMC_ERR_FAILED; 1638 sdhci_req_done(slot); 1639 return; 1640 } 1641 timeout--; 1642 DELAY(1000); 1643 } 1644 1645 /* Prepare command flags. */ 1646 if (!(cmd->flags & MMC_RSP_PRESENT)) 1647 flags = SDHCI_CMD_RESP_NONE; 1648 else if (cmd->flags & MMC_RSP_136) 1649 flags = SDHCI_CMD_RESP_LONG; 1650 else if (cmd->flags & MMC_RSP_BUSY) 1651 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1652 else 1653 flags = SDHCI_CMD_RESP_SHORT; 1654 if (cmd->flags & MMC_RSP_CRC) 1655 flags |= SDHCI_CMD_CRC; 1656 if (cmd->flags & MMC_RSP_OPCODE) 1657 flags |= SDHCI_CMD_INDEX; 1658 if (cmd->data != NULL) 1659 flags |= SDHCI_CMD_DATA; 1660 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1661 flags |= SDHCI_CMD_TYPE_ABORT; 1662 /* Prepare data. */ 1663 sdhci_start_data(slot, cmd->data); 1664 /* 1665 * Interrupt aggregation: To reduce total number of interrupts 1666 * group response interrupt with data interrupt when possible. 1667 * If there going to be data interrupt, mask response one. 1668 */ 1669 if (slot->data_done == 0) { 1670 WR4(slot, SDHCI_SIGNAL_ENABLE, 1671 slot->intmask &= ~SDHCI_INT_RESPONSE); 1672 } 1673 /* Set command argument. */ 1674 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1675 /* Set data transfer mode. */ 1676 sdhci_set_transfer_mode(slot, cmd->data); 1677 if (__predict_false(sdhci_debug > 1)) 1678 slot_printf(slot, "Starting command!\n"); 1679 /* Start command. */ 1680 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1681 /* Start timeout callout. */ 1682 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1683 sdhci_timeout, slot); 1684 } 1685 1686 static void 1687 sdhci_finish_command(struct sdhci_slot *slot) 1688 { 1689 int i; 1690 uint32_t val; 1691 uint8_t extra; 1692 1693 if (__predict_false(sdhci_debug > 1)) 1694 slot_printf(slot, "%s: called, err %d flags %d\n", 1695 __func__, slot->curcmd->error, slot->curcmd->flags); 1696 slot->cmd_done = 1; 1697 /* 1698 * Interrupt aggregation: Restore command interrupt. 1699 * Main restore point for the case when command interrupt 1700 * happened first. 1701 */ 1702 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1703 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1704 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1705 SDHCI_INT_RESPONSE); 1706 /* In case of error - reset host and return. */ 1707 if (slot->curcmd->error) { 1708 if (slot->curcmd->error == MMC_ERR_BADCRC) 1709 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1710 sdhci_reset(slot, SDHCI_RESET_CMD); 1711 sdhci_reset(slot, SDHCI_RESET_DATA); 1712 sdhci_start(slot); 1713 return; 1714 } 1715 /* If command has response - fetch it. */ 1716 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1717 if (slot->curcmd->flags & MMC_RSP_136) { 1718 /* CRC is stripped so we need one byte shift. */ 1719 extra = 0; 1720 for (i = 0; i < 4; i++) { 1721 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1722 if (slot->quirks & 1723 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1724 slot->curcmd->resp[3 - i] = val; 1725 else { 1726 slot->curcmd->resp[3 - i] = 1727 (val << 8) | extra; 1728 extra = val >> 24; 1729 } 1730 } 1731 } else 1732 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1733 } 1734 if (__predict_false(sdhci_debug > 1)) 1735 printf("Resp: %02x %02x %02x %02x\n", 1736 slot->curcmd->resp[0], slot->curcmd->resp[1], 1737 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1738 1739 /* If data ready - finish. */ 1740 if (slot->data_done) 1741 sdhci_start(slot); 1742 } 1743 1744 static void 1745 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1746 { 1747 uint32_t target_timeout, current_timeout; 1748 uint8_t div; 1749 1750 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1751 slot->data_done = 1; 1752 return; 1753 } 1754 1755 slot->data_done = 0; 1756 1757 /* Calculate and set data timeout.*/ 1758 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1759 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1760 div = 0xE; 1761 } else { 1762 target_timeout = 1000000; 1763 div = 0; 1764 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1765 while (current_timeout < target_timeout && div < 0xE) { 1766 ++div; 1767 current_timeout <<= 1; 1768 } 1769 /* Compensate for an off-by-one error in the CaFe chip.*/ 1770 if (div < 0xE && 1771 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1772 ++div; 1773 } 1774 } 1775 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1776 1777 if (data == NULL) 1778 return; 1779 1780 /* Use DMA if possible. */ 1781 if ((slot->opt & SDHCI_HAVE_DMA)) 1782 slot->flags |= SDHCI_USE_DMA; 1783 /* If data is small, broken DMA may return zeroes instead of data, */ 1784 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1785 (data->len <= 512)) 1786 slot->flags &= ~SDHCI_USE_DMA; 1787 /* Some controllers require even block sizes. */ 1788 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1789 ((data->len) & 0x3)) 1790 slot->flags &= ~SDHCI_USE_DMA; 1791 /* Load DMA buffer. */ 1792 if (slot->flags & SDHCI_USE_DMA) { 1793 if (data->flags & MMC_DATA_READ) 1794 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1795 BUS_DMASYNC_PREREAD); 1796 else { 1797 memcpy(slot->dmamem, data->data, 1798 (data->len < DMA_BLOCK_SIZE) ? 1799 data->len : DMA_BLOCK_SIZE); 1800 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1801 BUS_DMASYNC_PREWRITE); 1802 } 1803 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1804 /* Interrupt aggregation: Mask border interrupt 1805 * for the last page and unmask else. */ 1806 if (data->len == DMA_BLOCK_SIZE) 1807 slot->intmask &= ~SDHCI_INT_DMA_END; 1808 else 1809 slot->intmask |= SDHCI_INT_DMA_END; 1810 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1811 } 1812 /* Current data offset for both PIO and DMA. */ 1813 slot->offset = 0; 1814 /* Set block size and request IRQ on 4K border. */ 1815 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1816 (data->len < 512) ? data->len : 512)); 1817 /* Set block count. */ 1818 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1819 1820 if (__predict_false(sdhci_debug > 1)) 1821 slot_printf(slot, "Block size: %02x, count %lu\n", 1822 (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512), 1823 (unsigned long)(data->len + 511) / 512); 1824 } 1825 1826 void 1827 sdhci_finish_data(struct sdhci_slot *slot) 1828 { 1829 struct mmc_data *data = slot->curcmd->data; 1830 size_t left; 1831 1832 /* Interrupt aggregation: Restore command interrupt. 1833 * Auxiliary restore point for the case when data interrupt 1834 * happened first. */ 1835 if (!slot->cmd_done) { 1836 WR4(slot, SDHCI_SIGNAL_ENABLE, 1837 slot->intmask |= SDHCI_INT_RESPONSE); 1838 } 1839 /* Unload rest of data from DMA buffer. */ 1840 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1841 slot->curcmd->data != NULL) { 1842 if (data->flags & MMC_DATA_READ) { 1843 left = data->len - slot->offset; 1844 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1845 BUS_DMASYNC_POSTREAD); 1846 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1847 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1848 } else 1849 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1850 BUS_DMASYNC_POSTWRITE); 1851 } 1852 slot->data_done = 1; 1853 /* If there was error - reset the host. */ 1854 if (slot->curcmd->error) { 1855 if (slot->curcmd->error == MMC_ERR_BADCRC) 1856 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1857 sdhci_reset(slot, SDHCI_RESET_CMD); 1858 sdhci_reset(slot, SDHCI_RESET_DATA); 1859 sdhci_start(slot); 1860 return; 1861 } 1862 /* If we already have command response - finish. */ 1863 if (slot->cmd_done) 1864 sdhci_start(slot); 1865 } 1866 1867 #ifdef MMCCAM 1868 static void 1869 sdhci_start(struct sdhci_slot *slot) 1870 { 1871 union ccb *ccb; 1872 1873 ccb = slot->ccb; 1874 if (ccb == NULL) 1875 return; 1876 1877 struct ccb_mmcio *mmcio; 1878 mmcio = &ccb->mmcio; 1879 1880 if (!(slot->flags & CMD_STARTED)) { 1881 slot->flags |= CMD_STARTED; 1882 sdhci_start_command(slot, &mmcio->cmd); 1883 return; 1884 } 1885 1886 /* 1887 * Old stack doesn't use this! 1888 * Enabling this code causes significant performance degradation 1889 * and IRQ storms on BBB, Wandboard behaves fine. 1890 * Not using this code does no harm... 1891 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1892 slot->flags |= STOP_STARTED; 1893 sdhci_start_command(slot, &mmcio->stop); 1894 return; 1895 } 1896 */ 1897 if (__predict_false(sdhci_debug > 1)) 1898 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1899 if (mmcio->cmd.error == 0 && 1900 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1901 sdhci_reset(slot, SDHCI_RESET_CMD); 1902 sdhci_reset(slot, SDHCI_RESET_DATA); 1903 } 1904 1905 sdhci_req_done(slot); 1906 } 1907 #else 1908 static void 1909 sdhci_start(struct sdhci_slot *slot) 1910 { 1911 struct mmc_request *req; 1912 1913 req = slot->req; 1914 if (req == NULL) 1915 return; 1916 1917 if (!(slot->flags & CMD_STARTED)) { 1918 slot->flags |= CMD_STARTED; 1919 sdhci_start_command(slot, req->cmd); 1920 return; 1921 } 1922 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1923 !(slot->flags & STOP_STARTED) && req->stop) { 1924 slot->flags |= STOP_STARTED; 1925 sdhci_start_command(slot, req->stop); 1926 return; 1927 } 1928 if (__predict_false(sdhci_debug > 1)) 1929 slot_printf(slot, "result: %d\n", req->cmd->error); 1930 if (!req->cmd->error && 1931 ((slot->curcmd == req->stop && 1932 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1933 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1934 sdhci_reset(slot, SDHCI_RESET_CMD); 1935 sdhci_reset(slot, SDHCI_RESET_DATA); 1936 } 1937 1938 sdhci_req_done(slot); 1939 } 1940 #endif 1941 1942 int 1943 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1944 struct mmc_request *req) 1945 { 1946 struct sdhci_slot *slot = device_get_ivars(reqdev); 1947 1948 SDHCI_LOCK(slot); 1949 if (slot->req != NULL) { 1950 SDHCI_UNLOCK(slot); 1951 return (EBUSY); 1952 } 1953 if (__predict_false(sdhci_debug > 1)) { 1954 slot_printf(slot, 1955 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1956 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1957 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1958 (req->cmd->data)?req->cmd->data->flags:0); 1959 } 1960 slot->req = req; 1961 slot->flags = 0; 1962 sdhci_start(slot); 1963 SDHCI_UNLOCK(slot); 1964 if (dumping) { 1965 while (slot->req != NULL) { 1966 sdhci_generic_intr(slot); 1967 DELAY(10); 1968 } 1969 } 1970 return (0); 1971 } 1972 1973 int 1974 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1975 { 1976 struct sdhci_slot *slot = device_get_ivars(reqdev); 1977 uint32_t val; 1978 1979 SDHCI_LOCK(slot); 1980 val = RD4(slot, SDHCI_PRESENT_STATE); 1981 SDHCI_UNLOCK(slot); 1982 return (!(val & SDHCI_WRITE_PROTECT)); 1983 } 1984 1985 int 1986 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1987 { 1988 struct sdhci_slot *slot = device_get_ivars(reqdev); 1989 int err = 0; 1990 1991 SDHCI_LOCK(slot); 1992 while (slot->bus_busy) 1993 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1994 slot->bus_busy++; 1995 /* Activate led. */ 1996 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1997 SDHCI_UNLOCK(slot); 1998 return (err); 1999 } 2000 2001 int 2002 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 2003 { 2004 struct sdhci_slot *slot = device_get_ivars(reqdev); 2005 2006 SDHCI_LOCK(slot); 2007 /* Deactivate led. */ 2008 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 2009 slot->bus_busy--; 2010 SDHCI_UNLOCK(slot); 2011 wakeup(slot); 2012 return (0); 2013 } 2014 2015 static void 2016 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2017 { 2018 2019 if (!slot->curcmd) { 2020 slot_printf(slot, "Got command interrupt 0x%08x, but " 2021 "there is no active command.\n", intmask); 2022 sdhci_dumpregs(slot); 2023 return; 2024 } 2025 if (intmask & SDHCI_INT_TIMEOUT) 2026 slot->curcmd->error = MMC_ERR_TIMEOUT; 2027 else if (intmask & SDHCI_INT_CRC) 2028 slot->curcmd->error = MMC_ERR_BADCRC; 2029 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2030 slot->curcmd->error = MMC_ERR_FIFO; 2031 2032 sdhci_finish_command(slot); 2033 } 2034 2035 static void 2036 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2037 { 2038 struct mmc_data *data; 2039 size_t left; 2040 2041 if (!slot->curcmd) { 2042 slot_printf(slot, "Got data interrupt 0x%08x, but " 2043 "there is no active command.\n", intmask); 2044 sdhci_dumpregs(slot); 2045 return; 2046 } 2047 if (slot->curcmd->data == NULL && 2048 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2049 slot_printf(slot, "Got data interrupt 0x%08x, but " 2050 "there is no active data operation.\n", 2051 intmask); 2052 sdhci_dumpregs(slot); 2053 return; 2054 } 2055 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2056 slot->curcmd->error = MMC_ERR_TIMEOUT; 2057 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2058 slot->curcmd->error = MMC_ERR_BADCRC; 2059 if (slot->curcmd->data == NULL && 2060 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2061 SDHCI_INT_DMA_END))) { 2062 slot_printf(slot, "Got data interrupt 0x%08x, but " 2063 "there is busy-only command.\n", intmask); 2064 sdhci_dumpregs(slot); 2065 slot->curcmd->error = MMC_ERR_INVALID; 2066 } 2067 if (slot->curcmd->error) { 2068 /* No need to continue after any error. */ 2069 goto done; 2070 } 2071 2072 /* Handle tuning completion interrupt. */ 2073 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2074 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2075 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2076 slot->req->flags |= MMC_TUNE_DONE; 2077 sdhci_finish_command(slot); 2078 sdhci_finish_data(slot); 2079 return; 2080 } 2081 /* Handle PIO interrupt. */ 2082 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2083 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2084 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2085 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2086 &intmask); 2087 slot->flags |= PLATFORM_DATA_STARTED; 2088 } else 2089 sdhci_transfer_pio(slot); 2090 } 2091 /* Handle DMA border. */ 2092 if (intmask & SDHCI_INT_DMA_END) { 2093 data = slot->curcmd->data; 2094 2095 /* Unload DMA buffer ... */ 2096 left = data->len - slot->offset; 2097 if (data->flags & MMC_DATA_READ) { 2098 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2099 BUS_DMASYNC_POSTREAD); 2100 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2101 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 2102 } else { 2103 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2104 BUS_DMASYNC_POSTWRITE); 2105 } 2106 /* ... and reload it again. */ 2107 slot->offset += DMA_BLOCK_SIZE; 2108 left = data->len - slot->offset; 2109 if (data->flags & MMC_DATA_READ) { 2110 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2111 BUS_DMASYNC_PREREAD); 2112 } else { 2113 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2114 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 2115 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2116 BUS_DMASYNC_PREWRITE); 2117 } 2118 /* Interrupt aggregation: Mask border interrupt 2119 * for the last page. */ 2120 if (left == DMA_BLOCK_SIZE) { 2121 slot->intmask &= ~SDHCI_INT_DMA_END; 2122 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2123 } 2124 /* Restart DMA. */ 2125 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2126 } 2127 /* We have got all data. */ 2128 if (intmask & SDHCI_INT_DATA_END) { 2129 if (slot->flags & PLATFORM_DATA_STARTED) { 2130 slot->flags &= ~PLATFORM_DATA_STARTED; 2131 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2132 } else 2133 sdhci_finish_data(slot); 2134 } 2135 done: 2136 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2137 if (slot->flags & PLATFORM_DATA_STARTED) { 2138 slot->flags &= ~PLATFORM_DATA_STARTED; 2139 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2140 } else 2141 sdhci_finish_data(slot); 2142 } 2143 } 2144 2145 static void 2146 sdhci_acmd_irq(struct sdhci_slot *slot) 2147 { 2148 uint16_t err; 2149 2150 err = RD4(slot, SDHCI_ACMD12_ERR); 2151 if (!slot->curcmd) { 2152 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2153 "there is no active command.\n", err); 2154 sdhci_dumpregs(slot); 2155 return; 2156 } 2157 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 2158 sdhci_reset(slot, SDHCI_RESET_CMD); 2159 } 2160 2161 void 2162 sdhci_generic_intr(struct sdhci_slot *slot) 2163 { 2164 uint32_t intmask, present; 2165 2166 SDHCI_LOCK(slot); 2167 /* Read slot interrupt status. */ 2168 intmask = RD4(slot, SDHCI_INT_STATUS); 2169 if (intmask == 0 || intmask == 0xffffffff) { 2170 SDHCI_UNLOCK(slot); 2171 return; 2172 } 2173 if (__predict_false(sdhci_debug > 2)) 2174 slot_printf(slot, "Interrupt %#x\n", intmask); 2175 2176 /* Handle tuning error interrupt. */ 2177 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2178 slot_printf(slot, "Tuning error indicated\n"); 2179 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2180 if (slot->curcmd) { 2181 slot->curcmd->error = MMC_ERR_BADCRC; 2182 sdhci_finish_command(slot); 2183 } 2184 } 2185 /* Handle re-tuning interrupt. */ 2186 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2187 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2188 /* Handle card presence interrupts. */ 2189 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2190 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2191 slot->intmask &= 2192 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2193 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2194 SDHCI_INT_CARD_INSERT; 2195 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2196 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2197 WR4(slot, SDHCI_INT_STATUS, intmask & 2198 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2199 sdhci_handle_card_present_locked(slot, present); 2200 } 2201 /* Handle command interrupts. */ 2202 if (intmask & SDHCI_INT_CMD_MASK) { 2203 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2204 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2205 } 2206 /* Handle data interrupts. */ 2207 if (intmask & SDHCI_INT_DATA_MASK) { 2208 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2209 /* Don't call data_irq in case of errored command. */ 2210 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2211 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2212 } 2213 /* Handle AutoCMD12 error interrupt. */ 2214 if (intmask & SDHCI_INT_ACMD12ERR) { 2215 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2216 sdhci_acmd_irq(slot); 2217 } 2218 /* Handle bus power interrupt. */ 2219 if (intmask & SDHCI_INT_BUS_POWER) { 2220 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2221 slot_printf(slot, "Card is consuming too much power!\n"); 2222 } 2223 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2224 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2225 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2226 /* The rest is unknown. */ 2227 if (intmask) { 2228 WR4(slot, SDHCI_INT_STATUS, intmask); 2229 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2230 intmask); 2231 sdhci_dumpregs(slot); 2232 } 2233 2234 SDHCI_UNLOCK(slot); 2235 } 2236 2237 int 2238 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2239 uintptr_t *result) 2240 { 2241 struct sdhci_slot *slot = device_get_ivars(child); 2242 2243 switch (which) { 2244 default: 2245 return (EINVAL); 2246 case MMCBR_IVAR_BUS_MODE: 2247 *result = slot->host.ios.bus_mode; 2248 break; 2249 case MMCBR_IVAR_BUS_WIDTH: 2250 *result = slot->host.ios.bus_width; 2251 break; 2252 case MMCBR_IVAR_CHIP_SELECT: 2253 *result = slot->host.ios.chip_select; 2254 break; 2255 case MMCBR_IVAR_CLOCK: 2256 *result = slot->host.ios.clock; 2257 break; 2258 case MMCBR_IVAR_F_MIN: 2259 *result = slot->host.f_min; 2260 break; 2261 case MMCBR_IVAR_F_MAX: 2262 *result = slot->host.f_max; 2263 break; 2264 case MMCBR_IVAR_HOST_OCR: 2265 *result = slot->host.host_ocr; 2266 break; 2267 case MMCBR_IVAR_MODE: 2268 *result = slot->host.mode; 2269 break; 2270 case MMCBR_IVAR_OCR: 2271 *result = slot->host.ocr; 2272 break; 2273 case MMCBR_IVAR_POWER_MODE: 2274 *result = slot->host.ios.power_mode; 2275 break; 2276 case MMCBR_IVAR_VDD: 2277 *result = slot->host.ios.vdd; 2278 break; 2279 case MMCBR_IVAR_RETUNE_REQ: 2280 if (slot->opt & SDHCI_TUNING_ENABLED) { 2281 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2282 *result = retune_req_reset; 2283 break; 2284 } 2285 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2286 *result = retune_req_normal; 2287 break; 2288 } 2289 } 2290 *result = retune_req_none; 2291 break; 2292 case MMCBR_IVAR_VCCQ: 2293 *result = slot->host.ios.vccq; 2294 break; 2295 case MMCBR_IVAR_CAPS: 2296 *result = slot->host.caps; 2297 break; 2298 case MMCBR_IVAR_TIMING: 2299 *result = slot->host.ios.timing; 2300 break; 2301 case MMCBR_IVAR_MAX_DATA: 2302 /* 2303 * Re-tuning modes 1 and 2 restrict the maximum data length 2304 * per read/write command to 4 MiB. 2305 */ 2306 if (slot->opt & SDHCI_TUNING_ENABLED && 2307 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2308 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2309 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2310 break; 2311 } 2312 *result = 65535; 2313 break; 2314 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2315 /* 2316 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2317 */ 2318 *result = 1000000; 2319 break; 2320 } 2321 return (0); 2322 } 2323 2324 int 2325 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2326 uintptr_t value) 2327 { 2328 struct sdhci_slot *slot = device_get_ivars(child); 2329 uint32_t clock, max_clock; 2330 int i; 2331 2332 if (sdhci_debug > 1) 2333 slot_printf(slot, "%s: var=%d\n", __func__, which); 2334 switch (which) { 2335 default: 2336 return (EINVAL); 2337 case MMCBR_IVAR_BUS_MODE: 2338 slot->host.ios.bus_mode = value; 2339 break; 2340 case MMCBR_IVAR_BUS_WIDTH: 2341 slot->host.ios.bus_width = value; 2342 break; 2343 case MMCBR_IVAR_CHIP_SELECT: 2344 slot->host.ios.chip_select = value; 2345 break; 2346 case MMCBR_IVAR_CLOCK: 2347 if (value > 0) { 2348 max_clock = slot->max_clk; 2349 clock = max_clock; 2350 2351 if (slot->version < SDHCI_SPEC_300) { 2352 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2353 i <<= 1) { 2354 if (clock <= value) 2355 break; 2356 clock >>= 1; 2357 } 2358 } else { 2359 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2360 i += 2) { 2361 if (clock <= value) 2362 break; 2363 clock = max_clock / (i + 2); 2364 } 2365 } 2366 2367 slot->host.ios.clock = clock; 2368 } else 2369 slot->host.ios.clock = 0; 2370 break; 2371 case MMCBR_IVAR_MODE: 2372 slot->host.mode = value; 2373 break; 2374 case MMCBR_IVAR_OCR: 2375 slot->host.ocr = value; 2376 break; 2377 case MMCBR_IVAR_POWER_MODE: 2378 slot->host.ios.power_mode = value; 2379 break; 2380 case MMCBR_IVAR_VDD: 2381 slot->host.ios.vdd = value; 2382 break; 2383 case MMCBR_IVAR_VCCQ: 2384 slot->host.ios.vccq = value; 2385 break; 2386 case MMCBR_IVAR_TIMING: 2387 slot->host.ios.timing = value; 2388 break; 2389 case MMCBR_IVAR_CAPS: 2390 case MMCBR_IVAR_HOST_OCR: 2391 case MMCBR_IVAR_F_MIN: 2392 case MMCBR_IVAR_F_MAX: 2393 case MMCBR_IVAR_MAX_DATA: 2394 case MMCBR_IVAR_RETUNE_REQ: 2395 return (EINVAL); 2396 } 2397 return (0); 2398 } 2399 2400 #ifdef MMCCAM 2401 void 2402 sdhci_start_slot(struct sdhci_slot *slot) 2403 { 2404 if ((slot->devq = cam_simq_alloc(1)) == NULL) { 2405 goto fail; 2406 } 2407 2408 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2409 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2410 "sdhci_slot", slot, device_get_unit(slot->bus), 2411 &slot->sim_mtx, 1, 1, slot->devq); 2412 2413 if (slot->sim == NULL) { 2414 cam_simq_free(slot->devq); 2415 slot_printf(slot, "cannot allocate CAM SIM\n"); 2416 goto fail; 2417 } 2418 2419 mtx_lock(&slot->sim_mtx); 2420 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2421 slot_printf(slot, 2422 "cannot register SCSI pass-through bus\n"); 2423 cam_sim_free(slot->sim, FALSE); 2424 cam_simq_free(slot->devq); 2425 mtx_unlock(&slot->sim_mtx); 2426 goto fail; 2427 } 2428 2429 mtx_unlock(&slot->sim_mtx); 2430 /* End CAM-specific init */ 2431 slot->card_present = 0; 2432 sdhci_card_task(slot, 0); 2433 return; 2434 2435 fail: 2436 if (slot->sim != NULL) { 2437 mtx_lock(&slot->sim_mtx); 2438 xpt_bus_deregister(cam_sim_path(slot->sim)); 2439 cam_sim_free(slot->sim, FALSE); 2440 mtx_unlock(&slot->sim_mtx); 2441 } 2442 2443 if (slot->devq != NULL) 2444 cam_simq_free(slot->devq); 2445 } 2446 2447 static void 2448 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2449 { 2450 struct sdhci_slot *slot; 2451 2452 slot = cam_sim_softc(sim); 2453 2454 sdhci_cam_request(slot, ccb); 2455 } 2456 2457 void 2458 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2459 { 2460 struct sdhci_slot *slot; 2461 2462 slot = cam_sim_softc(sim); 2463 if (slot == NULL) { 2464 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2465 xpt_done(ccb); 2466 return; 2467 } 2468 2469 mtx_assert(&slot->sim_mtx, MA_OWNED); 2470 2471 switch (ccb->ccb_h.func_code) { 2472 case XPT_PATH_INQ: 2473 { 2474 struct ccb_pathinq *cpi; 2475 2476 cpi = &ccb->cpi; 2477 cpi->version_num = 1; 2478 cpi->hba_inquiry = 0; 2479 cpi->target_sprt = 0; 2480 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2481 cpi->hba_eng_cnt = 0; 2482 cpi->max_target = 0; 2483 cpi->max_lun = 0; 2484 cpi->initiator_id = 1; 2485 cpi->maxio = MAXPHYS; 2486 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2487 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2488 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2489 cpi->unit_number = cam_sim_unit(sim); 2490 cpi->bus_id = cam_sim_bus(sim); 2491 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2492 cpi->protocol = PROTO_MMCSD; 2493 cpi->protocol_version = SCSI_REV_0; 2494 cpi->transport = XPORT_MMCSD; 2495 cpi->transport_version = 0; 2496 2497 cpi->ccb_h.status = CAM_REQ_CMP; 2498 break; 2499 } 2500 case XPT_GET_TRAN_SETTINGS: 2501 { 2502 struct ccb_trans_settings *cts = &ccb->cts; 2503 2504 if (sdhci_debug > 1) 2505 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2506 2507 cts->protocol = PROTO_MMCSD; 2508 cts->protocol_version = 1; 2509 cts->transport = XPORT_MMCSD; 2510 cts->transport_version = 1; 2511 cts->xport_specific.valid = 0; 2512 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2513 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2514 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2515 cts->proto_specific.mmc.host_caps = slot->host.caps; 2516 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2517 ccb->ccb_h.status = CAM_REQ_CMP; 2518 break; 2519 } 2520 case XPT_SET_TRAN_SETTINGS: 2521 { 2522 if (sdhci_debug > 1) 2523 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2524 sdhci_cam_settran_settings(slot, ccb); 2525 ccb->ccb_h.status = CAM_REQ_CMP; 2526 break; 2527 } 2528 case XPT_RESET_BUS: 2529 if (sdhci_debug > 1) 2530 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2531 ccb->ccb_h.status = CAM_REQ_CMP; 2532 break; 2533 case XPT_MMC_IO: 2534 /* 2535 * Here is the HW-dependent part of 2536 * sending the command to the underlying h/w 2537 * At some point in the future an interrupt comes. 2538 * Then the request will be marked as completed. 2539 */ 2540 if (__predict_false(sdhci_debug > 1)) 2541 slot_printf(slot, "Got XPT_MMC_IO\n"); 2542 ccb->ccb_h.status = CAM_REQ_INPROG; 2543 2544 sdhci_cam_handle_mmcio(sim, ccb); 2545 return; 2546 /* NOTREACHED */ 2547 break; 2548 default: 2549 ccb->ccb_h.status = CAM_REQ_INVALID; 2550 break; 2551 } 2552 xpt_done(ccb); 2553 return; 2554 } 2555 2556 void 2557 sdhci_cam_poll(struct cam_sim *sim) 2558 { 2559 return; 2560 } 2561 2562 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) { 2563 int max_clock, clock, i; 2564 2565 if (proposed_clock == 0) 2566 return 0; 2567 max_clock = slot->max_clk; 2568 clock = max_clock; 2569 2570 if (slot->version < SDHCI_SPEC_300) { 2571 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2572 i <<= 1) { 2573 if (clock <= proposed_clock) 2574 break; 2575 clock >>= 1; 2576 } 2577 } else { 2578 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2579 i += 2) { 2580 if (clock <= proposed_clock) 2581 break; 2582 clock = max_clock / (i + 2); 2583 } 2584 } 2585 return clock; 2586 } 2587 2588 int 2589 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2590 { 2591 struct mmc_ios *ios; 2592 struct mmc_ios *new_ios; 2593 struct ccb_trans_settings_mmc *cts; 2594 2595 ios = &slot->host.ios; 2596 2597 cts = &ccb->cts.proto_specific.mmc; 2598 new_ios = &cts->ios; 2599 2600 /* Update only requested fields */ 2601 if (cts->ios_valid & MMC_CLK) { 2602 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2603 slot_printf(slot, "Clock => %d\n", ios->clock); 2604 } 2605 if (cts->ios_valid & MMC_VDD) { 2606 ios->vdd = new_ios->vdd; 2607 slot_printf(slot, "VDD => %d\n", ios->vdd); 2608 } 2609 if (cts->ios_valid & MMC_CS) { 2610 ios->chip_select = new_ios->chip_select; 2611 slot_printf(slot, "CS => %d\n", ios->chip_select); 2612 } 2613 if (cts->ios_valid & MMC_BW) { 2614 ios->bus_width = new_ios->bus_width; 2615 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2616 } 2617 if (cts->ios_valid & MMC_PM) { 2618 ios->power_mode = new_ios->power_mode; 2619 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2620 } 2621 if (cts->ios_valid & MMC_BT) { 2622 ios->timing = new_ios->timing; 2623 slot_printf(slot, "Timing => %d\n", ios->timing); 2624 } 2625 if (cts->ios_valid & MMC_BM) { 2626 ios->bus_mode = new_ios->bus_mode; 2627 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2628 } 2629 2630 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2631 return (sdhci_cam_update_ios(slot)); 2632 } 2633 2634 int 2635 sdhci_cam_update_ios(struct sdhci_slot *slot) 2636 { 2637 struct mmc_ios *ios = &slot->host.ios; 2638 2639 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2640 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2641 SDHCI_LOCK(slot); 2642 /* Do full reset on bus power down to clear from any state. */ 2643 if (ios->power_mode == power_off) { 2644 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2645 sdhci_init(slot); 2646 } 2647 /* Configure the bus. */ 2648 sdhci_set_clock(slot, ios->clock); 2649 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2650 if (ios->bus_width == bus_width_8) { 2651 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2652 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2653 } else if (ios->bus_width == bus_width_4) { 2654 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2655 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2656 } else if (ios->bus_width == bus_width_1) { 2657 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2658 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2659 } else { 2660 panic("Invalid bus width: %d", ios->bus_width); 2661 } 2662 if (ios->timing == bus_timing_hs && 2663 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2664 slot->hostctrl |= SDHCI_CTRL_HISPD; 2665 else 2666 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2667 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2668 /* Some controllers like reset after bus changes. */ 2669 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2670 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2671 2672 SDHCI_UNLOCK(slot); 2673 return (0); 2674 } 2675 2676 int 2677 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2678 { 2679 struct ccb_mmcio *mmcio; 2680 2681 mmcio = &ccb->mmcio; 2682 2683 SDHCI_LOCK(slot); 2684 /* if (slot->req != NULL) { 2685 SDHCI_UNLOCK(slot); 2686 return (EBUSY); 2687 } 2688 */ 2689 if (__predict_false(sdhci_debug > 1)) { 2690 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2691 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2692 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2693 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 2694 } 2695 if (mmcio->cmd.data != NULL) { 2696 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2697 panic("data->len = %d, data->flags = %d -- something is b0rked", 2698 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2699 } 2700 slot->ccb = ccb; 2701 slot->flags = 0; 2702 sdhci_start(slot); 2703 SDHCI_UNLOCK(slot); 2704 if (dumping) { 2705 while (slot->ccb != NULL) { 2706 sdhci_generic_intr(slot); 2707 DELAY(10); 2708 } 2709 } 2710 return (0); 2711 } 2712 #endif /* MMCCAM */ 2713 2714 MODULE_VERSION(sdhci, 1); 2715