xref: /freebsd/sys/dev/sdhci/sdhci.c (revision 56961fd7949de755f95a60fe8ac936f81e953f5b)
1 /*-
2  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/resource.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41 
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <machine/stdarg.h>
45 
46 #include <dev/mmc/bridge.h>
47 #include <dev/mmc/mmcreg.h>
48 #include <dev/mmc/mmcbrvar.h>
49 
50 #include "mmcbr_if.h"
51 #include "sdhci.h"
52 #include "sdhci_if.h"
53 
54 struct sdhci_softc;
55 
56 struct sdhci_softc {
57 	device_t	dev;		/* Controller device */
58 	struct resource *irq_res;	/* IRQ resource */
59 	int 		irq_rid;
60 	void 		*intrhand;	/* Interrupt handle */
61 
62 	int		num_slots;	/* Number of slots on this controller */
63 	struct sdhci_slot slots[6];
64 };
65 
66 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
67 
68 int	sdhci_debug = 0;
69 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
70 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
71 
72 #define RD1(slot, off)	SDHCI_READ_1((slot)->bus, (slot), (off))
73 #define RD2(slot, off)	SDHCI_READ_2((slot)->bus, (slot), (off))
74 #define RD4(slot, off)	SDHCI_READ_4((slot)->bus, (slot), (off))
75 #define RD_MULTI_4(slot, off, ptr, count)	\
76     SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
77 
78 #define WR1(slot, off, val)	SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
79 #define WR2(slot, off, val)	SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
80 #define WR4(slot, off, val)	SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
81 #define WR_MULTI_4(slot, off, ptr, count)	\
82     SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
83 
84 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
85 static void sdhci_start(struct sdhci_slot *slot);
86 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
87 
88 static void sdhci_card_task(void *, int);
89 
90 /* helper routines */
91 #define SDHCI_LOCK(_slot)		mtx_lock(&(_slot)->mtx)
92 #define	SDHCI_UNLOCK(_slot)		mtx_unlock(&(_slot)->mtx)
93 #define SDHCI_LOCK_INIT(_slot) \
94 	mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
95 #define SDHCI_LOCK_DESTROY(_slot)	mtx_destroy(&_slot->mtx);
96 #define SDHCI_ASSERT_LOCKED(_slot)	mtx_assert(&_slot->mtx, MA_OWNED);
97 #define SDHCI_ASSERT_UNLOCKED(_slot)	mtx_assert(&_slot->mtx, MA_NOTOWNED);
98 
99 #define	SDHCI_DEFAULT_MAX_FREQ	50
100 
101 static void
102 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
103 {
104 	if (error != 0) {
105 		printf("getaddr: error %d\n", error);
106 		return;
107 	}
108 	*(bus_addr_t *)arg = segs[0].ds_addr;
109 }
110 
111 static int
112 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
113 {
114 	va_list ap;
115 	int retval;
116 
117     	retval = printf("%s-slot%d: ",
118 	    device_get_nameunit(slot->bus), slot->num);
119 
120 	va_start(ap, fmt);
121 	retval += vprintf(fmt, ap);
122 	va_end(ap);
123 	return (retval);
124 }
125 
126 static void
127 sdhci_dumpregs(struct sdhci_slot *slot)
128 {
129 	slot_printf(slot,
130 	    "============== REGISTER DUMP ==============\n");
131 
132 	slot_printf(slot, "Sys addr: 0x%08x | Version:  0x%08x\n",
133 	    RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
134 	slot_printf(slot, "Blk size: 0x%08x | Blk cnt:  0x%08x\n",
135 	    RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
136 	slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
137 	    RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
138 	slot_printf(slot, "Present:  0x%08x | Host ctl: 0x%08x\n",
139 	    RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
140 	slot_printf(slot, "Power:    0x%08x | Blk gap:  0x%08x\n",
141 	    RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
142 	slot_printf(slot, "Wake-up:  0x%08x | Clock:    0x%08x\n",
143 	    RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
144 	slot_printf(slot, "Timeout:  0x%08x | Int stat: 0x%08x\n",
145 	    RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
146 	slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
147 	    RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
148 	slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
149 	    RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
150 	slot_printf(slot, "Caps:     0x%08x | Max curr: 0x%08x\n",
151 	    RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
152 
153 	slot_printf(slot,
154 	    "===========================================\n");
155 }
156 
157 static void
158 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
159 {
160 	int timeout;
161 	uint8_t res;
162 
163 	if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
164 		if (!(RD4(slot, SDHCI_PRESENT_STATE) &
165 			SDHCI_CARD_PRESENT))
166 			return;
167 	}
168 
169 	/* Some controllers need this kick or reset won't work. */
170 	if ((mask & SDHCI_RESET_ALL) == 0 &&
171 	    (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
172 		uint32_t clock;
173 
174 		/* This is to force an update */
175 		clock = slot->clock;
176 		slot->clock = 0;
177 		sdhci_set_clock(slot, clock);
178 	}
179 
180 	WR1(slot, SDHCI_SOFTWARE_RESET, mask);
181 
182 	if (mask & SDHCI_RESET_ALL) {
183 		slot->clock = 0;
184 		slot->power = 0;
185 	}
186 
187 	/* Wait max 100 ms */
188 	timeout = 100;
189 	/* Controller clears the bits when it's done */
190 	while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
191 		if (timeout == 0) {
192 			slot_printf(slot,
193 			    "Reset 0x%x never completed - 0x%x.\n",
194 			    (int)mask, (int)res);
195 			sdhci_dumpregs(slot);
196 			return;
197 		}
198 		timeout--;
199 		DELAY(1000);
200 	}
201 }
202 
203 static void
204 sdhci_init(struct sdhci_slot *slot)
205 {
206 
207 	sdhci_reset(slot, SDHCI_RESET_ALL);
208 
209 	/* Enable interrupts. */
210 	slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
211 	    SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
212 	    SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
213 	    SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
214 	    SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
215 	    SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
216 	    SDHCI_INT_ACMD12ERR;
217 	WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
218 	WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
219 }
220 
221 static void
222 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
223 {
224 	uint32_t res;
225 	uint16_t clk;
226 	uint16_t div;
227 	int timeout;
228 
229 	if (clock == slot->clock)
230 		return;
231 	slot->clock = clock;
232 
233 	/* Turn off the clock. */
234 	WR2(slot, SDHCI_CLOCK_CONTROL, 0);
235 	/* If no clock requested - left it so. */
236 	if (clock == 0)
237 		return;
238 	if (slot->version < SDHCI_SPEC_300) {
239 		/* Looking for highest freq <= clock. */
240 		res = slot->max_clk;
241 		for (div = 1; div < 256; div <<= 1) {
242 			if (res <= clock)
243 				break;
244 			res >>= 1;
245 		}
246 		/* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
247 		div >>= 1;
248 	}
249 	else {
250 		/* Version 3.0 divisors are multiples of two up to 1023*2 */
251 		if (clock > slot->max_clk)
252 			div = 2;
253 		else {
254 			for (div = 2; div < 1023*2; div += 2) {
255 				if ((slot->max_clk / div) <= clock)
256 					break;
257 			}
258 		}
259 		div >>= 1;
260 	}
261 
262 	if (bootverbose || sdhci_debug)
263 		slot_printf(slot, "Divider %d for freq %d (max %d)\n",
264 			div, clock, slot->max_clk);
265 
266 	/* Now we have got divider, set it. */
267 	clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
268 	clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
269 		<< SDHCI_DIVIDER_HI_SHIFT;
270 
271 	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
272 	/* Enable clock. */
273 	clk |= SDHCI_CLOCK_INT_EN;
274 	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
275 	/* Wait up to 10 ms until it stabilize. */
276 	timeout = 10;
277 	while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
278 		& SDHCI_CLOCK_INT_STABLE)) {
279 		if (timeout == 0) {
280 			slot_printf(slot,
281 			    "Internal clock never stabilised.\n");
282 			sdhci_dumpregs(slot);
283 			return;
284 		}
285 		timeout--;
286 		DELAY(1000);
287 	}
288 	/* Pass clock signal to the bus. */
289 	clk |= SDHCI_CLOCK_CARD_EN;
290 	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
291 }
292 
293 static void
294 sdhci_set_power(struct sdhci_slot *slot, u_char power)
295 {
296 	uint8_t pwr;
297 
298 	if (slot->power == power)
299 		return;
300 
301 	slot->power = power;
302 
303 	/* Turn off the power. */
304 	pwr = 0;
305 	WR1(slot, SDHCI_POWER_CONTROL, pwr);
306 	/* If power down requested - left it so. */
307 	if (power == 0)
308 		return;
309 	/* Set voltage. */
310 	switch (1 << power) {
311 	case MMC_OCR_LOW_VOLTAGE:
312 		pwr |= SDHCI_POWER_180;
313 		break;
314 	case MMC_OCR_290_300:
315 	case MMC_OCR_300_310:
316 		pwr |= SDHCI_POWER_300;
317 		break;
318 	case MMC_OCR_320_330:
319 	case MMC_OCR_330_340:
320 		pwr |= SDHCI_POWER_330;
321 		break;
322 	}
323 	WR1(slot, SDHCI_POWER_CONTROL, pwr);
324 	/* Turn on the power. */
325 	pwr |= SDHCI_POWER_ON;
326 	WR1(slot, SDHCI_POWER_CONTROL, pwr);
327 }
328 
329 static void
330 sdhci_read_block_pio(struct sdhci_slot *slot)
331 {
332 	uint32_t data;
333 	char *buffer;
334 	size_t left;
335 
336 	buffer = slot->curcmd->data->data;
337 	buffer += slot->offset;
338 	/* Transfer one block at a time. */
339 	left = min(512, slot->curcmd->data->len - slot->offset);
340 	slot->offset += left;
341 
342 	/* If we are too fast, broken controllers return zeroes. */
343 	if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
344 		DELAY(10);
345 	/* Handle unalligned and alligned buffer cases. */
346 	if ((intptr_t)buffer & 3) {
347 		while (left > 3) {
348 			data = RD4(slot, SDHCI_BUFFER);
349 			buffer[0] = data;
350 			buffer[1] = (data >> 8);
351 			buffer[2] = (data >> 16);
352 			buffer[3] = (data >> 24);
353 			buffer += 4;
354 			left -= 4;
355 		}
356 	} else {
357 		RD_MULTI_4(slot, SDHCI_BUFFER,
358 		    (uint32_t *)buffer, left >> 2);
359 		left &= 3;
360 	}
361 	/* Handle uneven size case. */
362 	if (left > 0) {
363 		data = RD4(slot, SDHCI_BUFFER);
364 		while (left > 0) {
365 			*(buffer++) = data;
366 			data >>= 8;
367 			left--;
368 		}
369 	}
370 }
371 
372 static void
373 sdhci_write_block_pio(struct sdhci_slot *slot)
374 {
375 	uint32_t data = 0;
376 	char *buffer;
377 	size_t left;
378 
379 	buffer = slot->curcmd->data->data;
380 	buffer += slot->offset;
381 	/* Transfer one block at a time. */
382 	left = min(512, slot->curcmd->data->len - slot->offset);
383 	slot->offset += left;
384 
385 	/* Handle unalligned and alligned buffer cases. */
386 	if ((intptr_t)buffer & 3) {
387 		while (left > 3) {
388 			data = buffer[0] +
389 			    (buffer[1] << 8) +
390 			    (buffer[2] << 16) +
391 			    (buffer[3] << 24);
392 			left -= 4;
393 			buffer += 4;
394 			WR4(slot, SDHCI_BUFFER, data);
395 		}
396 	} else {
397 		WR_MULTI_4(slot, SDHCI_BUFFER,
398 		    (uint32_t *)buffer, left >> 2);
399 		left &= 3;
400 	}
401 	/* Handle uneven size case. */
402 	if (left > 0) {
403 		while (left > 0) {
404 			data <<= 8;
405 			data += *(buffer++);
406 			left--;
407 		}
408 		WR4(slot, SDHCI_BUFFER, data);
409 	}
410 }
411 
412 static void
413 sdhci_transfer_pio(struct sdhci_slot *slot)
414 {
415 
416 	/* Read as many blocks as possible. */
417 	if (slot->curcmd->data->flags & MMC_DATA_READ) {
418 		while (RD4(slot, SDHCI_PRESENT_STATE) &
419 		    SDHCI_DATA_AVAILABLE) {
420 			sdhci_read_block_pio(slot);
421 			if (slot->offset >= slot->curcmd->data->len)
422 				break;
423 		}
424 	} else {
425 		while (RD4(slot, SDHCI_PRESENT_STATE) &
426 		    SDHCI_SPACE_AVAILABLE) {
427 			sdhci_write_block_pio(slot);
428 			if (slot->offset >= slot->curcmd->data->len)
429 				break;
430 		}
431 	}
432 }
433 
434 static void
435 sdhci_card_delay(void *arg)
436 {
437 	struct sdhci_slot *slot = arg;
438 
439 	taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
440 }
441 
442 static void
443 sdhci_card_task(void *arg, int pending)
444 {
445 	struct sdhci_slot *slot = arg;
446 
447 	SDHCI_LOCK(slot);
448 	if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
449 		if (slot->dev == NULL) {
450 			/* If card is present - attach mmc bus. */
451 			slot->dev = device_add_child(slot->bus, "mmc", -1);
452 			device_set_ivars(slot->dev, slot);
453 			SDHCI_UNLOCK(slot);
454 			device_probe_and_attach(slot->dev);
455 		} else
456 			SDHCI_UNLOCK(slot);
457 	} else {
458 		if (slot->dev != NULL) {
459 			/* If no card present - detach mmc bus. */
460 			device_t d = slot->dev;
461 			slot->dev = NULL;
462 			SDHCI_UNLOCK(slot);
463 			device_delete_child(slot->bus, d);
464 		} else
465 			SDHCI_UNLOCK(slot);
466 	}
467 }
468 
469 int
470 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
471 {
472 	uint32_t caps;
473 	int err;
474 
475 	SDHCI_LOCK_INIT(slot);
476 	slot->num = num;
477 	slot->bus = dev;
478 
479 	/* Allocate DMA tag. */
480 	err = bus_dma_tag_create(bus_get_dma_tag(dev),
481 	    DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
482 	    BUS_SPACE_MAXADDR, NULL, NULL,
483 	    DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
484 	    BUS_DMA_ALLOCNOW, NULL, NULL,
485 	    &slot->dmatag);
486 	if (err != 0) {
487 		device_printf(dev, "Can't create DMA tag\n");
488 		SDHCI_LOCK_DESTROY(slot);
489 		return (err);
490 	}
491 	/* Allocate DMA memory. */
492 	err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
493 	    BUS_DMA_NOWAIT, &slot->dmamap);
494 	if (err != 0) {
495 		device_printf(dev, "Can't alloc DMA memory\n");
496 		SDHCI_LOCK_DESTROY(slot);
497 		return (err);
498 	}
499 	/* Map the memory. */
500 	err = bus_dmamap_load(slot->dmatag, slot->dmamap,
501 	    (void *)slot->dmamem, DMA_BLOCK_SIZE,
502 	    sdhci_getaddr, &slot->paddr, 0);
503 	if (err != 0 || slot->paddr == 0) {
504 		device_printf(dev, "Can't load DMA memory\n");
505 		SDHCI_LOCK_DESTROY(slot);
506 		if(err)
507 			return (err);
508 		else
509 			return (EFAULT);
510 	}
511 
512 	/* Initialize slot. */
513 	sdhci_init(slot);
514 	slot->version = (RD2(slot, SDHCI_HOST_VERSION)
515 		>> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
516 	if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
517 		caps = slot->caps;
518 	else
519 		caps = RD4(slot, SDHCI_CAPABILITIES);
520 	/* Calculate base clock frequency. */
521 	if (slot->version >= SDHCI_SPEC_300)
522 		slot->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
523 		    >> SDHCI_CLOCK_BASE_SHIFT;
524 	else
525 		slot->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
526 		    >> SDHCI_CLOCK_BASE_SHIFT;
527 	if (slot->max_clk == 0) {
528 		slot->max_clk = SDHCI_DEFAULT_MAX_FREQ;
529 		device_printf(dev, "Hardware doesn't specify base clock "
530 		    "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
531 	}
532 	slot->max_clk *= 1000000;
533 	/* Calculate timeout clock frequency. */
534 	if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
535 		slot->timeout_clk = slot->max_clk / 1000;
536 	} else {
537 		slot->timeout_clk =
538 			(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
539 		if (caps & SDHCI_TIMEOUT_CLK_UNIT)
540 			slot->timeout_clk *= 1000;
541 	}
542 
543 	if (slot->timeout_clk == 0) {
544 		device_printf(dev, "Hardware doesn't specify timeout clock "
545 		    "frequency.\n");
546 	}
547 
548 	slot->host.f_min = slot->max_clk / 256;
549 	slot->host.f_max = slot->max_clk;
550 	slot->host.host_ocr = 0;
551 	if (caps & SDHCI_CAN_VDD_330)
552 	    slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
553 	if (caps & SDHCI_CAN_VDD_300)
554 	    slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
555 	if (caps & SDHCI_CAN_VDD_180)
556 	    slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
557 	if (slot->host.host_ocr == 0) {
558 		device_printf(dev, "Hardware doesn't report any "
559 		    "support voltages.\n");
560 	}
561 	slot->host.caps = MMC_CAP_4_BIT_DATA;
562 	if (caps & SDHCI_CAN_DO_HISPD)
563 		slot->host.caps |= MMC_CAP_HSPEED;
564 	/* Decide if we have usable DMA. */
565 	if (caps & SDHCI_CAN_DO_DMA)
566 		slot->opt |= SDHCI_HAVE_DMA;
567 
568 	if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
569 		slot->opt &= ~SDHCI_HAVE_DMA;
570 	if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
571 		slot->opt |= SDHCI_HAVE_DMA;
572 
573 	if (bootverbose || sdhci_debug) {
574 		slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
575 		    slot->max_clk / 1000000,
576 		    (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
577 		    (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
578 		    (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
579 		    (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
580 		    (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
581 		sdhci_dumpregs(slot);
582 	}
583 
584 	TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
585 	callout_init(&slot->card_callout, 1);
586 	return (0);
587 }
588 
589 void
590 sdhci_start_slot(struct sdhci_slot *slot)
591 {
592 	sdhci_card_task(slot, 0);
593 }
594 
595 int
596 sdhci_cleanup_slot(struct sdhci_slot *slot)
597 {
598 	device_t d;
599 
600 	callout_drain(&slot->card_callout);
601 	taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
602 
603 	SDHCI_LOCK(slot);
604 	d = slot->dev;
605 	slot->dev = NULL;
606 	SDHCI_UNLOCK(slot);
607 	if (d != NULL)
608 		device_delete_child(slot->bus, d);
609 
610 	SDHCI_LOCK(slot);
611 	sdhci_reset(slot, SDHCI_RESET_ALL);
612 	SDHCI_UNLOCK(slot);
613 	bus_dmamap_unload(slot->dmatag, slot->dmamap);
614 	bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
615 	bus_dma_tag_destroy(slot->dmatag);
616 
617 	SDHCI_LOCK_DESTROY(slot);
618 
619 	return (0);
620 }
621 
622 int
623 sdhci_generic_suspend(struct sdhci_slot *slot)
624 {
625 	sdhci_reset(slot, SDHCI_RESET_ALL);
626 
627 	return (0);
628 }
629 
630 int
631 sdhci_generic_resume(struct sdhci_slot *slot)
632 {
633 	sdhci_init(slot);
634 
635 	return (0);
636 }
637 
638 int
639 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
640 {
641 	struct sdhci_slot *slot = device_get_ivars(reqdev);
642 	struct mmc_ios *ios = &slot->host.ios;
643 
644 	SDHCI_LOCK(slot);
645 	/* Do full reset on bus power down to clear from any state. */
646 	if (ios->power_mode == power_off) {
647 		WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
648 		sdhci_init(slot);
649 	}
650 	/* Configure the bus. */
651 	sdhci_set_clock(slot, ios->clock);
652 	sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
653 	if (ios->bus_width == bus_width_4)
654 		slot->hostctrl |= SDHCI_CTRL_4BITBUS;
655 	else
656 		slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
657 	if (ios->timing == bus_timing_hs)
658 		slot->hostctrl |= SDHCI_CTRL_HISPD;
659 	else
660 		slot->hostctrl &= ~SDHCI_CTRL_HISPD;
661 	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
662 	/* Some controllers like reset after bus changes. */
663 	if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
664 		sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
665 
666 	SDHCI_UNLOCK(slot);
667 	return (0);
668 }
669 
670 static void
671 sdhci_set_transfer_mode(struct sdhci_slot *slot,
672 	struct mmc_data *data)
673 {
674 	uint16_t mode;
675 
676 	if (data == NULL)
677 		return;
678 
679 	mode = SDHCI_TRNS_BLK_CNT_EN;
680 	if (data->len > 512)
681 		mode |= SDHCI_TRNS_MULTI;
682 	if (data->flags & MMC_DATA_READ)
683 		mode |= SDHCI_TRNS_READ;
684 	if (slot->req->stop)
685 		mode |= SDHCI_TRNS_ACMD12;
686 	if (slot->flags & SDHCI_USE_DMA)
687 		mode |= SDHCI_TRNS_DMA;
688 
689 	WR2(slot, SDHCI_TRANSFER_MODE, mode);
690 }
691 
692 static void
693 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
694 {
695 	struct mmc_request *req = slot->req;
696 	int flags, timeout;
697 	uint32_t mask, state;
698 
699 	slot->curcmd = cmd;
700 	slot->cmd_done = 0;
701 
702 	cmd->error = MMC_ERR_NONE;
703 
704 	/* This flags combination is not supported by controller. */
705 	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
706 		slot_printf(slot, "Unsupported response type!\n");
707 		cmd->error = MMC_ERR_FAILED;
708 		slot->req = NULL;
709 		slot->curcmd = NULL;
710 		req->done(req);
711 		return;
712 	}
713 
714 	/* Read controller present state. */
715 	state = RD4(slot, SDHCI_PRESENT_STATE);
716 	/* Do not issue command if there is no card, clock or power.
717 	 * Controller will not detect timeout without clock active. */
718 	if ((state & SDHCI_CARD_PRESENT) == 0 ||
719 	    slot->power == 0 ||
720 	    slot->clock == 0) {
721 		cmd->error = MMC_ERR_FAILED;
722 		slot->req = NULL;
723 		slot->curcmd = NULL;
724 		req->done(req);
725 		return;
726 	}
727 	/* Always wait for free CMD bus. */
728 	mask = SDHCI_CMD_INHIBIT;
729 	/* Wait for free DAT if we have data or busy signal. */
730 	if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
731 		mask |= SDHCI_DAT_INHIBIT;
732 	/* We shouldn't wait for DAT for stop commands. */
733 	if (cmd == slot->req->stop)
734 		mask &= ~SDHCI_DAT_INHIBIT;
735 	/* Wait for bus no more then 10 ms. */
736 	timeout = 10;
737 	while (state & mask) {
738 		if (timeout == 0) {
739 			slot_printf(slot, "Controller never released "
740 			    "inhibit bit(s).\n");
741 			sdhci_dumpregs(slot);
742 			cmd->error = MMC_ERR_FAILED;
743 			slot->req = NULL;
744 			slot->curcmd = NULL;
745 			req->done(req);
746 			return;
747 		}
748 		timeout--;
749 		DELAY(1000);
750 		state = RD4(slot, SDHCI_PRESENT_STATE);
751 	}
752 
753 	/* Prepare command flags. */
754 	if (!(cmd->flags & MMC_RSP_PRESENT))
755 		flags = SDHCI_CMD_RESP_NONE;
756 	else if (cmd->flags & MMC_RSP_136)
757 		flags = SDHCI_CMD_RESP_LONG;
758 	else if (cmd->flags & MMC_RSP_BUSY)
759 		flags = SDHCI_CMD_RESP_SHORT_BUSY;
760 	else
761 		flags = SDHCI_CMD_RESP_SHORT;
762 	if (cmd->flags & MMC_RSP_CRC)
763 		flags |= SDHCI_CMD_CRC;
764 	if (cmd->flags & MMC_RSP_OPCODE)
765 		flags |= SDHCI_CMD_INDEX;
766 	if (cmd->data)
767 		flags |= SDHCI_CMD_DATA;
768 	if (cmd->opcode == MMC_STOP_TRANSMISSION)
769 		flags |= SDHCI_CMD_TYPE_ABORT;
770 	/* Prepare data. */
771 	sdhci_start_data(slot, cmd->data);
772 	/*
773 	 * Interrupt aggregation: To reduce total number of interrupts
774 	 * group response interrupt with data interrupt when possible.
775 	 * If there going to be data interrupt, mask response one.
776 	 */
777 	if (slot->data_done == 0) {
778 		WR4(slot, SDHCI_SIGNAL_ENABLE,
779 		    slot->intmask &= ~SDHCI_INT_RESPONSE);
780 	}
781 	/* Set command argument. */
782 	WR4(slot, SDHCI_ARGUMENT, cmd->arg);
783 	/* Set data transfer mode. */
784 	sdhci_set_transfer_mode(slot, cmd->data);
785 	/* Start command. */
786 	WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
787 }
788 
789 static void
790 sdhci_finish_command(struct sdhci_slot *slot)
791 {
792 	int i;
793 
794 	slot->cmd_done = 1;
795 	/* Interrupt aggregation: Restore command interrupt.
796 	 * Main restore point for the case when command interrupt
797 	 * happened first. */
798 	WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
799 	/* In case of error - reset host and return. */
800 	if (slot->curcmd->error) {
801 		sdhci_reset(slot, SDHCI_RESET_CMD);
802 		sdhci_reset(slot, SDHCI_RESET_DATA);
803 		sdhci_start(slot);
804 		return;
805 	}
806 	/* If command has response - fetch it. */
807 	if (slot->curcmd->flags & MMC_RSP_PRESENT) {
808 		if (slot->curcmd->flags & MMC_RSP_136) {
809 			/* CRC is stripped so we need one byte shift. */
810 			uint8_t extra = 0;
811 			for (i = 0; i < 4; i++) {
812 				uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
813 				slot->curcmd->resp[3 - i] = (val << 8) + extra;
814 				extra = val >> 24;
815 			}
816 		} else
817 			slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
818 	}
819 	/* If data ready - finish. */
820 	if (slot->data_done)
821 		sdhci_start(slot);
822 }
823 
824 static void
825 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
826 {
827 	uint32_t target_timeout, current_timeout;
828 	uint8_t div;
829 
830 	if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
831 		slot->data_done = 1;
832 		return;
833 	}
834 
835 	slot->data_done = 0;
836 
837 	/* Calculate and set data timeout.*/
838 	/* XXX: We should have this from mmc layer, now assume 1 sec. */
839 	target_timeout = 1000000;
840 	div = 0;
841 	current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
842 	while (current_timeout < target_timeout) {
843 		div++;
844 		current_timeout <<= 1;
845 		if (div >= 0xF)
846 			break;
847 	}
848 	/* Compensate for an off-by-one error in the CaFe chip.*/
849 	if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
850 		div++;
851 	if (div >= 0xF) {
852 		slot_printf(slot, "Timeout too large!\n");
853 		div = 0xE;
854 	}
855 	if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
856 		div = 0xE;
857 	WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
858 
859 	if (data == NULL)
860 		return;
861 
862 	/* Use DMA if possible. */
863 	if ((slot->opt & SDHCI_HAVE_DMA))
864 		slot->flags |= SDHCI_USE_DMA;
865 	/* If data is small, broken DMA may return zeroes instead of data, */
866 	if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
867 	    (data->len <= 512))
868 		slot->flags &= ~SDHCI_USE_DMA;
869 	/* Some controllers require even block sizes. */
870 	if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
871 	    ((data->len) & 0x3))
872 		slot->flags &= ~SDHCI_USE_DMA;
873 	/* Load DMA buffer. */
874 	if (slot->flags & SDHCI_USE_DMA) {
875 		if (data->flags & MMC_DATA_READ)
876 			bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
877 		else {
878 			memcpy(slot->dmamem, data->data,
879 			    (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE);
880 			bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE);
881 		}
882 		WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
883 		/* Interrupt aggregation: Mask border interrupt
884 		 * for the last page and unmask else. */
885 		if (data->len == DMA_BLOCK_SIZE)
886 			slot->intmask &= ~SDHCI_INT_DMA_END;
887 		else
888 			slot->intmask |= SDHCI_INT_DMA_END;
889 		WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
890 	}
891 	/* Current data offset for both PIO and DMA. */
892 	slot->offset = 0;
893 	/* Set block size and request IRQ on 4K border. */
894 	WR2(slot, SDHCI_BLOCK_SIZE,
895 	    SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
896 	/* Set block count. */
897 	WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
898 }
899 
900 static void
901 sdhci_finish_data(struct sdhci_slot *slot)
902 {
903 	struct mmc_data *data = slot->curcmd->data;
904 
905 	slot->data_done = 1;
906 	/* Interrupt aggregation: Restore command interrupt.
907 	 * Auxillary restore point for the case when data interrupt
908 	 * happened first. */
909 	if (!slot->cmd_done) {
910 		WR4(slot, SDHCI_SIGNAL_ENABLE,
911 		    slot->intmask |= SDHCI_INT_RESPONSE);
912 	}
913 	/* Unload rest of data from DMA buffer. */
914 	if (slot->flags & SDHCI_USE_DMA) {
915 		if (data->flags & MMC_DATA_READ) {
916 			size_t left = data->len - slot->offset;
917 			bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD);
918 			memcpy((u_char*)data->data + slot->offset, slot->dmamem,
919 			    (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
920 		} else
921 			bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
922 	}
923 	/* If there was error - reset the host. */
924 	if (slot->curcmd->error) {
925 		sdhci_reset(slot, SDHCI_RESET_CMD);
926 		sdhci_reset(slot, SDHCI_RESET_DATA);
927 		sdhci_start(slot);
928 		return;
929 	}
930 	/* If we already have command response - finish. */
931 	if (slot->cmd_done)
932 		sdhci_start(slot);
933 }
934 
935 static void
936 sdhci_start(struct sdhci_slot *slot)
937 {
938 	struct mmc_request *req;
939 
940 	req = slot->req;
941 	if (req == NULL)
942 		return;
943 
944 	if (!(slot->flags & CMD_STARTED)) {
945 		slot->flags |= CMD_STARTED;
946 		sdhci_start_command(slot, req->cmd);
947 		return;
948 	}
949 /* 	We don't need this until using Auto-CMD12 feature
950 	if (!(slot->flags & STOP_STARTED) && req->stop) {
951 		slot->flags |= STOP_STARTED;
952 		sdhci_start_command(slot, req->stop);
953 		return;
954 	}
955 */
956 	if (sdhci_debug > 1)
957 		slot_printf(slot, "result: %d\n", req->cmd->error);
958 	if (!req->cmd->error &&
959 	    (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
960 		sdhci_reset(slot, SDHCI_RESET_CMD);
961 		sdhci_reset(slot, SDHCI_RESET_DATA);
962 	}
963 
964 	/* We must be done -- bad idea to do this while locked? */
965 	slot->req = NULL;
966 	slot->curcmd = NULL;
967 	req->done(req);
968 }
969 
970 int
971 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
972 {
973 	struct sdhci_slot *slot = device_get_ivars(reqdev);
974 
975 	SDHCI_LOCK(slot);
976 	if (slot->req != NULL) {
977 		SDHCI_UNLOCK(slot);
978 		return (EBUSY);
979 	}
980 	if (sdhci_debug > 1) {
981 		slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
982     		    req->cmd->opcode, req->cmd->arg, req->cmd->flags,
983     		    (req->cmd->data)?(u_int)req->cmd->data->len:0,
984 		    (req->cmd->data)?req->cmd->data->flags:0);
985 	}
986 	slot->req = req;
987 	slot->flags = 0;
988 	sdhci_start(slot);
989 	SDHCI_UNLOCK(slot);
990 	if (dumping) {
991 		while (slot->req != NULL) {
992 			sdhci_generic_intr(slot);
993 			DELAY(10);
994 		}
995 	}
996 	return (0);
997 }
998 
999 int
1000 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1001 {
1002 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1003 	uint32_t val;
1004 
1005 	SDHCI_LOCK(slot);
1006 	val = RD4(slot, SDHCI_PRESENT_STATE);
1007 	SDHCI_UNLOCK(slot);
1008 	return (!(val & SDHCI_WRITE_PROTECT));
1009 }
1010 
1011 int
1012 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1013 {
1014 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1015 	int err = 0;
1016 
1017 	SDHCI_LOCK(slot);
1018 	while (slot->bus_busy)
1019 		msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1020 	slot->bus_busy++;
1021 	/* Activate led. */
1022 	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1023 	SDHCI_UNLOCK(slot);
1024 	return (err);
1025 }
1026 
1027 int
1028 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1029 {
1030 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1031 
1032 	SDHCI_LOCK(slot);
1033 	/* Deactivate led. */
1034 	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1035 	slot->bus_busy--;
1036 	SDHCI_UNLOCK(slot);
1037 	wakeup(slot);
1038 	return (0);
1039 }
1040 
1041 static void
1042 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1043 {
1044 
1045 	if (!slot->curcmd) {
1046 		slot_printf(slot, "Got command interrupt 0x%08x, but "
1047 		    "there is no active command.\n", intmask);
1048 		sdhci_dumpregs(slot);
1049 		return;
1050 	}
1051 	if (intmask & SDHCI_INT_TIMEOUT)
1052 		slot->curcmd->error = MMC_ERR_TIMEOUT;
1053 	else if (intmask & SDHCI_INT_CRC)
1054 		slot->curcmd->error = MMC_ERR_BADCRC;
1055 	else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1056 		slot->curcmd->error = MMC_ERR_FIFO;
1057 
1058 	sdhci_finish_command(slot);
1059 }
1060 
1061 static void
1062 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1063 {
1064 
1065 	if (!slot->curcmd) {
1066 		slot_printf(slot, "Got data interrupt 0x%08x, but "
1067 		    "there is no active command.\n", intmask);
1068 		sdhci_dumpregs(slot);
1069 		return;
1070 	}
1071 	if (slot->curcmd->data == NULL &&
1072 	    (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1073 		slot_printf(slot, "Got data interrupt 0x%08x, but "
1074 		    "there is no active data operation.\n",
1075 		    intmask);
1076 		sdhci_dumpregs(slot);
1077 		return;
1078 	}
1079 	if (intmask & SDHCI_INT_DATA_TIMEOUT)
1080 		slot->curcmd->error = MMC_ERR_TIMEOUT;
1081 	else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1082 		slot->curcmd->error = MMC_ERR_BADCRC;
1083 	if (slot->curcmd->data == NULL &&
1084 	    (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1085 	    SDHCI_INT_DMA_END))) {
1086 		slot_printf(slot, "Got data interrupt 0x%08x, but "
1087 		    "there is busy-only command.\n", intmask);
1088 		sdhci_dumpregs(slot);
1089 		slot->curcmd->error = MMC_ERR_INVALID;
1090 	}
1091 	if (slot->curcmd->error) {
1092 		/* No need to continue after any error. */
1093 		sdhci_finish_data(slot);
1094 		return;
1095 	}
1096 
1097 	/* Handle PIO interrupt. */
1098 	if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1099 		sdhci_transfer_pio(slot);
1100 	/* Handle DMA border. */
1101 	if (intmask & SDHCI_INT_DMA_END) {
1102 		struct mmc_data *data = slot->curcmd->data;
1103 		size_t left;
1104 
1105 		/* Unload DMA buffer... */
1106 		left = data->len - slot->offset;
1107 		if (data->flags & MMC_DATA_READ) {
1108 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1109 			    BUS_DMASYNC_POSTREAD);
1110 			memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1111 			    (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1112 		} else {
1113 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1114 			    BUS_DMASYNC_POSTWRITE);
1115 		}
1116 		/* ... and reload it again. */
1117 		slot->offset += DMA_BLOCK_SIZE;
1118 		left = data->len - slot->offset;
1119 		if (data->flags & MMC_DATA_READ) {
1120 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1121 			    BUS_DMASYNC_PREREAD);
1122 		} else {
1123 			memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1124 			    (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1125 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1126 			    BUS_DMASYNC_PREWRITE);
1127 		}
1128 		/* Interrupt aggregation: Mask border interrupt
1129 		 * for the last page. */
1130 		if (left == DMA_BLOCK_SIZE) {
1131 			slot->intmask &= ~SDHCI_INT_DMA_END;
1132 			WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1133 		}
1134 		/* Restart DMA. */
1135 		WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1136 	}
1137 	/* We have got all data. */
1138 	if (intmask & SDHCI_INT_DATA_END)
1139 		sdhci_finish_data(slot);
1140 }
1141 
1142 static void
1143 sdhci_acmd_irq(struct sdhci_slot *slot)
1144 {
1145 	uint16_t err;
1146 
1147 	err = RD4(slot, SDHCI_ACMD12_ERR);
1148 	if (!slot->curcmd) {
1149 		slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1150 		    "there is no active command.\n", err);
1151 		sdhci_dumpregs(slot);
1152 		return;
1153 	}
1154 	slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1155 	sdhci_reset(slot, SDHCI_RESET_CMD);
1156 }
1157 
1158 void
1159 sdhci_generic_intr(struct sdhci_slot *slot)
1160 {
1161 	uint32_t intmask;
1162 
1163 	SDHCI_LOCK(slot);
1164 	/* Read slot interrupt status. */
1165 	intmask = RD4(slot, SDHCI_INT_STATUS);
1166 	if (intmask == 0 || intmask == 0xffffffff) {
1167 		SDHCI_UNLOCK(slot);
1168 		return;
1169 	}
1170 	if (sdhci_debug > 2)
1171 		slot_printf(slot, "Interrupt %#x\n", intmask);
1172 
1173 	/* Handle card presence interrupts. */
1174 	if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1175 		WR4(slot, SDHCI_INT_STATUS, intmask &
1176 		    (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1177 
1178 		if (intmask & SDHCI_INT_CARD_REMOVE) {
1179 			if (bootverbose || sdhci_debug)
1180 				slot_printf(slot, "Card removed\n");
1181 			callout_stop(&slot->card_callout);
1182 			taskqueue_enqueue(taskqueue_swi_giant,
1183 			    &slot->card_task);
1184 		}
1185 		if (intmask & SDHCI_INT_CARD_INSERT) {
1186 			if (bootverbose || sdhci_debug)
1187 				slot_printf(slot, "Card inserted\n");
1188 			callout_reset(&slot->card_callout, hz / 2,
1189 			    sdhci_card_delay, slot);
1190 		}
1191 		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1192 	}
1193 	/* Handle command interrupts. */
1194 	if (intmask & SDHCI_INT_CMD_MASK) {
1195 		WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1196 		sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1197 	}
1198 	/* Handle data interrupts. */
1199 	if (intmask & SDHCI_INT_DATA_MASK) {
1200 		WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1201 		sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1202 	}
1203 	/* Handle AutoCMD12 error interrupt. */
1204 	if (intmask & SDHCI_INT_ACMD12ERR) {
1205 		WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1206 		sdhci_acmd_irq(slot);
1207 	}
1208 	intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1209 	intmask &= ~SDHCI_INT_ACMD12ERR;
1210 	intmask &= ~SDHCI_INT_ERROR;
1211 	/* Handle bus power interrupt. */
1212 	if (intmask & SDHCI_INT_BUS_POWER) {
1213 		WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1214 		slot_printf(slot,
1215 		    "Card is consuming too much power!\n");
1216 		intmask &= ~SDHCI_INT_BUS_POWER;
1217 	}
1218 	/* The rest is unknown. */
1219 	if (intmask) {
1220 		WR4(slot, SDHCI_INT_STATUS, intmask);
1221 		slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1222 		    intmask);
1223 		sdhci_dumpregs(slot);
1224 	}
1225 
1226 	SDHCI_UNLOCK(slot);
1227 }
1228 
1229 int
1230 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1231 {
1232 	struct sdhci_slot *slot = device_get_ivars(child);
1233 
1234 	switch (which) {
1235 	default:
1236 		return (EINVAL);
1237 	case MMCBR_IVAR_BUS_MODE:
1238 		*result = slot->host.ios.bus_mode;
1239 		break;
1240 	case MMCBR_IVAR_BUS_WIDTH:
1241 		*result = slot->host.ios.bus_width;
1242 		break;
1243 	case MMCBR_IVAR_CHIP_SELECT:
1244 		*result = slot->host.ios.chip_select;
1245 		break;
1246 	case MMCBR_IVAR_CLOCK:
1247 		*result = slot->host.ios.clock;
1248 		break;
1249 	case MMCBR_IVAR_F_MIN:
1250 		*result = slot->host.f_min;
1251 		break;
1252 	case MMCBR_IVAR_F_MAX:
1253 		*result = slot->host.f_max;
1254 		break;
1255 	case MMCBR_IVAR_HOST_OCR:
1256 		*result = slot->host.host_ocr;
1257 		break;
1258 	case MMCBR_IVAR_MODE:
1259 		*result = slot->host.mode;
1260 		break;
1261 	case MMCBR_IVAR_OCR:
1262 		*result = slot->host.ocr;
1263 		break;
1264 	case MMCBR_IVAR_POWER_MODE:
1265 		*result = slot->host.ios.power_mode;
1266 		break;
1267 	case MMCBR_IVAR_VDD:
1268 		*result = slot->host.ios.vdd;
1269 		break;
1270 	case MMCBR_IVAR_CAPS:
1271 		*result = slot->host.caps;
1272 		break;
1273 	case MMCBR_IVAR_TIMING:
1274 		*result = slot->host.ios.timing;
1275 		break;
1276 	case MMCBR_IVAR_MAX_DATA:
1277 		*result = 65535;
1278 		break;
1279 	}
1280 	return (0);
1281 }
1282 
1283 int
1284 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1285 {
1286 	struct sdhci_slot *slot = device_get_ivars(child);
1287 
1288 	switch (which) {
1289 	default:
1290 		return (EINVAL);
1291 	case MMCBR_IVAR_BUS_MODE:
1292 		slot->host.ios.bus_mode = value;
1293 		break;
1294 	case MMCBR_IVAR_BUS_WIDTH:
1295 		slot->host.ios.bus_width = value;
1296 		break;
1297 	case MMCBR_IVAR_CHIP_SELECT:
1298 		slot->host.ios.chip_select = value;
1299 		break;
1300 	case MMCBR_IVAR_CLOCK:
1301 		if (value > 0) {
1302 			uint32_t clock = slot->max_clk;
1303 			int i;
1304 
1305 			for (i = 0; i < 8; i++) {
1306 				if (clock <= value)
1307 					break;
1308 				clock >>= 1;
1309 			}
1310 			slot->host.ios.clock = clock;
1311 		} else
1312 			slot->host.ios.clock = 0;
1313 		break;
1314 	case MMCBR_IVAR_MODE:
1315 		slot->host.mode = value;
1316 		break;
1317 	case MMCBR_IVAR_OCR:
1318 		slot->host.ocr = value;
1319 		break;
1320 	case MMCBR_IVAR_POWER_MODE:
1321 		slot->host.ios.power_mode = value;
1322 		break;
1323 	case MMCBR_IVAR_VDD:
1324 		slot->host.ios.vdd = value;
1325 		break;
1326 	case MMCBR_IVAR_TIMING:
1327 		slot->host.ios.timing = value;
1328 		break;
1329 	case MMCBR_IVAR_CAPS:
1330 	case MMCBR_IVAR_HOST_OCR:
1331 	case MMCBR_IVAR_F_MIN:
1332 	case MMCBR_IVAR_F_MAX:
1333 	case MMCBR_IVAR_MAX_DATA:
1334 		return (EINVAL);
1335 	}
1336 	return (0);
1337 }
1338 
1339 MODULE_VERSION(sdhci, 1);
1340