1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/taskqueue.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 #include <machine/stdarg.h> 47 48 #include <dev/mmc/bridge.h> 49 #include <dev/mmc/mmcreg.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include "mmcbr_if.h" 53 #include "sdhci.h" 54 55 #define DMA_BLOCK_SIZE 4096 56 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 57 58 /* Controller doesn't honor resets unless we touch the clock register */ 59 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 60 /* Controller really supports DMA */ 61 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 62 /* Controller has unusable DMA engine */ 63 #define SDHCI_QUIRK_BROKEN_DMA (1<<2) 64 /* Controller doesn't like to be reset when there is no card inserted. */ 65 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 66 /* Controller has flaky internal state so reset it on each ios change */ 67 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 68 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 69 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 70 /* Controller needs to be reset after each request to stay stable */ 71 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 72 /* Controller has an off-by-one issue with timeout value */ 73 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 74 /* Controller has broken read timings */ 75 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 76 77 static const struct sdhci_device { 78 uint32_t model; 79 uint16_t subvendor; 80 char *desc; 81 u_int quirks; 82 } sdhci_devices[] = { 83 { 0x08221180, 0xffff, "RICOH R5C822 SD", 84 SDHCI_QUIRK_FORCE_DMA }, 85 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 86 SDHCI_QUIRK_FORCE_DMA }, 87 { 0x05501524, 0xffff, "ENE CB712 SD", 88 SDHCI_QUIRK_BROKEN_TIMINGS }, 89 { 0x05511524, 0xffff, "ENE CB712 SD 2", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x07501524, 0xffff, "ENE CB714 SD", 92 SDHCI_QUIRK_RESET_ON_IOS | 93 SDHCI_QUIRK_BROKEN_TIMINGS }, 94 { 0x07511524, 0xffff, "ENE CB714 SD 2", 95 SDHCI_QUIRK_RESET_ON_IOS | 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x410111ab, 0xffff, "Marvell CaFe SD", 98 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 99 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 100 SDHCI_QUIRK_32BIT_DMA_SIZE | 101 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 102 { 0, 0xffff, NULL, 103 0 } 104 }; 105 106 struct sdhci_softc; 107 108 struct sdhci_slot { 109 struct sdhci_softc *sc; 110 device_t dev; /* Slot device */ 111 u_char num; /* Slot number */ 112 u_char opt; /* Slot options */ 113 #define SDHCI_HAVE_DMA 1 114 uint32_t max_clk; /* Max possible freq */ 115 uint32_t timeout_clk; /* Timeout freq */ 116 struct resource *mem_res; /* Memory resource */ 117 int mem_rid; 118 bus_dma_tag_t dmatag; 119 bus_dmamap_t dmamap; 120 u_char *dmamem; 121 bus_addr_t paddr; /* DMA buffer address */ 122 struct task card_task; /* Card presence check task */ 123 struct callout card_callout; /* Card insert delay callout */ 124 struct mmc_host host; /* Host parameters */ 125 struct mmc_request *req; /* Current request */ 126 struct mmc_command *curcmd; /* Current command of current request */ 127 128 uint32_t intmask; /* Current interrupt mask */ 129 uint32_t clock; /* Current clock freq. */ 130 size_t offset; /* Data buffer offset */ 131 uint8_t hostctrl; /* Current host control register */ 132 u_char power; /* Current power */ 133 u_char bus_busy; /* Bus busy status */ 134 u_char cmd_done; /* CMD command part done flag */ 135 u_char data_done; /* DAT command part done flag */ 136 u_char flags; /* Request execution flags */ 137 #define CMD_STARTED 1 138 #define STOP_STARTED 2 139 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 140 struct mtx mtx; /* Slot mutex */ 141 }; 142 143 struct sdhci_softc { 144 device_t dev; /* Controller device */ 145 u_int quirks; /* Chip specific quirks */ 146 struct resource *irq_res; /* IRQ resource */ 147 int irq_rid; 148 void *intrhand; /* Interrupt handle */ 149 150 int num_slots; /* Number of slots on this controller */ 151 struct sdhci_slot slots[6]; 152 }; 153 154 static inline uint8_t 155 RD1(struct sdhci_slot *slot, bus_size_t off) 156 { 157 bus_barrier(slot->mem_res, 0, 0xFF, 158 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 159 return bus_read_1(slot->mem_res, off); 160 } 161 162 static inline void 163 WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) 164 { 165 bus_barrier(slot->mem_res, 0, 0xFF, 166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167 bus_write_1(slot->mem_res, off, val); 168 } 169 170 static inline uint16_t 171 RD2(struct sdhci_slot *slot, bus_size_t off) 172 { 173 bus_barrier(slot->mem_res, 0, 0xFF, 174 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 175 return bus_read_2(slot->mem_res, off); 176 } 177 178 static inline void 179 WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) 180 { 181 bus_barrier(slot->mem_res, 0, 0xFF, 182 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 183 bus_write_2(slot->mem_res, off, val); 184 } 185 186 static inline uint32_t 187 RD4(struct sdhci_slot *slot, bus_size_t off) 188 { 189 bus_barrier(slot->mem_res, 0, 0xFF, 190 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 191 return bus_read_4(slot->mem_res, off); 192 } 193 194 static inline void 195 WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) 196 { 197 bus_barrier(slot->mem_res, 0, 0xFF, 198 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 199 bus_write_4(slot->mem_res, off, val); 200 } 201 202 /* bus entry points */ 203 static int sdhci_probe(device_t dev); 204 static int sdhci_attach(device_t dev); 205 static int sdhci_detach(device_t dev); 206 static void sdhci_intr(void *); 207 208 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 209 static void sdhci_start(struct sdhci_slot *slot); 210 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 211 212 static void sdhci_card_task(void *, int); 213 214 /* helper routines */ 215 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 216 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 217 #define SDHCI_LOCK_INIT(_slot) \ 218 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 219 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 220 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 221 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 222 223 static int 224 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 225 { 226 va_list ap; 227 int retval; 228 229 retval = printf("%s-slot%d: ", 230 device_get_nameunit(slot->sc->dev), slot->num); 231 232 va_start(ap, fmt); 233 retval += vprintf(fmt, ap); 234 va_end(ap); 235 return (retval); 236 } 237 238 static void 239 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 240 { 241 if (error != 0) { 242 printf("getaddr: error %d\n", error); 243 return; 244 } 245 *(bus_addr_t *)arg = segs[0].ds_addr; 246 } 247 248 static void 249 sdhci_dumpregs(struct sdhci_slot *slot) 250 { 251 slot_printf(slot, 252 "============== REGISTER DUMP ==============\n"); 253 254 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 255 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 256 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 257 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 258 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 259 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 260 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 261 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 262 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 263 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 264 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 265 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 266 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 267 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 268 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 269 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 270 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 271 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 272 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 273 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 274 275 slot_printf(slot, 276 "===========================================\n"); 277 } 278 279 static void 280 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 281 { 282 int timeout; 283 uint8_t res; 284 285 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 286 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 287 SDHCI_CARD_PRESENT)) 288 return; 289 } 290 291 /* Some controllers need this kick or reset won't work. */ 292 if ((mask & SDHCI_RESET_ALL) == 0 && 293 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 294 uint32_t clock; 295 296 /* This is to force an update */ 297 clock = slot->clock; 298 slot->clock = 0; 299 sdhci_set_clock(slot, clock); 300 } 301 302 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 303 304 if (mask & SDHCI_RESET_ALL) { 305 slot->clock = 0; 306 slot->power = 0; 307 } 308 309 /* Wait max 100 ms */ 310 timeout = 100; 311 /* Controller clears the bits when it's done */ 312 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 313 if (timeout == 0) { 314 slot_printf(slot, 315 "Reset 0x%x never completed - 0x%x.\n", 316 (int)mask, (int)res); 317 sdhci_dumpregs(slot); 318 return; 319 } 320 timeout--; 321 DELAY(1000); 322 } 323 } 324 325 static void 326 sdhci_init(struct sdhci_slot *slot) 327 { 328 329 sdhci_reset(slot, SDHCI_RESET_ALL); 330 331 /* Enable interrupts. */ 332 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 333 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 334 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 335 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 336 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 337 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 338 SDHCI_INT_ACMD12ERR; 339 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 340 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 341 } 342 343 static void 344 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 345 { 346 uint32_t res; 347 uint16_t clk; 348 int timeout; 349 350 if (clock == slot->clock) 351 return; 352 slot->clock = clock; 353 354 /* Turn off the clock. */ 355 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 356 /* If no clock requested - left it so. */ 357 if (clock == 0) 358 return; 359 /* Looking for highest freq <= clock. */ 360 res = slot->max_clk; 361 for (clk = 1; clk < 256; clk <<= 1) { 362 if (res <= clock) 363 break; 364 res >>= 1; 365 } 366 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 367 clk >>= 1; 368 /* Now we have got divider, set it. */ 369 clk <<= SDHCI_DIVIDER_SHIFT; 370 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 371 /* Enable clock. */ 372 clk |= SDHCI_CLOCK_INT_EN; 373 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 374 /* Wait up to 10 ms until it stabilize. */ 375 timeout = 10; 376 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 377 & SDHCI_CLOCK_INT_STABLE)) { 378 if (timeout == 0) { 379 slot_printf(slot, 380 "Internal clock never stabilised.\n"); 381 sdhci_dumpregs(slot); 382 return; 383 } 384 timeout--; 385 DELAY(1000); 386 } 387 /* Pass clock signal to the bus. */ 388 clk |= SDHCI_CLOCK_CARD_EN; 389 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 390 } 391 392 static void 393 sdhci_set_power(struct sdhci_slot *slot, u_char power) 394 { 395 uint8_t pwr; 396 397 if (slot->power == power) 398 return; 399 slot->power = power; 400 401 /* Turn off the power. */ 402 pwr = 0; 403 WR1(slot, SDHCI_POWER_CONTROL, pwr); 404 /* If power down requested - left it so. */ 405 if (power == 0) 406 return; 407 /* Set voltage. */ 408 switch (1 << power) { 409 case MMC_OCR_LOW_VOLTAGE: 410 pwr |= SDHCI_POWER_180; 411 break; 412 case MMC_OCR_290_300: 413 case MMC_OCR_300_310: 414 pwr |= SDHCI_POWER_300; 415 break; 416 case MMC_OCR_320_330: 417 case MMC_OCR_330_340: 418 pwr |= SDHCI_POWER_330; 419 break; 420 } 421 WR1(slot, SDHCI_POWER_CONTROL, pwr); 422 /* Turn on the power. */ 423 pwr |= SDHCI_POWER_ON; 424 WR1(slot, SDHCI_POWER_CONTROL, pwr); 425 } 426 427 static void 428 sdhci_read_block_pio(struct sdhci_slot *slot) 429 { 430 uint32_t data; 431 char *buffer; 432 size_t left; 433 434 buffer = slot->curcmd->data->data; 435 buffer += slot->offset; 436 /* Transfer one block at a time. */ 437 left = min(512, slot->curcmd->data->len - slot->offset); 438 slot->offset += left; 439 440 /* If we are too fast, broken controllers return zeroes. */ 441 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 442 DELAY(10); 443 /* Handle unalligned and alligned buffer cases. */ 444 if ((intptr_t)buffer & 3) { 445 while (left > 3) { 446 data = RD4(slot, SDHCI_BUFFER); 447 buffer[0] = data; 448 buffer[1] = (data >> 8); 449 buffer[2] = (data >> 16); 450 buffer[3] = (data >> 24); 451 buffer += 4; 452 left -= 4; 453 } 454 } else { 455 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 456 (uint32_t *)buffer, left >> 2); 457 left &= 3; 458 } 459 /* Handle uneven size case. */ 460 if (left > 0) { 461 data = RD4(slot, SDHCI_BUFFER); 462 while (left > 0) { 463 *(buffer++) = data; 464 data >>= 8; 465 left--; 466 } 467 } 468 } 469 470 static void 471 sdhci_write_block_pio(struct sdhci_slot *slot) 472 { 473 uint32_t data = 0; 474 char *buffer; 475 size_t left; 476 477 buffer = slot->curcmd->data->data; 478 buffer += slot->offset; 479 /* Transfer one block at a time. */ 480 left = min(512, slot->curcmd->data->len - slot->offset); 481 slot->offset += left; 482 483 /* Handle unalligned and alligned buffer cases. */ 484 if ((intptr_t)buffer & 3) { 485 while (left > 3) { 486 data = buffer[0] + 487 (buffer[1] << 8) + 488 (buffer[2] << 16) + 489 (buffer[3] << 24); 490 left -= 4; 491 buffer += 4; 492 WR4(slot, SDHCI_BUFFER, data); 493 } 494 } else { 495 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 496 (uint32_t *)buffer, left >> 2); 497 left &= 3; 498 } 499 /* Handle uneven size case. */ 500 if (left > 0) { 501 while (left > 0) { 502 data <<= 8; 503 data += *(buffer++); 504 left--; 505 } 506 WR4(slot, SDHCI_BUFFER, data); 507 } 508 } 509 510 static void 511 sdhci_transfer_pio(struct sdhci_slot *slot) 512 { 513 514 /* Read as many blocks as possible. */ 515 if (slot->curcmd->data->flags & MMC_DATA_READ) { 516 while (RD4(slot, SDHCI_PRESENT_STATE) & 517 SDHCI_DATA_AVAILABLE) { 518 sdhci_read_block_pio(slot); 519 if (slot->offset >= slot->curcmd->data->len) 520 break; 521 } 522 } else { 523 while (RD4(slot, SDHCI_PRESENT_STATE) & 524 SDHCI_SPACE_AVAILABLE) { 525 sdhci_write_block_pio(slot); 526 if (slot->offset >= slot->curcmd->data->len) 527 break; 528 } 529 } 530 } 531 532 static void 533 sdhci_card_delay(void *arg) 534 { 535 struct sdhci_slot *slot = arg; 536 537 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 538 } 539 540 static void 541 sdhci_card_task(void *arg, int pending) 542 { 543 struct sdhci_slot *slot = arg; 544 545 SDHCI_LOCK(slot); 546 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 547 if (slot->dev == NULL) { 548 /* If card is present - attach mmc bus. */ 549 slot->dev = device_add_child(slot->sc->dev, "mmc", -1); 550 device_set_ivars(slot->dev, slot); 551 SDHCI_UNLOCK(slot); 552 device_probe_and_attach(slot->dev); 553 } else 554 SDHCI_UNLOCK(slot); 555 } else { 556 if (slot->dev != NULL) { 557 /* If no card present - detach mmc bus. */ 558 device_t d = slot->dev; 559 slot->dev = NULL; 560 SDHCI_UNLOCK(slot); 561 device_delete_child(slot->sc->dev, d); 562 } else 563 SDHCI_UNLOCK(slot); 564 } 565 } 566 567 static int 568 sdhci_probe(device_t dev) 569 { 570 uint32_t model; 571 uint16_t subvendor; 572 uint8_t class, subclass; 573 int i, result; 574 575 model = (uint32_t)pci_get_device(dev) << 16; 576 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 577 subvendor = pci_get_subvendor(dev); 578 class = pci_get_class(dev); 579 subclass = pci_get_subclass(dev); 580 581 result = ENXIO; 582 for (i = 0; sdhci_devices[i].model != 0; i++) { 583 if (sdhci_devices[i].model == model && 584 (sdhci_devices[i].subvendor == 0xffff || 585 sdhci_devices[i].subvendor == subvendor)) { 586 device_set_desc(dev, sdhci_devices[i].desc); 587 result = BUS_PROBE_DEFAULT; 588 break; 589 } 590 } 591 if (result == ENXIO && class == PCIC_BASEPERIPH && 592 subclass == PCIS_BASEPERIPH_SDHC) { 593 device_set_desc(dev, "Generic SD HCI"); 594 result = BUS_PROBE_GENERIC; 595 } 596 597 return (result); 598 } 599 600 static int 601 sdhci_attach(device_t dev) 602 { 603 struct sdhci_softc *sc = device_get_softc(dev); 604 uint32_t model; 605 uint16_t subvendor; 606 uint8_t class, subclass, progif; 607 int err, slots, bar, i; 608 609 sc->dev = dev; 610 model = (uint32_t)pci_get_device(dev) << 16; 611 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 612 subvendor = pci_get_subvendor(dev); 613 class = pci_get_class(dev); 614 subclass = pci_get_subclass(dev); 615 progif = pci_get_progif(dev); 616 /* Apply chip specific quirks. */ 617 for (i = 0; sdhci_devices[i].model != 0; i++) { 618 if (sdhci_devices[i].model == model && 619 (sdhci_devices[i].subvendor == 0xffff || 620 sdhci_devices[i].subvendor == subvendor)) { 621 sc->quirks = sdhci_devices[i].quirks; 622 break; 623 } 624 } 625 /* Read slots info from PCI registers. */ 626 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 627 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 628 slots = PCI_SLOT_INFO_SLOTS(slots); 629 if (slots > 6 || bar > 5) { 630 device_printf(dev, "Incorrect slots information (%d, %d).\n", 631 slots, bar); 632 return (EINVAL); 633 } 634 /* Allocate IRQ. */ 635 sc->irq_rid = 0; 636 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 637 RF_SHAREABLE | RF_ACTIVE); 638 if (sc->irq_res == NULL) { 639 device_printf(dev, "Can't allocate IRQ\n"); 640 return (ENOMEM); 641 } 642 /* Scan all slots. */ 643 for (i = 0; i < slots; i++) { 644 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 645 uint32_t caps; 646 647 SDHCI_LOCK_INIT(slot); 648 slot->sc = sc; 649 slot->num = sc->num_slots; 650 /* Allocate memory. */ 651 slot->mem_rid = PCIR_BAR(bar + i); 652 slot->mem_res = bus_alloc_resource(dev, 653 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 654 if (slot->mem_res == NULL) { 655 device_printf(dev, "Can't allocate memory\n"); 656 SDHCI_LOCK_DESTROY(slot); 657 continue; 658 } 659 /* Allocate DMA tag. */ 660 err = bus_dma_tag_create(bus_get_dma_tag(dev), 661 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 662 BUS_SPACE_MAXADDR, NULL, NULL, 663 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 664 BUS_DMA_ALLOCNOW, NULL, NULL, 665 &slot->dmatag); 666 if (err != 0) { 667 device_printf(dev, "Can't create DMA tag\n"); 668 SDHCI_LOCK_DESTROY(slot); 669 continue; 670 } 671 /* Allocate DMA memory. */ 672 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 673 BUS_DMA_NOWAIT, &slot->dmamap); 674 if (err != 0) { 675 device_printf(dev, "Can't alloc DMA memory\n"); 676 SDHCI_LOCK_DESTROY(slot); 677 continue; 678 } 679 /* Map the memory. */ 680 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 681 (void *)slot->dmamem, DMA_BLOCK_SIZE, 682 sdhci_getaddr, &slot->paddr, 0); 683 if (err != 0 || slot->paddr == 0) { 684 device_printf(dev, "Can't load DMA memory\n"); 685 SDHCI_LOCK_DESTROY(slot); 686 continue; 687 } 688 /* Initialize slot. */ 689 sdhci_init(slot); 690 caps = RD4(slot, SDHCI_CAPABILITIES); 691 /* Calculate base clock frequency. */ 692 slot->max_clk = 693 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 694 if (slot->max_clk == 0) { 695 device_printf(dev, "Hardware doesn't specify base clock " 696 "frequency.\n"); 697 } 698 slot->max_clk *= 1000000; 699 /* Calculate timeout clock frequency. */ 700 slot->timeout_clk = 701 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 702 if (slot->timeout_clk == 0) { 703 device_printf(dev, "Hardware doesn't specify timeout clock " 704 "frequency.\n"); 705 } 706 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 707 slot->timeout_clk *= 1000; 708 709 slot->host.f_min = slot->max_clk / 256; 710 slot->host.f_max = slot->max_clk; 711 slot->host.host_ocr = 0; 712 if (caps & SDHCI_CAN_VDD_330) 713 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 714 if (caps & SDHCI_CAN_VDD_300) 715 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 716 if (caps & SDHCI_CAN_VDD_180) 717 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 718 if (slot->host.host_ocr == 0) { 719 device_printf(dev, "Hardware doesn't report any " 720 "support voltages.\n"); 721 } 722 slot->host.caps = MMC_CAP_4_BIT_DATA; 723 if (caps & SDHCI_CAN_DO_HISPD) 724 slot->host.caps |= MMC_CAP_HSPEED; 725 /* Decide if we have usable DMA. */ 726 if (caps & SDHCI_CAN_DO_DMA) 727 slot->opt |= SDHCI_HAVE_DMA; 728 if (class == PCIC_BASEPERIPH && 729 subclass == PCIS_BASEPERIPH_SDHC && 730 progif != PCI_SDHCI_IFDMA) 731 slot->opt &= ~SDHCI_HAVE_DMA; 732 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) 733 slot->opt &= ~SDHCI_HAVE_DMA; 734 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) 735 slot->opt |= SDHCI_HAVE_DMA; 736 737 if (bootverbose) { 738 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 739 slot->max_clk / 1000000, 740 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 741 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 742 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 743 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 744 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 745 sdhci_dumpregs(slot); 746 } 747 748 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 749 callout_init(&slot->card_callout, 1); 750 sc->num_slots++; 751 } 752 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 753 /* Activate the interrupt */ 754 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 755 NULL, sdhci_intr, sc, &sc->intrhand); 756 if (err) 757 device_printf(dev, "Can't setup IRQ\n"); 758 pci_enable_busmaster(dev); 759 /* Process cards detection. */ 760 for (i = 0; i < sc->num_slots; i++) { 761 struct sdhci_slot *slot = &sc->slots[i]; 762 763 sdhci_card_task(slot, 0); 764 } 765 766 return (0); 767 } 768 769 static int 770 sdhci_detach(device_t dev) 771 { 772 struct sdhci_softc *sc = device_get_softc(dev); 773 int i; 774 775 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 776 bus_release_resource(dev, SYS_RES_IRQ, 777 sc->irq_rid, sc->irq_res); 778 779 for (i = 0; i < sc->num_slots; i++) { 780 struct sdhci_slot *slot = &sc->slots[i]; 781 device_t d; 782 783 callout_drain(&slot->card_callout); 784 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 785 786 SDHCI_LOCK(slot); 787 d = slot->dev; 788 slot->dev = NULL; 789 SDHCI_UNLOCK(slot); 790 if (d != NULL) 791 device_delete_child(dev, d); 792 793 SDHCI_LOCK(slot); 794 sdhci_reset(slot, SDHCI_RESET_ALL); 795 SDHCI_UNLOCK(slot); 796 bus_dmamap_unload(slot->dmatag, slot->dmamap); 797 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 798 bus_dma_tag_destroy(slot->dmatag); 799 bus_release_resource(dev, SYS_RES_MEMORY, 800 slot->mem_rid, slot->mem_res); 801 SDHCI_LOCK_DESTROY(slot); 802 } 803 return (0); 804 } 805 806 static int 807 sdhci_suspend(device_t dev) 808 { 809 struct sdhci_softc *sc = device_get_softc(dev); 810 int i, err; 811 812 err = bus_generic_suspend(dev); 813 if (err) 814 return (err); 815 for (i = 0; i < sc->num_slots; i++) 816 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); 817 return (0); 818 } 819 820 static int 821 sdhci_resume(device_t dev) 822 { 823 struct sdhci_softc *sc = device_get_softc(dev); 824 int i; 825 826 for (i = 0; i < sc->num_slots; i++) 827 sdhci_init(&sc->slots[i]); 828 return (bus_generic_resume(dev)); 829 } 830 831 static int 832 sdhci_update_ios(device_t brdev, device_t reqdev) 833 { 834 struct sdhci_slot *slot = device_get_ivars(reqdev); 835 struct mmc_ios *ios = &slot->host.ios; 836 837 SDHCI_LOCK(slot); 838 /* Do full reset on bus power down to clear from any state. */ 839 if (ios->power_mode == power_off) { 840 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 841 sdhci_init(slot); 842 } 843 /* Configure the bus. */ 844 sdhci_set_clock(slot, ios->clock); 845 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 846 if (ios->bus_width == bus_width_4) 847 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 848 else 849 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 850 if (ios->timing == bus_timing_hs) 851 slot->hostctrl |= SDHCI_CTRL_HISPD; 852 else 853 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 854 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 855 /* Some controllers like reset after bus changes. */ 856 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) 857 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 858 859 SDHCI_UNLOCK(slot); 860 return (0); 861 } 862 863 static void 864 sdhci_set_transfer_mode(struct sdhci_slot *slot, 865 struct mmc_data *data) 866 { 867 uint16_t mode; 868 869 if (data == NULL) 870 return; 871 872 mode = SDHCI_TRNS_BLK_CNT_EN; 873 if (data->len > 512) 874 mode |= SDHCI_TRNS_MULTI; 875 if (data->flags & MMC_DATA_READ) 876 mode |= SDHCI_TRNS_READ; 877 if (slot->req->stop) 878 mode |= SDHCI_TRNS_ACMD12; 879 if (slot->flags & SDHCI_USE_DMA) 880 mode |= SDHCI_TRNS_DMA; 881 882 WR2(slot, SDHCI_TRANSFER_MODE, mode); 883 } 884 885 static void 886 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 887 { 888 struct mmc_request *req = slot->req; 889 int flags, timeout; 890 uint32_t mask, state; 891 892 slot->curcmd = cmd; 893 slot->cmd_done = 0; 894 895 cmd->error = MMC_ERR_NONE; 896 897 /* This flags combination is not supported by controller. */ 898 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 899 slot_printf(slot, "Unsupported response type!\n"); 900 cmd->error = MMC_ERR_FAILED; 901 slot->req = NULL; 902 slot->curcmd = NULL; 903 req->done(req); 904 return; 905 } 906 907 /* Read controller present state. */ 908 state = RD4(slot, SDHCI_PRESENT_STATE); 909 /* Do not issue command if there is no card, clock or power. 910 * Controller will not detect timeout without clock active. */ 911 if ((state & SDHCI_CARD_PRESENT) == 0 || 912 slot->power == 0 || 913 slot->clock == 0) { 914 cmd->error = MMC_ERR_FAILED; 915 slot->req = NULL; 916 slot->curcmd = NULL; 917 req->done(req); 918 return; 919 } 920 /* Always wait for free CMD bus. */ 921 mask = SDHCI_CMD_INHIBIT; 922 /* Wait for free DAT if we have data or busy signal. */ 923 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 924 mask |= SDHCI_DAT_INHIBIT; 925 /* We shouldn't wait for DAT for stop commands. */ 926 if (cmd == slot->req->stop) 927 mask &= ~SDHCI_DAT_INHIBIT; 928 /* Wait for bus no more then 10 ms. */ 929 timeout = 10; 930 while (state & mask) { 931 if (timeout == 0) { 932 slot_printf(slot, "Controller never released " 933 "inhibit bit(s).\n"); 934 sdhci_dumpregs(slot); 935 cmd->error = MMC_ERR_FAILED; 936 slot->req = NULL; 937 slot->curcmd = NULL; 938 req->done(req); 939 return; 940 } 941 timeout--; 942 DELAY(1000); 943 state = RD4(slot, SDHCI_PRESENT_STATE); 944 } 945 946 /* Prepare command flags. */ 947 if (!(cmd->flags & MMC_RSP_PRESENT)) 948 flags = SDHCI_CMD_RESP_NONE; 949 else if (cmd->flags & MMC_RSP_136) 950 flags = SDHCI_CMD_RESP_LONG; 951 else if (cmd->flags & MMC_RSP_BUSY) 952 flags = SDHCI_CMD_RESP_SHORT_BUSY; 953 else 954 flags = SDHCI_CMD_RESP_SHORT; 955 if (cmd->flags & MMC_RSP_CRC) 956 flags |= SDHCI_CMD_CRC; 957 if (cmd->flags & MMC_RSP_OPCODE) 958 flags |= SDHCI_CMD_INDEX; 959 if (cmd->data) 960 flags |= SDHCI_CMD_DATA; 961 if (cmd->opcode == MMC_STOP_TRANSMISSION) 962 flags |= SDHCI_CMD_TYPE_ABORT; 963 /* Prepare data. */ 964 sdhci_start_data(slot, cmd->data); 965 /* 966 * Interrupt aggregation: To reduce total number of interrupts 967 * group response interrupt with data interrupt when possible. 968 * If there going to be data interrupt, mask response one. 969 */ 970 if (slot->data_done == 0) { 971 WR4(slot, SDHCI_SIGNAL_ENABLE, 972 slot->intmask &= ~SDHCI_INT_RESPONSE); 973 } 974 /* Set command argument. */ 975 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 976 /* Set data transfer mode. */ 977 sdhci_set_transfer_mode(slot, cmd->data); 978 /* Set command flags. */ 979 WR1(slot, SDHCI_COMMAND_FLAGS, flags); 980 /* Start command. */ 981 WR1(slot, SDHCI_COMMAND, cmd->opcode); 982 } 983 984 static void 985 sdhci_finish_command(struct sdhci_slot *slot) 986 { 987 int i; 988 989 slot->cmd_done = 1; 990 /* Interrupt aggregation: Restore command interrupt. 991 * Main restore point for the case when command interrupt 992 * happened first. */ 993 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 994 /* In case of error - reset host and return. */ 995 if (slot->curcmd->error) { 996 sdhci_reset(slot, SDHCI_RESET_CMD); 997 sdhci_reset(slot, SDHCI_RESET_DATA); 998 sdhci_start(slot); 999 return; 1000 } 1001 /* If command has response - fetch it. */ 1002 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1003 if (slot->curcmd->flags & MMC_RSP_136) { 1004 /* CRC is stripped so we need one byte shift. */ 1005 uint8_t extra = 0; 1006 for (i = 0; i < 4; i++) { 1007 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1008 slot->curcmd->resp[3 - i] = (val << 8) + extra; 1009 extra = val >> 24; 1010 } 1011 } else 1012 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1013 } 1014 /* If data ready - finish. */ 1015 if (slot->data_done) 1016 sdhci_start(slot); 1017 } 1018 1019 static void 1020 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1021 { 1022 uint32_t target_timeout, current_timeout; 1023 uint8_t div; 1024 1025 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1026 slot->data_done = 1; 1027 return; 1028 } 1029 1030 slot->data_done = 0; 1031 1032 /* Calculate and set data timeout.*/ 1033 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1034 target_timeout = 1000000; 1035 div = 0; 1036 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1037 while (current_timeout < target_timeout) { 1038 div++; 1039 current_timeout <<= 1; 1040 if (div >= 0xF) 1041 break; 1042 } 1043 /* Compensate for an off-by-one error in the CaFe chip.*/ 1044 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 1045 div++; 1046 if (div >= 0xF) { 1047 slot_printf(slot, "Timeout too large!\n"); 1048 div = 0xE; 1049 } 1050 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1051 1052 if (data == NULL) 1053 return; 1054 1055 /* Use DMA if possible. */ 1056 if ((slot->opt & SDHCI_HAVE_DMA)) 1057 slot->flags |= SDHCI_USE_DMA; 1058 /* If data is small, broken DMA may return zeroes instead of data, */ 1059 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1060 (data->len <= 512)) 1061 slot->flags &= ~SDHCI_USE_DMA; 1062 /* Some controllers require even block sizes. */ 1063 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1064 ((data->len) & 0x3)) 1065 slot->flags &= ~SDHCI_USE_DMA; 1066 /* Load DMA buffer. */ 1067 if (slot->flags & SDHCI_USE_DMA) { 1068 if (data->flags & MMC_DATA_READ) 1069 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 1070 else { 1071 memcpy(slot->dmamem, data->data, 1072 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 1073 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 1074 } 1075 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1076 /* Interrupt aggregation: Mask border interrupt 1077 * for the last page and unmask else. */ 1078 if (data->len == DMA_BLOCK_SIZE) 1079 slot->intmask &= ~SDHCI_INT_DMA_END; 1080 else 1081 slot->intmask |= SDHCI_INT_DMA_END; 1082 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1083 } 1084 /* Current data offset for both PIO and DMA. */ 1085 slot->offset = 0; 1086 /* Set block size and request IRQ on 4K border. */ 1087 WR2(slot, SDHCI_BLOCK_SIZE, 1088 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1089 /* Set block count. */ 1090 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1091 } 1092 1093 static void 1094 sdhci_finish_data(struct sdhci_slot *slot) 1095 { 1096 struct mmc_data *data = slot->curcmd->data; 1097 1098 slot->data_done = 1; 1099 /* Interrupt aggregation: Restore command interrupt. 1100 * Auxillary restore point for the case when data interrupt 1101 * happened first. */ 1102 if (!slot->cmd_done) { 1103 WR4(slot, SDHCI_SIGNAL_ENABLE, 1104 slot->intmask |= SDHCI_INT_RESPONSE); 1105 } 1106 /* Unload rest of data from DMA buffer. */ 1107 if (slot->flags & SDHCI_USE_DMA) { 1108 if (data->flags & MMC_DATA_READ) { 1109 size_t left = data->len - slot->offset; 1110 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1111 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1112 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1113 } else 1114 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1115 } 1116 /* If there was error - reset the host. */ 1117 if (slot->curcmd->error) { 1118 sdhci_reset(slot, SDHCI_RESET_CMD); 1119 sdhci_reset(slot, SDHCI_RESET_DATA); 1120 sdhci_start(slot); 1121 return; 1122 } 1123 /* If we already have command response - finish. */ 1124 if (slot->cmd_done) 1125 sdhci_start(slot); 1126 } 1127 1128 static void 1129 sdhci_start(struct sdhci_slot *slot) 1130 { 1131 struct mmc_request *req; 1132 1133 req = slot->req; 1134 if (req == NULL) 1135 return; 1136 1137 if (!(slot->flags & CMD_STARTED)) { 1138 slot->flags |= CMD_STARTED; 1139 sdhci_start_command(slot, req->cmd); 1140 return; 1141 } 1142 /* We don't need this until using Auto-CMD12 feature 1143 if (!(slot->flags & STOP_STARTED) && req->stop) { 1144 slot->flags |= STOP_STARTED; 1145 sdhci_start_command(slot, req->stop); 1146 return; 1147 } 1148 */ 1149 if (req->cmd->error) { 1150 if (bootverbose) { 1151 slot_printf(slot, 1152 "Command error %d (opcode %u arg %u flags %u " 1153 "dlen %u dflags %u)\n", 1154 req->cmd->error, req->cmd->opcode, req->cmd->arg, 1155 req->cmd->flags, 1156 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1157 (req->cmd->data)?(u_int)req->cmd->data->flags:0); 1158 } 1159 } else if (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST) { 1160 sdhci_reset(slot, SDHCI_RESET_CMD); 1161 sdhci_reset(slot, SDHCI_RESET_DATA); 1162 } 1163 1164 /* We must be done -- bad idea to do this while locked? */ 1165 slot->req = NULL; 1166 slot->curcmd = NULL; 1167 req->done(req); 1168 } 1169 1170 static int 1171 sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1172 { 1173 struct sdhci_slot *slot = device_get_ivars(reqdev); 1174 1175 SDHCI_LOCK(slot); 1176 if (slot->req != NULL) { 1177 SDHCI_UNLOCK(slot); 1178 return (EBUSY); 1179 } 1180 /* printf("%s cmd op %u arg %u flags %u data %ju\n", __func__, 1181 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1182 (req->cmd->data)?req->cmd->data->len:0); */ 1183 slot->req = req; 1184 slot->flags = 0; 1185 sdhci_start(slot); 1186 SDHCI_UNLOCK(slot); 1187 return (0); 1188 } 1189 1190 static int 1191 sdhci_get_ro(device_t brdev, device_t reqdev) 1192 { 1193 struct sdhci_slot *slot = device_get_ivars(reqdev); 1194 uint32_t val; 1195 1196 SDHCI_LOCK(slot); 1197 val = RD4(slot, SDHCI_PRESENT_STATE); 1198 SDHCI_UNLOCK(slot); 1199 return (!(val & SDHCI_WRITE_PROTECT)); 1200 } 1201 1202 static int 1203 sdhci_acquire_host(device_t brdev, device_t reqdev) 1204 { 1205 struct sdhci_slot *slot = device_get_ivars(reqdev); 1206 int err = 0; 1207 1208 SDHCI_LOCK(slot); 1209 while (slot->bus_busy) 1210 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1211 slot->bus_busy++; 1212 /* Activate led. */ 1213 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1214 SDHCI_UNLOCK(slot); 1215 return (err); 1216 } 1217 1218 static int 1219 sdhci_release_host(device_t brdev, device_t reqdev) 1220 { 1221 struct sdhci_slot *slot = device_get_ivars(reqdev); 1222 1223 SDHCI_LOCK(slot); 1224 /* Deactivate led. */ 1225 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1226 slot->bus_busy--; 1227 SDHCI_UNLOCK(slot); 1228 wakeup(slot); 1229 return (0); 1230 } 1231 1232 static void 1233 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1234 { 1235 1236 if (!slot->curcmd) { 1237 slot_printf(slot, "Got command interrupt 0x%08x, but " 1238 "there is no active command.\n", intmask); 1239 sdhci_dumpregs(slot); 1240 return; 1241 } 1242 if (intmask & SDHCI_INT_TIMEOUT) 1243 slot->curcmd->error = MMC_ERR_TIMEOUT; 1244 else if (intmask & SDHCI_INT_CRC) 1245 slot->curcmd->error = MMC_ERR_BADCRC; 1246 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1247 slot->curcmd->error = MMC_ERR_FIFO; 1248 1249 sdhci_finish_command(slot); 1250 } 1251 1252 static void 1253 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1254 { 1255 1256 if (!slot->curcmd) { 1257 slot_printf(slot, "Got data interrupt 0x%08x, but " 1258 "there is no active command.\n", intmask); 1259 sdhci_dumpregs(slot); 1260 return; 1261 } 1262 if (slot->curcmd->data == NULL && 1263 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1264 slot_printf(slot, "Got data interrupt 0x%08x, but " 1265 "there is no active data operation.\n", 1266 intmask); 1267 sdhci_dumpregs(slot); 1268 return; 1269 } 1270 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1271 slot->curcmd->error = MMC_ERR_TIMEOUT; 1272 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1273 slot->curcmd->error = MMC_ERR_BADCRC; 1274 if (slot->curcmd->data == NULL && 1275 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1276 SDHCI_INT_DMA_END))) { 1277 slot_printf(slot, "Got data interrupt 0x%08x, but " 1278 "there is busy-only command.\n", intmask); 1279 sdhci_dumpregs(slot); 1280 slot->curcmd->error = MMC_ERR_INVALID; 1281 } 1282 if (slot->curcmd->error) { 1283 /* No need to continue after any error. */ 1284 sdhci_finish_data(slot); 1285 return; 1286 } 1287 1288 /* Handle PIO interrupt. */ 1289 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1290 sdhci_transfer_pio(slot); 1291 /* Handle DMA border. */ 1292 if (intmask & SDHCI_INT_DMA_END) { 1293 struct mmc_data *data = slot->curcmd->data; 1294 size_t left; 1295 1296 /* Unload DMA buffer... */ 1297 left = data->len - slot->offset; 1298 if (data->flags & MMC_DATA_READ) { 1299 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1300 BUS_DMASYNC_POSTREAD); 1301 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1302 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1303 } else { 1304 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1305 BUS_DMASYNC_POSTWRITE); 1306 } 1307 /* ... and reload it again. */ 1308 slot->offset += DMA_BLOCK_SIZE; 1309 left = data->len - slot->offset; 1310 if (data->flags & MMC_DATA_READ) { 1311 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1312 BUS_DMASYNC_PREREAD); 1313 } else { 1314 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1315 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1316 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1317 BUS_DMASYNC_PREWRITE); 1318 } 1319 /* Interrupt aggregation: Mask border interrupt 1320 * for the last page. */ 1321 if (left == DMA_BLOCK_SIZE) { 1322 slot->intmask &= ~SDHCI_INT_DMA_END; 1323 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1324 } 1325 /* Restart DMA. */ 1326 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1327 } 1328 /* We have got all data. */ 1329 if (intmask & SDHCI_INT_DATA_END) 1330 sdhci_finish_data(slot); 1331 } 1332 1333 static void 1334 sdhci_acmd_irq(struct sdhci_slot *slot) 1335 { 1336 uint16_t err; 1337 1338 err = RD4(slot, SDHCI_ACMD12_ERR); 1339 if (!slot->curcmd) { 1340 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1341 "there is no active command.\n", err); 1342 sdhci_dumpregs(slot); 1343 return; 1344 } 1345 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1346 sdhci_reset(slot, SDHCI_RESET_CMD); 1347 } 1348 1349 static void 1350 sdhci_intr(void *arg) 1351 { 1352 struct sdhci_softc *sc = (struct sdhci_softc *)arg; 1353 int i; 1354 1355 for (i = 0; i < sc->num_slots; i++) { 1356 struct sdhci_slot *slot = &sc->slots[i]; 1357 uint32_t intmask; 1358 1359 SDHCI_LOCK(slot); 1360 /* Read slot interrupt status. */ 1361 intmask = RD4(slot, SDHCI_INT_STATUS); 1362 if (intmask == 0 || intmask == 0xffffffff) { 1363 SDHCI_UNLOCK(slot); 1364 continue; 1365 } 1366 /* 1367 slot_printf(slot, "got interrupt %x\n", intmask); 1368 */ 1369 /* Handle card presence interrupts. */ 1370 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1371 WR4(slot, SDHCI_INT_STATUS, intmask & 1372 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1373 1374 if (intmask & SDHCI_INT_CARD_REMOVE) { 1375 if (bootverbose) 1376 slot_printf(slot, "Card removed\n"); 1377 callout_stop(&slot->card_callout); 1378 taskqueue_enqueue(taskqueue_swi_giant, 1379 &slot->card_task); 1380 } 1381 if (intmask & SDHCI_INT_CARD_INSERT) { 1382 if (bootverbose) 1383 slot_printf(slot, "Card inserted\n"); 1384 callout_reset(&slot->card_callout, hz / 2, 1385 sdhci_card_delay, slot); 1386 } 1387 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1388 } 1389 /* Handle command interrupts. */ 1390 if (intmask & SDHCI_INT_CMD_MASK) { 1391 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1392 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1393 } 1394 /* Handle data interrupts. */ 1395 if (intmask & SDHCI_INT_DATA_MASK) { 1396 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1397 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1398 } 1399 /* Handle AutoCMD12 error interrupt. */ 1400 if (intmask & SDHCI_INT_ACMD12ERR) { 1401 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1402 sdhci_acmd_irq(slot); 1403 } 1404 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1405 intmask &= ~SDHCI_INT_ACMD12ERR; 1406 intmask &= ~SDHCI_INT_ERROR; 1407 /* Handle bus power interrupt. */ 1408 if (intmask & SDHCI_INT_BUS_POWER) { 1409 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1410 slot_printf(slot, 1411 "Card is consuming too much power!\n"); 1412 intmask &= ~SDHCI_INT_BUS_POWER; 1413 } 1414 /* The rest is unknown. */ 1415 if (intmask) { 1416 WR4(slot, SDHCI_INT_STATUS, intmask); 1417 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1418 intmask); 1419 sdhci_dumpregs(slot); 1420 } 1421 1422 SDHCI_UNLOCK(slot); 1423 } 1424 } 1425 1426 static int 1427 sdhci_read_ivar(device_t bus, device_t child, int which, u_char *result) 1428 { 1429 struct sdhci_slot *slot = device_get_ivars(child); 1430 1431 switch (which) { 1432 default: 1433 return (EINVAL); 1434 case MMCBR_IVAR_BUS_MODE: 1435 *(int *)result = slot->host.ios.bus_mode; 1436 break; 1437 case MMCBR_IVAR_BUS_WIDTH: 1438 *(int *)result = slot->host.ios.bus_width; 1439 break; 1440 case MMCBR_IVAR_CHIP_SELECT: 1441 *(int *)result = slot->host.ios.chip_select; 1442 break; 1443 case MMCBR_IVAR_CLOCK: 1444 *(int *)result = slot->host.ios.clock; 1445 break; 1446 case MMCBR_IVAR_F_MIN: 1447 *(int *)result = slot->host.f_min; 1448 break; 1449 case MMCBR_IVAR_F_MAX: 1450 *(int *)result = slot->host.f_max; 1451 break; 1452 case MMCBR_IVAR_HOST_OCR: 1453 *(int *)result = slot->host.host_ocr; 1454 break; 1455 case MMCBR_IVAR_MODE: 1456 *(int *)result = slot->host.mode; 1457 break; 1458 case MMCBR_IVAR_OCR: 1459 *(int *)result = slot->host.ocr; 1460 break; 1461 case MMCBR_IVAR_POWER_MODE: 1462 *(int *)result = slot->host.ios.power_mode; 1463 break; 1464 case MMCBR_IVAR_VDD: 1465 *(int *)result = slot->host.ios.vdd; 1466 break; 1467 case MMCBR_IVAR_CAPS: 1468 *(int *)result = slot->host.caps; 1469 break; 1470 case MMCBR_IVAR_TIMING: 1471 *(int *)result = slot->host.ios.timing; 1472 break; 1473 case MMCBR_IVAR_MAX_DATA: 1474 *(int *)result = 65535; 1475 break; 1476 } 1477 return (0); 1478 } 1479 1480 static int 1481 sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1482 { 1483 struct sdhci_slot *slot = device_get_ivars(child); 1484 1485 switch (which) { 1486 default: 1487 return (EINVAL); 1488 case MMCBR_IVAR_BUS_MODE: 1489 slot->host.ios.bus_mode = value; 1490 break; 1491 case MMCBR_IVAR_BUS_WIDTH: 1492 slot->host.ios.bus_width = value; 1493 break; 1494 case MMCBR_IVAR_CHIP_SELECT: 1495 slot->host.ios.chip_select = value; 1496 break; 1497 case MMCBR_IVAR_CLOCK: 1498 if (value > 0) { 1499 uint32_t clock = slot->max_clk; 1500 int i; 1501 1502 for (i = 0; i < 8; i++) { 1503 if (clock <= value) 1504 break; 1505 clock >>= 1; 1506 } 1507 slot->host.ios.clock = clock; 1508 } else 1509 slot->host.ios.clock = 0; 1510 break; 1511 case MMCBR_IVAR_MODE: 1512 slot->host.mode = value; 1513 break; 1514 case MMCBR_IVAR_OCR: 1515 slot->host.ocr = value; 1516 break; 1517 case MMCBR_IVAR_POWER_MODE: 1518 slot->host.ios.power_mode = value; 1519 break; 1520 case MMCBR_IVAR_VDD: 1521 slot->host.ios.vdd = value; 1522 break; 1523 case MMCBR_IVAR_TIMING: 1524 slot->host.ios.timing = value; 1525 break; 1526 case MMCBR_IVAR_CAPS: 1527 case MMCBR_IVAR_HOST_OCR: 1528 case MMCBR_IVAR_F_MIN: 1529 case MMCBR_IVAR_F_MAX: 1530 case MMCBR_IVAR_MAX_DATA: 1531 return (EINVAL); 1532 } 1533 return (0); 1534 } 1535 1536 static device_method_t sdhci_methods[] = { 1537 /* device_if */ 1538 DEVMETHOD(device_probe, sdhci_probe), 1539 DEVMETHOD(device_attach, sdhci_attach), 1540 DEVMETHOD(device_detach, sdhci_detach), 1541 DEVMETHOD(device_suspend, sdhci_suspend), 1542 DEVMETHOD(device_resume, sdhci_resume), 1543 1544 /* Bus interface */ 1545 DEVMETHOD(bus_read_ivar, sdhci_read_ivar), 1546 DEVMETHOD(bus_write_ivar, sdhci_write_ivar), 1547 1548 /* mmcbr_if */ 1549 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), 1550 DEVMETHOD(mmcbr_request, sdhci_request), 1551 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), 1552 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), 1553 DEVMETHOD(mmcbr_release_host, sdhci_release_host), 1554 1555 {0, 0}, 1556 }; 1557 1558 static driver_t sdhci_driver = { 1559 "sdhci", 1560 sdhci_methods, 1561 sizeof(struct sdhci_softc), 1562 }; 1563 static devclass_t sdhci_devclass; 1564 1565 1566 DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); 1567