1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/taskqueue.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 #include <machine/stdarg.h> 47 48 #include <dev/mmc/bridge.h> 49 #include <dev/mmc/mmcreg.h> 50 #include <dev/mmc/mmcbrvar.h> 51 52 #include "mmcbr_if.h" 53 #include "sdhci.h" 54 55 #define DMA_BLOCK_SIZE 4096 56 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ 57 58 /* Controller doesn't honor resets unless we touch the clock register */ 59 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 60 /* Controller really supports DMA */ 61 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 62 /* Controller has unusable DMA engine */ 63 #define SDHCI_QUIRK_BROKEN_DMA (1<<2) 64 /* Controller doesn't like to be reset when there is no card inserted. */ 65 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3) 66 /* Controller has flaky internal state so reset it on each ios change */ 67 #define SDHCI_QUIRK_RESET_ON_IOS (1<<4) 68 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 69 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5) 70 /* Controller needs to be reset after each request to stay stable */ 71 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6) 72 /* Controller has an off-by-one issue with timeout value */ 73 #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7) 74 /* Controller has broken read timings */ 75 #define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8) 76 77 static const struct sdhci_device { 78 uint32_t model; 79 uint16_t subvendor; 80 char *desc; 81 u_int quirks; 82 } sdhci_devices[] = { 83 { 0x08221180, 0xffff, "RICOH R5C822 SD", 84 SDHCI_QUIRK_FORCE_DMA }, 85 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 86 SDHCI_QUIRK_FORCE_DMA }, 87 { 0x05501524, 0xffff, "ENE CB712 SD", 88 SDHCI_QUIRK_BROKEN_TIMINGS }, 89 { 0x05511524, 0xffff, "ENE CB712 SD 2", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x07501524, 0xffff, "ENE CB714 SD", 92 SDHCI_QUIRK_RESET_ON_IOS | 93 SDHCI_QUIRK_BROKEN_TIMINGS }, 94 { 0x07511524, 0xffff, "ENE CB714 SD 2", 95 SDHCI_QUIRK_RESET_ON_IOS | 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x410111ab, 0xffff, "Marvell CaFe SD", 98 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 99 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 100 SDHCI_QUIRK_32BIT_DMA_SIZE | 101 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 102 { 0, 0xffff, NULL, 103 0 } 104 }; 105 106 struct sdhci_softc; 107 108 struct sdhci_slot { 109 struct sdhci_softc *sc; 110 device_t dev; /* Slot device */ 111 u_char num; /* Slot number */ 112 u_char opt; /* Slot options */ 113 #define SDHCI_HAVE_DMA 1 114 uint32_t max_clk; /* Max possible freq */ 115 uint32_t timeout_clk; /* Timeout freq */ 116 struct resource *mem_res; /* Memory resource */ 117 int mem_rid; 118 bus_dma_tag_t dmatag; 119 bus_dmamap_t dmamap; 120 u_char *dmamem; 121 bus_addr_t paddr; /* DMA buffer address */ 122 struct task card_task; /* Card presence check task */ 123 struct callout card_callout; /* Card insert delay callout */ 124 struct mmc_host host; /* Host parameters */ 125 struct mmc_request *req; /* Current request */ 126 struct mmc_command *curcmd; /* Current command of current request */ 127 128 uint32_t intmask; /* Current interrupt mask */ 129 uint32_t clock; /* Current clock freq. */ 130 size_t offset; /* Data buffer offset */ 131 uint8_t hostctrl; /* Current host control register */ 132 u_char power; /* Current power */ 133 u_char bus_busy; /* Bus busy status */ 134 u_char cmd_done; /* CMD command part done flag */ 135 u_char data_done; /* DAT command part done flag */ 136 u_char flags; /* Request execution flags */ 137 #define CMD_STARTED 1 138 #define STOP_STARTED 2 139 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ 140 struct mtx mtx; /* Slot mutex */ 141 }; 142 143 struct sdhci_softc { 144 device_t dev; /* Controller device */ 145 u_int quirks; /* Chip specific quirks */ 146 struct resource *irq_res; /* IRQ resource */ 147 int irq_rid; 148 void *intrhand; /* Interrupt handle */ 149 150 int num_slots; /* Number of slots on this controller */ 151 struct sdhci_slot slots[6]; 152 }; 153 154 static inline uint8_t 155 RD1(struct sdhci_slot *slot, bus_size_t off) 156 { 157 bus_barrier(slot->mem_res, 0, 0xFF, 158 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 159 return bus_read_1(slot->mem_res, off); 160 } 161 162 static inline void 163 WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val) 164 { 165 bus_barrier(slot->mem_res, 0, 0xFF, 166 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 167 bus_write_1(slot->mem_res, off, val); 168 } 169 170 static inline uint16_t 171 RD2(struct sdhci_slot *slot, bus_size_t off) 172 { 173 bus_barrier(slot->mem_res, 0, 0xFF, 174 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 175 return bus_read_2(slot->mem_res, off); 176 } 177 178 static inline void 179 WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val) 180 { 181 bus_barrier(slot->mem_res, 0, 0xFF, 182 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 183 bus_write_2(slot->mem_res, off, val); 184 } 185 186 static inline uint32_t 187 RD4(struct sdhci_slot *slot, bus_size_t off) 188 { 189 bus_barrier(slot->mem_res, 0, 0xFF, 190 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 191 return bus_read_4(slot->mem_res, off); 192 } 193 194 static inline void 195 WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val) 196 { 197 bus_barrier(slot->mem_res, 0, 0xFF, 198 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 199 bus_write_4(slot->mem_res, off, val); 200 } 201 202 /* bus entry points */ 203 static int sdhci_probe(device_t dev); 204 static int sdhci_attach(device_t dev); 205 static int sdhci_detach(device_t dev); 206 static void sdhci_intr(void *); 207 208 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 209 static void sdhci_start(struct sdhci_slot *slot); 210 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 211 212 static void sdhci_card_task(void *, int); 213 214 /* helper routines */ 215 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 216 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 217 #define SDHCI_LOCK_INIT(_slot) \ 218 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 219 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 220 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 221 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 222 223 static int 224 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 225 { 226 va_list ap; 227 int retval; 228 229 retval = printf("%s-slot%d: ", 230 device_get_nameunit(slot->sc->dev), slot->num); 231 232 va_start(ap, fmt); 233 retval += vprintf(fmt, ap); 234 va_end(ap); 235 return (retval); 236 } 237 238 static void 239 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 240 { 241 if (error != 0) { 242 printf("getaddr: error %d\n", error); 243 return; 244 } 245 *(bus_addr_t *)arg = segs[0].ds_addr; 246 } 247 248 static void 249 sdhci_dumpregs(struct sdhci_slot *slot) 250 { 251 slot_printf(slot, 252 "============== REGISTER DUMP ==============\n"); 253 254 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 255 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 256 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 257 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 258 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 259 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 260 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 261 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 262 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 263 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 264 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 265 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 266 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 267 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 268 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 269 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 270 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 271 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 272 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 273 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 274 275 slot_printf(slot, 276 "===========================================\n"); 277 } 278 279 static void 280 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 281 { 282 int timeout; 283 uint8_t res; 284 285 if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 286 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 287 SDHCI_CARD_PRESENT)) 288 return; 289 } 290 291 /* Some controllers need this kick or reset won't work. */ 292 if ((mask & SDHCI_RESET_ALL) == 0 && 293 (slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 294 uint32_t clock; 295 296 /* This is to force an update */ 297 clock = slot->clock; 298 slot->clock = 0; 299 sdhci_set_clock(slot, clock); 300 } 301 302 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 303 304 if (mask & SDHCI_RESET_ALL) 305 slot->clock = 0; 306 307 /* Wait max 100 ms */ 308 timeout = 100; 309 /* Controller clears the bits when it's done */ 310 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 311 if (timeout == 0) { 312 slot_printf(slot, 313 "Reset 0x%x never completed - 0x%x.\n", 314 (int)mask, (int)res); 315 sdhci_dumpregs(slot); 316 return; 317 } 318 timeout--; 319 DELAY(1000); 320 } 321 } 322 323 static void 324 sdhci_init(struct sdhci_slot *slot) 325 { 326 327 sdhci_reset(slot, SDHCI_RESET_ALL); 328 329 /* Enable interrupts. */ 330 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 331 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 332 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 333 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 334 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 335 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 336 SDHCI_INT_ACMD12ERR; 337 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 338 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 339 } 340 341 static void 342 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 343 { 344 uint32_t res; 345 uint16_t clk; 346 int timeout; 347 348 if (clock == slot->clock) 349 return; 350 slot->clock = clock; 351 352 /* Turn off the clock. */ 353 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 354 /* If no clock requested - left it so. */ 355 if (clock == 0) 356 return; 357 /* Looking for highest freq <= clock. */ 358 res = slot->max_clk; 359 for (clk = 1; clk < 256; clk <<= 1) { 360 if (res <= clock) 361 break; 362 res >>= 1; 363 } 364 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 365 clk >>= 1; 366 /* Now we have got divider, set it. */ 367 clk <<= SDHCI_DIVIDER_SHIFT; 368 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 369 /* Enable clock. */ 370 clk |= SDHCI_CLOCK_INT_EN; 371 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 372 /* Wait up to 10 ms until it stabilize. */ 373 timeout = 10; 374 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 375 & SDHCI_CLOCK_INT_STABLE)) { 376 if (timeout == 0) { 377 slot_printf(slot, 378 "Internal clock never stabilised.\n"); 379 sdhci_dumpregs(slot); 380 return; 381 } 382 timeout--; 383 DELAY(1000); 384 } 385 /* Pass clock signal to the bus. */ 386 clk |= SDHCI_CLOCK_CARD_EN; 387 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 388 } 389 390 static void 391 sdhci_set_power(struct sdhci_slot *slot, u_char power) 392 { 393 uint8_t pwr; 394 395 if (slot->power == power) 396 return; 397 slot->power = power; 398 399 /* Turn off the power. */ 400 pwr = 0; 401 WR1(slot, SDHCI_POWER_CONTROL, pwr); 402 /* If power down requested - left it so. */ 403 if (power == 0) 404 return; 405 /* Set voltage. */ 406 switch (1 << power) { 407 case MMC_OCR_LOW_VOLTAGE: 408 pwr |= SDHCI_POWER_180; 409 break; 410 case MMC_OCR_290_300: 411 case MMC_OCR_300_310: 412 pwr |= SDHCI_POWER_300; 413 break; 414 case MMC_OCR_320_330: 415 case MMC_OCR_330_340: 416 pwr |= SDHCI_POWER_330; 417 break; 418 } 419 WR1(slot, SDHCI_POWER_CONTROL, pwr); 420 /* Turn on the power. */ 421 pwr |= SDHCI_POWER_ON; 422 WR1(slot, SDHCI_POWER_CONTROL, pwr); 423 } 424 425 static void 426 sdhci_read_block_pio(struct sdhci_slot *slot) 427 { 428 uint32_t data; 429 char *buffer; 430 size_t left; 431 432 buffer = slot->curcmd->data->data; 433 buffer += slot->offset; 434 /* Transfer one block at a time. */ 435 left = min(512, slot->curcmd->data->len - slot->offset); 436 slot->offset += left; 437 438 /* If we are too fast, broken controllers return zeroes. */ 439 if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 440 DELAY(10); 441 /* Handle unalligned and alligned buffer cases. */ 442 if ((intptr_t)buffer & 3) { 443 while (left > 3) { 444 data = RD4(slot, SDHCI_BUFFER); 445 buffer[0] = data; 446 buffer[1] = (data >> 8); 447 buffer[2] = (data >> 16); 448 buffer[3] = (data >> 24); 449 buffer += 4; 450 left -= 4; 451 } 452 } else { 453 bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 454 (uint32_t *)buffer, left >> 2); 455 left &= 3; 456 } 457 /* Handle uneven size case. */ 458 if (left > 0) { 459 data = RD4(slot, SDHCI_BUFFER); 460 while (left > 0) { 461 *(buffer++) = data; 462 data >>= 8; 463 left--; 464 } 465 } 466 } 467 468 static void 469 sdhci_write_block_pio(struct sdhci_slot *slot) 470 { 471 uint32_t data = 0; 472 char *buffer; 473 size_t left; 474 475 buffer = slot->curcmd->data->data; 476 buffer += slot->offset; 477 /* Transfer one block at a time. */ 478 left = min(512, slot->curcmd->data->len - slot->offset); 479 slot->offset += left; 480 481 /* Handle unalligned and alligned buffer cases. */ 482 if ((intptr_t)buffer & 3) { 483 while (left > 3) { 484 data = buffer[0] + 485 (buffer[1] << 8) + 486 (buffer[2] << 16) + 487 (buffer[3] << 24); 488 left -= 4; 489 buffer += 4; 490 WR4(slot, SDHCI_BUFFER, data); 491 } 492 } else { 493 bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER, 494 (uint32_t *)buffer, left >> 2); 495 left &= 3; 496 } 497 /* Handle uneven size case. */ 498 if (left > 0) { 499 while (left > 0) { 500 data <<= 8; 501 data += *(buffer++); 502 left--; 503 } 504 WR4(slot, SDHCI_BUFFER, data); 505 } 506 } 507 508 static void 509 sdhci_transfer_pio(struct sdhci_slot *slot) 510 { 511 512 /* Read as many blocks as possible. */ 513 if (slot->curcmd->data->flags & MMC_DATA_READ) { 514 while (RD4(slot, SDHCI_PRESENT_STATE) & 515 SDHCI_DATA_AVAILABLE) { 516 sdhci_read_block_pio(slot); 517 if (slot->offset >= slot->curcmd->data->len) 518 break; 519 } 520 } else { 521 while (RD4(slot, SDHCI_PRESENT_STATE) & 522 SDHCI_SPACE_AVAILABLE) { 523 sdhci_write_block_pio(slot); 524 if (slot->offset >= slot->curcmd->data->len) 525 break; 526 } 527 } 528 } 529 530 static void 531 sdhci_card_delay(void *arg) 532 { 533 struct sdhci_slot *slot = arg; 534 535 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 536 } 537 538 static void 539 sdhci_card_task(void *arg, int pending) 540 { 541 struct sdhci_slot *slot = arg; 542 543 SDHCI_LOCK(slot); 544 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 545 if (slot->dev == NULL) { 546 /* If card is present - attach mmc bus. */ 547 slot->dev = device_add_child(slot->sc->dev, "mmc", -1); 548 device_set_ivars(slot->dev, slot); 549 SDHCI_UNLOCK(slot); 550 device_probe_and_attach(slot->dev); 551 } else 552 SDHCI_UNLOCK(slot); 553 } else { 554 if (slot->dev != NULL) { 555 /* If no card present - detach mmc bus. */ 556 device_t d = slot->dev; 557 slot->dev = NULL; 558 SDHCI_UNLOCK(slot); 559 device_delete_child(slot->sc->dev, d); 560 } else 561 SDHCI_UNLOCK(slot); 562 } 563 } 564 565 static int 566 sdhci_probe(device_t dev) 567 { 568 uint32_t model; 569 uint16_t subvendor; 570 uint8_t class, subclass; 571 int i, result; 572 573 model = (uint32_t)pci_get_device(dev) << 16; 574 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 575 subvendor = pci_get_subvendor(dev); 576 class = pci_get_class(dev); 577 subclass = pci_get_subclass(dev); 578 579 result = ENXIO; 580 for (i = 0; sdhci_devices[i].model != 0; i++) { 581 if (sdhci_devices[i].model == model && 582 (sdhci_devices[i].subvendor == 0xffff || 583 sdhci_devices[i].subvendor == subvendor)) { 584 device_set_desc(dev, sdhci_devices[i].desc); 585 result = BUS_PROBE_DEFAULT; 586 break; 587 } 588 } 589 if (result == ENXIO && class == PCIC_BASEPERIPH && 590 subclass == PCIS_BASEPERIPH_SDHC) { 591 device_set_desc(dev, "Generic SD HCI"); 592 result = BUS_PROBE_GENERIC; 593 } 594 595 return (result); 596 } 597 598 static int 599 sdhci_attach(device_t dev) 600 { 601 struct sdhci_softc *sc = device_get_softc(dev); 602 uint32_t model; 603 uint16_t subvendor; 604 uint8_t class, subclass, progif; 605 int err, slots, bar, i; 606 607 sc->dev = dev; 608 model = (uint32_t)pci_get_device(dev) << 16; 609 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 610 subvendor = pci_get_subvendor(dev); 611 class = pci_get_class(dev); 612 subclass = pci_get_subclass(dev); 613 progif = pci_get_progif(dev); 614 /* Apply chip specific quirks. */ 615 for (i = 0; sdhci_devices[i].model != 0; i++) { 616 if (sdhci_devices[i].model == model && 617 (sdhci_devices[i].subvendor == 0xffff || 618 sdhci_devices[i].subvendor == subvendor)) { 619 sc->quirks = sdhci_devices[i].quirks; 620 break; 621 } 622 } 623 /* Read slots info from PCI registers. */ 624 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 625 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 626 slots = PCI_SLOT_INFO_SLOTS(slots); 627 if (slots > 6 || bar > 5) { 628 device_printf(dev, "Incorrect slots information (%d, %d).\n", 629 slots, bar); 630 return (EINVAL); 631 } 632 /* Allocate IRQ. */ 633 sc->irq_rid = 0; 634 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 635 RF_SHAREABLE | RF_ACTIVE); 636 if (sc->irq_res == NULL) { 637 device_printf(dev, "Can't allocate IRQ\n"); 638 return (ENOMEM); 639 } 640 /* Scan all slots. */ 641 for (i = 0; i < slots; i++) { 642 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 643 uint32_t caps; 644 645 SDHCI_LOCK_INIT(slot); 646 slot->sc = sc; 647 slot->num = sc->num_slots; 648 /* Allocate memory. */ 649 slot->mem_rid = PCIR_BAR(bar + i); 650 slot->mem_res = bus_alloc_resource(dev, 651 SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 652 if (slot->mem_res == NULL) { 653 device_printf(dev, "Can't allocate memory\n"); 654 SDHCI_LOCK_DESTROY(slot); 655 continue; 656 } 657 /* Allocate DMA tag. */ 658 err = bus_dma_tag_create(bus_get_dma_tag(dev), 659 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 660 BUS_SPACE_MAXADDR, NULL, NULL, 661 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 662 BUS_DMA_ALLOCNOW, NULL, NULL, 663 &slot->dmatag); 664 if (err != 0) { 665 device_printf(dev, "Can't create DMA tag\n"); 666 SDHCI_LOCK_DESTROY(slot); 667 continue; 668 } 669 /* Allocate DMA memory. */ 670 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 671 BUS_DMA_NOWAIT, &slot->dmamap); 672 if (err != 0) { 673 device_printf(dev, "Can't alloc DMA memory\n"); 674 SDHCI_LOCK_DESTROY(slot); 675 continue; 676 } 677 /* Map the memory. */ 678 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 679 (void *)slot->dmamem, DMA_BLOCK_SIZE, 680 sdhci_getaddr, &slot->paddr, 0); 681 if (err != 0 || slot->paddr == 0) { 682 device_printf(dev, "Can't load DMA memory\n"); 683 SDHCI_LOCK_DESTROY(slot); 684 continue; 685 } 686 /* Initialize slot. */ 687 sdhci_init(slot); 688 caps = RD4(slot, SDHCI_CAPABILITIES); 689 /* Calculate base clock frequency. */ 690 slot->max_clk = 691 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 692 if (slot->max_clk == 0) { 693 device_printf(dev, "Hardware doesn't specify base clock " 694 "frequency.\n"); 695 } 696 slot->max_clk *= 1000000; 697 /* Calculate timeout clock frequency. */ 698 slot->timeout_clk = 699 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 700 if (slot->timeout_clk == 0) { 701 device_printf(dev, "Hardware doesn't specify timeout clock " 702 "frequency.\n"); 703 } 704 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 705 slot->timeout_clk *= 1000; 706 707 slot->host.f_min = slot->max_clk / 256; 708 slot->host.f_max = slot->max_clk; 709 slot->host.host_ocr = 0; 710 if (caps & SDHCI_CAN_VDD_330) 711 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 712 if (caps & SDHCI_CAN_VDD_300) 713 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 714 if (caps & SDHCI_CAN_VDD_180) 715 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 716 if (slot->host.host_ocr == 0) { 717 device_printf(dev, "Hardware doesn't report any " 718 "support voltages.\n"); 719 } 720 slot->host.caps = MMC_CAP_4_BIT_DATA; 721 if (caps & SDHCI_CAN_DO_HISPD) 722 slot->host.caps |= MMC_CAP_HSPEED; 723 /* Decide if we have usable DMA. */ 724 if (caps & SDHCI_CAN_DO_DMA) 725 slot->opt |= SDHCI_HAVE_DMA; 726 if (class == PCIC_BASEPERIPH && 727 subclass == PCIS_BASEPERIPH_SDHC && 728 progif != PCI_SDHCI_IFDMA) 729 slot->opt &= ~SDHCI_HAVE_DMA; 730 if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA) 731 slot->opt &= ~SDHCI_HAVE_DMA; 732 if (sc->quirks & SDHCI_QUIRK_FORCE_DMA) 733 slot->opt |= SDHCI_HAVE_DMA; 734 735 if (bootverbose) { 736 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 737 slot->max_clk / 1000000, 738 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 739 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 740 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 741 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 742 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 743 sdhci_dumpregs(slot); 744 } 745 746 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 747 callout_init(&slot->card_callout, 1); 748 sc->num_slots++; 749 } 750 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 751 /* Activate the interrupt */ 752 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 753 NULL, sdhci_intr, sc, &sc->intrhand); 754 if (err) 755 device_printf(dev, "Can't setup IRQ\n"); 756 pci_enable_busmaster(dev); 757 /* Process cards detection. */ 758 for (i = 0; i < sc->num_slots; i++) { 759 struct sdhci_slot *slot = &sc->slots[i]; 760 761 sdhci_card_task(slot, 0); 762 } 763 764 return (0); 765 } 766 767 static int 768 sdhci_detach(device_t dev) 769 { 770 struct sdhci_softc *sc = device_get_softc(dev); 771 int i; 772 773 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 774 bus_release_resource(dev, SYS_RES_IRQ, 775 sc->irq_rid, sc->irq_res); 776 777 for (i = 0; i < sc->num_slots; i++) { 778 struct sdhci_slot *slot = &sc->slots[i]; 779 device_t d; 780 781 callout_drain(&slot->card_callout); 782 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 783 784 SDHCI_LOCK(slot); 785 d = slot->dev; 786 slot->dev = NULL; 787 SDHCI_UNLOCK(slot); 788 if (d != NULL) 789 device_delete_child(dev, d); 790 791 SDHCI_LOCK(slot); 792 sdhci_reset(slot, SDHCI_RESET_ALL); 793 SDHCI_UNLOCK(slot); 794 bus_dmamap_unload(slot->dmatag, slot->dmamap); 795 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 796 bus_dma_tag_destroy(slot->dmatag); 797 bus_release_resource(dev, SYS_RES_MEMORY, 798 slot->mem_rid, slot->mem_res); 799 SDHCI_LOCK_DESTROY(slot); 800 } 801 return (0); 802 } 803 804 static int 805 sdhci_suspend(device_t dev) 806 { 807 struct sdhci_softc *sc = device_get_softc(dev); 808 int i, err; 809 810 err = bus_generic_suspend(dev); 811 if (err) 812 return (err); 813 for (i = 0; i < sc->num_slots; i++) 814 sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL); 815 return (0); 816 } 817 818 static int 819 sdhci_resume(device_t dev) 820 { 821 struct sdhci_softc *sc = device_get_softc(dev); 822 int i; 823 824 for (i = 0; i < sc->num_slots; i++) 825 sdhci_init(&sc->slots[i]); 826 return (bus_generic_resume(dev)); 827 } 828 829 static int 830 sdhci_update_ios(device_t brdev, device_t reqdev) 831 { 832 struct sdhci_slot *slot = device_get_ivars(reqdev); 833 struct mmc_ios *ios = &slot->host.ios; 834 835 SDHCI_LOCK(slot); 836 /* Do full reset on bus power down to clear from any state. */ 837 if (ios->power_mode == power_off) { 838 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 839 sdhci_init(slot); 840 } 841 /* Configure the bus. */ 842 sdhci_set_clock(slot, ios->clock); 843 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 844 if (ios->bus_width == bus_width_4) 845 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 846 else 847 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 848 if (ios->timing == bus_timing_hs) 849 slot->hostctrl |= SDHCI_CTRL_HISPD; 850 else 851 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 852 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 853 /* Some controllers like reset after bus changes. */ 854 if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS) 855 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 856 857 SDHCI_UNLOCK(slot); 858 return (0); 859 } 860 861 static void 862 sdhci_set_transfer_mode(struct sdhci_slot *slot, 863 struct mmc_data *data) 864 { 865 uint16_t mode; 866 867 if (data == NULL) 868 return; 869 870 mode = SDHCI_TRNS_BLK_CNT_EN; 871 if (data->len > 512) 872 mode |= SDHCI_TRNS_MULTI; 873 if (data->flags & MMC_DATA_READ) 874 mode |= SDHCI_TRNS_READ; 875 if (slot->req->stop) 876 mode |= SDHCI_TRNS_ACMD12; 877 if (slot->flags & SDHCI_USE_DMA) 878 mode |= SDHCI_TRNS_DMA; 879 880 WR2(slot, SDHCI_TRANSFER_MODE, mode); 881 } 882 883 static void 884 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 885 { 886 struct mmc_request *req = slot->req; 887 int flags, timeout; 888 uint32_t mask, state; 889 890 slot->curcmd = cmd; 891 slot->cmd_done = 0; 892 893 cmd->error = MMC_ERR_NONE; 894 895 /* This flags combination is not supported by controller. */ 896 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 897 slot_printf(slot, "Unsupported response type!\n"); 898 cmd->error = MMC_ERR_FAILED; 899 slot->req = NULL; 900 slot->curcmd = NULL; 901 req->done(req); 902 return; 903 } 904 905 /* Read controller present state. */ 906 state = RD4(slot, SDHCI_PRESENT_STATE); 907 /* Do not issue command if there is no card. */ 908 if ((state & SDHCI_CARD_PRESENT) == 0) { 909 cmd->error = MMC_ERR_FAILED; 910 slot->req = NULL; 911 slot->curcmd = NULL; 912 req->done(req); 913 return; 914 } 915 /* Always wait for free CMD bus. */ 916 mask = SDHCI_CMD_INHIBIT; 917 /* Wait for free DAT if we have data or busy signal. */ 918 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 919 mask |= SDHCI_DAT_INHIBIT; 920 /* We shouldn't wait for DAT for stop commands. */ 921 if (cmd == slot->req->stop) 922 mask &= ~SDHCI_DAT_INHIBIT; 923 /* Wait for bus no more then 10 ms. */ 924 timeout = 10; 925 while (state & mask) { 926 if (timeout == 0) { 927 slot_printf(slot, "Controller never released " 928 "inhibit bit(s).\n"); 929 sdhci_dumpregs(slot); 930 cmd->error = MMC_ERR_FAILED; 931 slot->req = NULL; 932 slot->curcmd = NULL; 933 req->done(req); 934 return; 935 } 936 timeout--; 937 DELAY(1000); 938 state = RD4(slot, SDHCI_PRESENT_STATE); 939 } 940 941 /* Prepare command flags. */ 942 if (!(cmd->flags & MMC_RSP_PRESENT)) 943 flags = SDHCI_CMD_RESP_NONE; 944 else if (cmd->flags & MMC_RSP_136) 945 flags = SDHCI_CMD_RESP_LONG; 946 else if (cmd->flags & MMC_RSP_BUSY) 947 flags = SDHCI_CMD_RESP_SHORT_BUSY; 948 else 949 flags = SDHCI_CMD_RESP_SHORT; 950 if (cmd->flags & MMC_RSP_CRC) 951 flags |= SDHCI_CMD_CRC; 952 if (cmd->flags & MMC_RSP_OPCODE) 953 flags |= SDHCI_CMD_INDEX; 954 if (cmd->data) 955 flags |= SDHCI_CMD_DATA; 956 if (cmd->opcode == MMC_STOP_TRANSMISSION) 957 flags |= SDHCI_CMD_TYPE_ABORT; 958 /* Prepare data. */ 959 sdhci_start_data(slot, cmd->data); 960 /* 961 * Interrupt aggregation: To reduce total number of interrupts 962 * group response interrupt with data interrupt when possible. 963 * If there going to be data interrupt, mask response one. 964 */ 965 if (slot->data_done == 0) { 966 WR4(slot, SDHCI_SIGNAL_ENABLE, 967 slot->intmask &= ~SDHCI_INT_RESPONSE); 968 } 969 /* Set command argument. */ 970 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 971 /* Set data transfer mode. */ 972 sdhci_set_transfer_mode(slot, cmd->data); 973 /* Set command flags. */ 974 WR1(slot, SDHCI_COMMAND_FLAGS, flags); 975 /* Start command. */ 976 WR1(slot, SDHCI_COMMAND, cmd->opcode); 977 } 978 979 static void 980 sdhci_finish_command(struct sdhci_slot *slot) 981 { 982 int i; 983 984 slot->cmd_done = 1; 985 /* Interrupt aggregation: Restore command interrupt. 986 * Main restore point for the case when command interrupt 987 * happened first. */ 988 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 989 /* In case of error - reset host and return. */ 990 if (slot->curcmd->error) { 991 sdhci_reset(slot, SDHCI_RESET_CMD); 992 sdhci_reset(slot, SDHCI_RESET_DATA); 993 sdhci_start(slot); 994 return; 995 } 996 /* If command has response - fetch it. */ 997 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 998 if (slot->curcmd->flags & MMC_RSP_136) { 999 /* CRC is stripped so we need one byte shift. */ 1000 uint8_t extra = 0; 1001 for (i = 0; i < 4; i++) { 1002 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 1003 slot->curcmd->resp[3 - i] = (val << 8) + extra; 1004 extra = val >> 24; 1005 } 1006 } else 1007 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1008 } 1009 /* If data ready - finish. */ 1010 if (slot->data_done) 1011 sdhci_start(slot); 1012 } 1013 1014 static void 1015 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1016 { 1017 uint32_t target_timeout, current_timeout; 1018 uint8_t div; 1019 1020 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1021 slot->data_done = 1; 1022 return; 1023 } 1024 1025 slot->data_done = 0; 1026 1027 /* Calculate and set data timeout.*/ 1028 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1029 target_timeout = 1000000; 1030 div = 0; 1031 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1032 while (current_timeout < target_timeout) { 1033 div++; 1034 current_timeout <<= 1; 1035 if (div >= 0xF) 1036 break; 1037 } 1038 /* Compensate for an off-by-one error in the CaFe chip.*/ 1039 if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 1040 div++; 1041 if (div >= 0xF) { 1042 slot_printf(slot, "Timeout too large!\n"); 1043 div = 0xE; 1044 } 1045 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1046 1047 if (data == NULL) 1048 return; 1049 1050 /* Use DMA if possible. */ 1051 if ((slot->opt & SDHCI_HAVE_DMA)) 1052 slot->flags |= SDHCI_USE_DMA; 1053 /* If data is small, broken DMA may return zeroes instead of data, */ 1054 if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1055 (data->len <= 512)) 1056 slot->flags &= ~SDHCI_USE_DMA; 1057 /* Some controllers require even block sizes. */ 1058 if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1059 ((data->len) & 0x3)) 1060 slot->flags &= ~SDHCI_USE_DMA; 1061 /* Load DMA buffer. */ 1062 if (slot->flags & SDHCI_USE_DMA) { 1063 if (data->flags & MMC_DATA_READ) 1064 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 1065 else { 1066 memcpy(slot->dmamem, data->data, 1067 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 1068 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 1069 } 1070 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1071 /* Interrupt aggregation: Mask border interrupt 1072 * for the last page and unmask else. */ 1073 if (data->len == DMA_BLOCK_SIZE) 1074 slot->intmask &= ~SDHCI_INT_DMA_END; 1075 else 1076 slot->intmask |= SDHCI_INT_DMA_END; 1077 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1078 } 1079 /* Current data offset for both PIO and DMA. */ 1080 slot->offset = 0; 1081 /* Set block size and request IRQ on 4K border. */ 1082 WR2(slot, SDHCI_BLOCK_SIZE, 1083 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1084 /* Set block count. */ 1085 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1086 } 1087 1088 static void 1089 sdhci_finish_data(struct sdhci_slot *slot) 1090 { 1091 struct mmc_data *data = slot->curcmd->data; 1092 1093 slot->data_done = 1; 1094 /* Interrupt aggregation: Restore command interrupt. 1095 * Auxillary restore point for the case when data interrupt 1096 * happened first. */ 1097 if (!slot->cmd_done) { 1098 WR4(slot, SDHCI_SIGNAL_ENABLE, 1099 slot->intmask |= SDHCI_INT_RESPONSE); 1100 } 1101 /* Unload rest of data from DMA buffer. */ 1102 if (slot->flags & SDHCI_USE_DMA) { 1103 if (data->flags & MMC_DATA_READ) { 1104 size_t left = data->len - slot->offset; 1105 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1106 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1107 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1108 } else 1109 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1110 } 1111 /* If there was error - reset the host. */ 1112 if (slot->curcmd->error) { 1113 sdhci_reset(slot, SDHCI_RESET_CMD); 1114 sdhci_reset(slot, SDHCI_RESET_DATA); 1115 sdhci_start(slot); 1116 return; 1117 } 1118 /* If we already have command response - finish. */ 1119 if (slot->cmd_done) 1120 sdhci_start(slot); 1121 } 1122 1123 static void 1124 sdhci_start(struct sdhci_slot *slot) 1125 { 1126 struct mmc_request *req; 1127 1128 req = slot->req; 1129 if (req == NULL) 1130 return; 1131 1132 if (!(slot->flags & CMD_STARTED)) { 1133 slot->flags |= CMD_STARTED; 1134 sdhci_start_command(slot, req->cmd); 1135 return; 1136 } 1137 /* We don't need this until using Auto-CMD12 feature 1138 if (!(slot->flags & STOP_STARTED) && req->stop) { 1139 slot->flags |= STOP_STARTED; 1140 sdhci_start_command(slot, req->stop); 1141 return; 1142 } 1143 */ 1144 if (req->cmd->error) { 1145 if (bootverbose) { 1146 slot_printf(slot, 1147 "Command error %d (opcode %u arg %u flags %u " 1148 "dlen %u dflags %u)\n", 1149 req->cmd->error, req->cmd->opcode, req->cmd->arg, 1150 req->cmd->flags, 1151 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1152 (req->cmd->data)?(u_int)req->cmd->data->flags:0); 1153 } 1154 } else if (slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST) { 1155 sdhci_reset(slot, SDHCI_RESET_CMD); 1156 sdhci_reset(slot, SDHCI_RESET_DATA); 1157 } 1158 1159 /* We must be done -- bad idea to do this while locked? */ 1160 slot->req = NULL; 1161 slot->curcmd = NULL; 1162 req->done(req); 1163 } 1164 1165 static int 1166 sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1167 { 1168 struct sdhci_slot *slot = device_get_ivars(reqdev); 1169 1170 SDHCI_LOCK(slot); 1171 if (slot->req != NULL) { 1172 SDHCI_UNLOCK(slot); 1173 return (EBUSY); 1174 } 1175 /* printf("%s cmd op %u arg %u flags %u data %ju\n", __func__, 1176 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1177 (req->cmd->data)?req->cmd->data->len:0); */ 1178 slot->req = req; 1179 slot->flags = 0; 1180 sdhci_start(slot); 1181 SDHCI_UNLOCK(slot); 1182 return (0); 1183 } 1184 1185 static int 1186 sdhci_get_ro(device_t brdev, device_t reqdev) 1187 { 1188 struct sdhci_slot *slot = device_get_ivars(reqdev); 1189 uint32_t val; 1190 1191 SDHCI_LOCK(slot); 1192 val = RD4(slot, SDHCI_PRESENT_STATE); 1193 SDHCI_UNLOCK(slot); 1194 return (!(val & SDHCI_WRITE_PROTECT)); 1195 } 1196 1197 static int 1198 sdhci_acquire_host(device_t brdev, device_t reqdev) 1199 { 1200 struct sdhci_slot *slot = device_get_ivars(reqdev); 1201 int err = 0; 1202 1203 SDHCI_LOCK(slot); 1204 while (slot->bus_busy) 1205 msleep(slot, &slot->mtx, PZERO, "sdhciah", hz / 5); 1206 slot->bus_busy++; 1207 /* Activate led. */ 1208 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1209 SDHCI_UNLOCK(slot); 1210 return (err); 1211 } 1212 1213 static int 1214 sdhci_release_host(device_t brdev, device_t reqdev) 1215 { 1216 struct sdhci_slot *slot = device_get_ivars(reqdev); 1217 1218 SDHCI_LOCK(slot); 1219 /* Deactivate led. */ 1220 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1221 slot->bus_busy--; 1222 wakeup(slot); 1223 SDHCI_UNLOCK(slot); 1224 return (0); 1225 } 1226 1227 static void 1228 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1229 { 1230 1231 if (!slot->curcmd) { 1232 slot_printf(slot, "Got command interrupt 0x%08x, but " 1233 "there is no active command.\n", intmask); 1234 sdhci_dumpregs(slot); 1235 return; 1236 } 1237 if (intmask & SDHCI_INT_TIMEOUT) 1238 slot->curcmd->error = MMC_ERR_TIMEOUT; 1239 else if (intmask & SDHCI_INT_CRC) 1240 slot->curcmd->error = MMC_ERR_BADCRC; 1241 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1242 slot->curcmd->error = MMC_ERR_FIFO; 1243 1244 sdhci_finish_command(slot); 1245 } 1246 1247 static void 1248 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1249 { 1250 1251 if (!slot->curcmd) { 1252 slot_printf(slot, "Got data interrupt 0x%08x, but " 1253 "there is no active command.\n", intmask); 1254 sdhci_dumpregs(slot); 1255 return; 1256 } 1257 if (slot->curcmd->data == NULL && 1258 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1259 slot_printf(slot, "Got data interrupt 0x%08x, but " 1260 "there is no active data operation.\n", 1261 intmask); 1262 sdhci_dumpregs(slot); 1263 return; 1264 } 1265 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1266 slot->curcmd->error = MMC_ERR_TIMEOUT; 1267 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1268 slot->curcmd->error = MMC_ERR_BADCRC; 1269 if (slot->curcmd->data == NULL && 1270 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1271 SDHCI_INT_DMA_END))) { 1272 slot_printf(slot, "Got data interrupt 0x%08x, but " 1273 "there is busy-only command.\n", intmask); 1274 sdhci_dumpregs(slot); 1275 slot->curcmd->error = MMC_ERR_INVALID; 1276 } 1277 if (slot->curcmd->error) { 1278 /* No need to continue after any error. */ 1279 sdhci_finish_data(slot); 1280 return; 1281 } 1282 1283 /* Handle PIO interrupt. */ 1284 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1285 sdhci_transfer_pio(slot); 1286 /* Handle DMA border. */ 1287 if (intmask & SDHCI_INT_DMA_END) { 1288 struct mmc_data *data = slot->curcmd->data; 1289 size_t left; 1290 1291 /* Unload DMA buffer... */ 1292 left = data->len - slot->offset; 1293 if (data->flags & MMC_DATA_READ) { 1294 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1295 BUS_DMASYNC_POSTREAD); 1296 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1297 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1298 } else { 1299 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1300 BUS_DMASYNC_POSTWRITE); 1301 } 1302 /* ... and reload it again. */ 1303 slot->offset += DMA_BLOCK_SIZE; 1304 left = data->len - slot->offset; 1305 if (data->flags & MMC_DATA_READ) { 1306 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1307 BUS_DMASYNC_PREREAD); 1308 } else { 1309 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1310 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1311 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1312 BUS_DMASYNC_PREWRITE); 1313 } 1314 /* Interrupt aggregation: Mask border interrupt 1315 * for the last page. */ 1316 if (left == DMA_BLOCK_SIZE) { 1317 slot->intmask &= ~SDHCI_INT_DMA_END; 1318 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1319 } 1320 /* Restart DMA. */ 1321 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1322 } 1323 /* We have got all data. */ 1324 if (intmask & SDHCI_INT_DATA_END) 1325 sdhci_finish_data(slot); 1326 } 1327 1328 static void 1329 sdhci_acmd_irq(struct sdhci_slot *slot) 1330 { 1331 uint16_t err; 1332 1333 err = RD4(slot, SDHCI_ACMD12_ERR); 1334 if (!slot->curcmd) { 1335 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1336 "there is no active command.\n", err); 1337 sdhci_dumpregs(slot); 1338 return; 1339 } 1340 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1341 sdhci_reset(slot, SDHCI_RESET_CMD); 1342 } 1343 1344 static void 1345 sdhci_intr(void *arg) 1346 { 1347 struct sdhci_softc *sc = (struct sdhci_softc *)arg; 1348 int i; 1349 1350 for (i = 0; i < sc->num_slots; i++) { 1351 struct sdhci_slot *slot = &sc->slots[i]; 1352 uint32_t intmask; 1353 1354 SDHCI_LOCK(slot); 1355 /* Read slot interrupt status. */ 1356 intmask = RD4(slot, SDHCI_INT_STATUS); 1357 if (intmask == 0 || intmask == 0xffffffff) { 1358 SDHCI_UNLOCK(slot); 1359 continue; 1360 } 1361 /* 1362 slot_printf(slot, "got interrupt %x\n", intmask); 1363 */ 1364 /* Handle card presence interrupts. */ 1365 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1366 WR4(slot, SDHCI_INT_STATUS, intmask & 1367 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1368 1369 if (intmask & SDHCI_INT_CARD_REMOVE) { 1370 if (bootverbose) 1371 slot_printf(slot, "Card removed\n"); 1372 callout_stop(&slot->card_callout); 1373 taskqueue_enqueue(taskqueue_swi_giant, 1374 &slot->card_task); 1375 } 1376 if (intmask & SDHCI_INT_CARD_INSERT) { 1377 if (bootverbose) 1378 slot_printf(slot, "Card inserted\n"); 1379 callout_reset(&slot->card_callout, hz / 2, 1380 sdhci_card_delay, slot); 1381 } 1382 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1383 } 1384 /* Handle command interrupts. */ 1385 if (intmask & SDHCI_INT_CMD_MASK) { 1386 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1387 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1388 } 1389 /* Handle data interrupts. */ 1390 if (intmask & SDHCI_INT_DATA_MASK) { 1391 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1392 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1393 } 1394 /* Handle AutoCMD12 error interrupt. */ 1395 if (intmask & SDHCI_INT_ACMD12ERR) { 1396 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1397 sdhci_acmd_irq(slot); 1398 } 1399 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1400 intmask &= ~SDHCI_INT_ACMD12ERR; 1401 intmask &= ~SDHCI_INT_ERROR; 1402 /* Handle bus power interrupt. */ 1403 if (intmask & SDHCI_INT_BUS_POWER) { 1404 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1405 slot_printf(slot, 1406 "Card is consuming too much power!\n"); 1407 intmask &= ~SDHCI_INT_BUS_POWER; 1408 } 1409 /* The rest is unknown. */ 1410 if (intmask) { 1411 WR4(slot, SDHCI_INT_STATUS, intmask); 1412 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1413 intmask); 1414 sdhci_dumpregs(slot); 1415 } 1416 1417 SDHCI_UNLOCK(slot); 1418 } 1419 } 1420 1421 static int 1422 sdhci_read_ivar(device_t bus, device_t child, int which, u_char *result) 1423 { 1424 struct sdhci_slot *slot = device_get_ivars(child); 1425 1426 switch (which) { 1427 default: 1428 return (EINVAL); 1429 case MMCBR_IVAR_BUS_MODE: 1430 *(int *)result = slot->host.ios.bus_mode; 1431 break; 1432 case MMCBR_IVAR_BUS_WIDTH: 1433 *(int *)result = slot->host.ios.bus_width; 1434 break; 1435 case MMCBR_IVAR_CHIP_SELECT: 1436 *(int *)result = slot->host.ios.chip_select; 1437 break; 1438 case MMCBR_IVAR_CLOCK: 1439 *(int *)result = slot->host.ios.clock; 1440 break; 1441 case MMCBR_IVAR_F_MIN: 1442 *(int *)result = slot->host.f_min; 1443 break; 1444 case MMCBR_IVAR_F_MAX: 1445 *(int *)result = slot->host.f_max; 1446 break; 1447 case MMCBR_IVAR_HOST_OCR: 1448 *(int *)result = slot->host.host_ocr; 1449 break; 1450 case MMCBR_IVAR_MODE: 1451 *(int *)result = slot->host.mode; 1452 break; 1453 case MMCBR_IVAR_OCR: 1454 *(int *)result = slot->host.ocr; 1455 break; 1456 case MMCBR_IVAR_POWER_MODE: 1457 *(int *)result = slot->host.ios.power_mode; 1458 break; 1459 case MMCBR_IVAR_VDD: 1460 *(int *)result = slot->host.ios.vdd; 1461 break; 1462 case MMCBR_IVAR_CAPS: 1463 *(int *)result = slot->host.caps; 1464 break; 1465 case MMCBR_IVAR_TIMING: 1466 *(int *)result = slot->host.ios.timing; 1467 break; 1468 case MMCBR_IVAR_MAX_DATA: 1469 *(int *)result = 65535; 1470 break; 1471 } 1472 return (0); 1473 } 1474 1475 static int 1476 sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1477 { 1478 struct sdhci_slot *slot = device_get_ivars(child); 1479 1480 switch (which) { 1481 default: 1482 return (EINVAL); 1483 case MMCBR_IVAR_BUS_MODE: 1484 slot->host.ios.bus_mode = value; 1485 break; 1486 case MMCBR_IVAR_BUS_WIDTH: 1487 slot->host.ios.bus_width = value; 1488 break; 1489 case MMCBR_IVAR_CHIP_SELECT: 1490 slot->host.ios.chip_select = value; 1491 break; 1492 case MMCBR_IVAR_CLOCK: 1493 if (value > 0) { 1494 uint32_t clock = slot->max_clk; 1495 int i; 1496 1497 for (i = 0; i < 8; i++) { 1498 if (clock <= value) 1499 break; 1500 clock >>= 1; 1501 } 1502 slot->host.ios.clock = clock; 1503 } else 1504 slot->host.ios.clock = 0; 1505 break; 1506 case MMCBR_IVAR_MODE: 1507 slot->host.mode = value; 1508 break; 1509 case MMCBR_IVAR_OCR: 1510 slot->host.ocr = value; 1511 break; 1512 case MMCBR_IVAR_POWER_MODE: 1513 slot->host.ios.power_mode = value; 1514 break; 1515 case MMCBR_IVAR_VDD: 1516 slot->host.ios.vdd = value; 1517 break; 1518 case MMCBR_IVAR_TIMING: 1519 slot->host.ios.timing = value; 1520 break; 1521 case MMCBR_IVAR_CAPS: 1522 case MMCBR_IVAR_HOST_OCR: 1523 case MMCBR_IVAR_F_MIN: 1524 case MMCBR_IVAR_F_MAX: 1525 case MMCBR_IVAR_MAX_DATA: 1526 return (EINVAL); 1527 } 1528 return (0); 1529 } 1530 1531 static device_method_t sdhci_methods[] = { 1532 /* device_if */ 1533 DEVMETHOD(device_probe, sdhci_probe), 1534 DEVMETHOD(device_attach, sdhci_attach), 1535 DEVMETHOD(device_detach, sdhci_detach), 1536 DEVMETHOD(device_suspend, sdhci_suspend), 1537 DEVMETHOD(device_resume, sdhci_resume), 1538 1539 /* Bus interface */ 1540 DEVMETHOD(bus_read_ivar, sdhci_read_ivar), 1541 DEVMETHOD(bus_write_ivar, sdhci_write_ivar), 1542 1543 /* mmcbr_if */ 1544 DEVMETHOD(mmcbr_update_ios, sdhci_update_ios), 1545 DEVMETHOD(mmcbr_request, sdhci_request), 1546 DEVMETHOD(mmcbr_get_ro, sdhci_get_ro), 1547 DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host), 1548 DEVMETHOD(mmcbr_release_host, sdhci_release_host), 1549 1550 {0, 0}, 1551 }; 1552 1553 static driver_t sdhci_driver = { 1554 "sdhci", 1555 sdhci_methods, 1556 sizeof(struct sdhci_softc), 1557 }; 1558 static devclass_t sdhci_devclass; 1559 1560 1561 DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0); 1562