1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/module.h> 36 #include <sys/mutex.h> 37 #include <sys/resource.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <machine/stdarg.h> 45 46 #include <dev/mmc/bridge.h> 47 #include <dev/mmc/mmcreg.h> 48 #include <dev/mmc/mmcbrvar.h> 49 50 #include "mmcbr_if.h" 51 #include "sdhci.h" 52 #include "sdhci_if.h" 53 54 struct sdhci_softc; 55 56 struct sdhci_softc { 57 device_t dev; /* Controller device */ 58 struct resource *irq_res; /* IRQ resource */ 59 int irq_rid; 60 void *intrhand; /* Interrupt handle */ 61 62 int num_slots; /* Number of slots on this controller */ 63 struct sdhci_slot slots[6]; 64 }; 65 66 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 67 68 int sdhci_debug = 0; 69 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 70 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 71 72 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 73 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 74 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 75 #define RD_MULTI_4(slot, off, ptr, count) \ 76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 77 78 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 79 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 80 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 81 #define WR_MULTI_4(slot, off, ptr, count) \ 82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 83 84 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 85 static void sdhci_start(struct sdhci_slot *slot); 86 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 87 88 static void sdhci_card_task(void *, int); 89 90 /* helper routines */ 91 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93 #define SDHCI_LOCK_INIT(_slot) \ 94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98 99 static void 100 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 101 { 102 if (error != 0) { 103 printf("getaddr: error %d\n", error); 104 return; 105 } 106 *(bus_addr_t *)arg = segs[0].ds_addr; 107 } 108 109 static int 110 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 111 { 112 va_list ap; 113 int retval; 114 115 retval = printf("%s-slot%d: ", 116 device_get_nameunit(slot->bus), slot->num); 117 118 va_start(ap, fmt); 119 retval += vprintf(fmt, ap); 120 va_end(ap); 121 return (retval); 122 } 123 124 static void 125 sdhci_dumpregs(struct sdhci_slot *slot) 126 { 127 slot_printf(slot, 128 "============== REGISTER DUMP ==============\n"); 129 130 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 131 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 132 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 133 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 134 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 135 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 136 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 137 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 138 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 139 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 140 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 141 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 142 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 143 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 144 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 145 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 146 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 147 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 148 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 149 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 150 151 slot_printf(slot, 152 "===========================================\n"); 153 } 154 155 static void 156 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 157 { 158 int timeout; 159 uint8_t res; 160 161 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 162 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 163 SDHCI_CARD_PRESENT)) 164 return; 165 } 166 167 /* Some controllers need this kick or reset won't work. */ 168 if ((mask & SDHCI_RESET_ALL) == 0 && 169 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 170 uint32_t clock; 171 172 /* This is to force an update */ 173 clock = slot->clock; 174 slot->clock = 0; 175 sdhci_set_clock(slot, clock); 176 } 177 178 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 179 180 if (mask & SDHCI_RESET_ALL) { 181 slot->clock = 0; 182 slot->power = 0; 183 } 184 185 /* Wait max 100 ms */ 186 timeout = 100; 187 /* Controller clears the bits when it's done */ 188 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 189 if (timeout == 0) { 190 slot_printf(slot, 191 "Reset 0x%x never completed - 0x%x.\n", 192 (int)mask, (int)res); 193 sdhci_dumpregs(slot); 194 return; 195 } 196 timeout--; 197 DELAY(1000); 198 } 199 } 200 201 static void 202 sdhci_init(struct sdhci_slot *slot) 203 { 204 205 sdhci_reset(slot, SDHCI_RESET_ALL); 206 207 /* Enable interrupts. */ 208 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 209 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 210 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 211 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 212 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 213 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 214 SDHCI_INT_ACMD12ERR; 215 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 216 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 217 } 218 219 static void 220 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 221 { 222 uint32_t res; 223 uint16_t clk; 224 uint16_t div; 225 int timeout; 226 227 if (clock == slot->clock) 228 return; 229 slot->clock = clock; 230 231 /* Turn off the clock. */ 232 WR2(slot, SDHCI_CLOCK_CONTROL, 0); 233 /* If no clock requested - left it so. */ 234 if (clock == 0) 235 return; 236 if (slot->version < SDHCI_SPEC_300) { 237 /* Looking for highest freq <= clock. */ 238 res = slot->max_clk; 239 for (div = 1; div < 256; div <<= 1) { 240 if (res <= clock) 241 break; 242 res >>= 1; 243 } 244 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 245 div >>= 1; 246 } 247 else { 248 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 249 if (clock > slot->max_clk) 250 div = 2; 251 else { 252 for (div = 2; div < 1023*2; div += 2) { 253 if ((slot->max_clk / div) <= clock) 254 break; 255 } 256 } 257 div >>= 1; 258 } 259 260 if (bootverbose || sdhci_debug) 261 slot_printf(slot, "Divider %d for freq %d (max %d)\n", 262 div, clock, slot->max_clk); 263 264 /* Now we have got divider, set it. */ 265 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 266 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 267 << SDHCI_DIVIDER_HI_SHIFT; 268 269 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 270 /* Enable clock. */ 271 clk |= SDHCI_CLOCK_INT_EN; 272 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 273 /* Wait up to 10 ms until it stabilize. */ 274 timeout = 10; 275 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 276 & SDHCI_CLOCK_INT_STABLE)) { 277 if (timeout == 0) { 278 slot_printf(slot, 279 "Internal clock never stabilised.\n"); 280 sdhci_dumpregs(slot); 281 return; 282 } 283 timeout--; 284 DELAY(1000); 285 } 286 /* Pass clock signal to the bus. */ 287 clk |= SDHCI_CLOCK_CARD_EN; 288 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 289 } 290 291 static void 292 sdhci_set_power(struct sdhci_slot *slot, u_char power) 293 { 294 uint8_t pwr; 295 296 if (slot->power == power) 297 return; 298 299 slot->power = power; 300 301 /* Turn off the power. */ 302 pwr = 0; 303 WR1(slot, SDHCI_POWER_CONTROL, pwr); 304 /* If power down requested - left it so. */ 305 if (power == 0) 306 return; 307 /* Set voltage. */ 308 switch (1 << power) { 309 case MMC_OCR_LOW_VOLTAGE: 310 pwr |= SDHCI_POWER_180; 311 break; 312 case MMC_OCR_290_300: 313 case MMC_OCR_300_310: 314 pwr |= SDHCI_POWER_300; 315 break; 316 case MMC_OCR_320_330: 317 case MMC_OCR_330_340: 318 pwr |= SDHCI_POWER_330; 319 break; 320 } 321 WR1(slot, SDHCI_POWER_CONTROL, pwr); 322 /* Turn on the power. */ 323 pwr |= SDHCI_POWER_ON; 324 WR1(slot, SDHCI_POWER_CONTROL, pwr); 325 } 326 327 static void 328 sdhci_read_block_pio(struct sdhci_slot *slot) 329 { 330 uint32_t data; 331 char *buffer; 332 size_t left; 333 334 buffer = slot->curcmd->data->data; 335 buffer += slot->offset; 336 /* Transfer one block at a time. */ 337 left = min(512, slot->curcmd->data->len - slot->offset); 338 slot->offset += left; 339 340 /* If we are too fast, broken controllers return zeroes. */ 341 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 342 DELAY(10); 343 /* Handle unalligned and alligned buffer cases. */ 344 if ((intptr_t)buffer & 3) { 345 while (left > 3) { 346 data = RD4(slot, SDHCI_BUFFER); 347 buffer[0] = data; 348 buffer[1] = (data >> 8); 349 buffer[2] = (data >> 16); 350 buffer[3] = (data >> 24); 351 buffer += 4; 352 left -= 4; 353 } 354 } else { 355 RD_MULTI_4(slot, SDHCI_BUFFER, 356 (uint32_t *)buffer, left >> 2); 357 left &= 3; 358 } 359 /* Handle uneven size case. */ 360 if (left > 0) { 361 data = RD4(slot, SDHCI_BUFFER); 362 while (left > 0) { 363 *(buffer++) = data; 364 data >>= 8; 365 left--; 366 } 367 } 368 } 369 370 static void 371 sdhci_write_block_pio(struct sdhci_slot *slot) 372 { 373 uint32_t data = 0; 374 char *buffer; 375 size_t left; 376 377 buffer = slot->curcmd->data->data; 378 buffer += slot->offset; 379 /* Transfer one block at a time. */ 380 left = min(512, slot->curcmd->data->len - slot->offset); 381 slot->offset += left; 382 383 /* Handle unalligned and alligned buffer cases. */ 384 if ((intptr_t)buffer & 3) { 385 while (left > 3) { 386 data = buffer[0] + 387 (buffer[1] << 8) + 388 (buffer[2] << 16) + 389 (buffer[3] << 24); 390 left -= 4; 391 buffer += 4; 392 WR4(slot, SDHCI_BUFFER, data); 393 } 394 } else { 395 WR_MULTI_4(slot, SDHCI_BUFFER, 396 (uint32_t *)buffer, left >> 2); 397 left &= 3; 398 } 399 /* Handle uneven size case. */ 400 if (left > 0) { 401 while (left > 0) { 402 data <<= 8; 403 data += *(buffer++); 404 left--; 405 } 406 WR4(slot, SDHCI_BUFFER, data); 407 } 408 } 409 410 static void 411 sdhci_transfer_pio(struct sdhci_slot *slot) 412 { 413 414 /* Read as many blocks as possible. */ 415 if (slot->curcmd->data->flags & MMC_DATA_READ) { 416 while (RD4(slot, SDHCI_PRESENT_STATE) & 417 SDHCI_DATA_AVAILABLE) { 418 sdhci_read_block_pio(slot); 419 if (slot->offset >= slot->curcmd->data->len) 420 break; 421 } 422 } else { 423 while (RD4(slot, SDHCI_PRESENT_STATE) & 424 SDHCI_SPACE_AVAILABLE) { 425 sdhci_write_block_pio(slot); 426 if (slot->offset >= slot->curcmd->data->len) 427 break; 428 } 429 } 430 } 431 432 static void 433 sdhci_card_delay(void *arg) 434 { 435 struct sdhci_slot *slot = arg; 436 437 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 438 } 439 440 static void 441 sdhci_card_task(void *arg, int pending) 442 { 443 struct sdhci_slot *slot = arg; 444 445 SDHCI_LOCK(slot); 446 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 447 if (slot->dev == NULL) { 448 /* If card is present - attach mmc bus. */ 449 slot->dev = device_add_child(slot->bus, "mmc", -1); 450 device_set_ivars(slot->dev, slot); 451 SDHCI_UNLOCK(slot); 452 device_probe_and_attach(slot->dev); 453 } else 454 SDHCI_UNLOCK(slot); 455 } else { 456 if (slot->dev != NULL) { 457 /* If no card present - detach mmc bus. */ 458 device_t d = slot->dev; 459 slot->dev = NULL; 460 SDHCI_UNLOCK(slot); 461 device_delete_child(slot->bus, d); 462 } else 463 SDHCI_UNLOCK(slot); 464 } 465 } 466 467 int 468 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 469 { 470 uint32_t caps; 471 int err; 472 473 SDHCI_LOCK_INIT(slot); 474 slot->num = num; 475 slot->bus = dev; 476 477 /* Allocate DMA tag. */ 478 err = bus_dma_tag_create(bus_get_dma_tag(dev), 479 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 480 BUS_SPACE_MAXADDR, NULL, NULL, 481 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 482 BUS_DMA_ALLOCNOW, NULL, NULL, 483 &slot->dmatag); 484 if (err != 0) { 485 device_printf(dev, "Can't create DMA tag\n"); 486 SDHCI_LOCK_DESTROY(slot); 487 return (err); 488 } 489 /* Allocate DMA memory. */ 490 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 491 BUS_DMA_NOWAIT, &slot->dmamap); 492 if (err != 0) { 493 device_printf(dev, "Can't alloc DMA memory\n"); 494 SDHCI_LOCK_DESTROY(slot); 495 return (err); 496 } 497 /* Map the memory. */ 498 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 499 (void *)slot->dmamem, DMA_BLOCK_SIZE, 500 sdhci_getaddr, &slot->paddr, 0); 501 if (err != 0 || slot->paddr == 0) { 502 device_printf(dev, "Can't load DMA memory\n"); 503 SDHCI_LOCK_DESTROY(slot); 504 if(err) 505 return (err); 506 else 507 return (EFAULT); 508 } 509 510 /* Initialize slot. */ 511 sdhci_init(slot); 512 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 513 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 514 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 515 caps = slot->caps; 516 else 517 caps = RD4(slot, SDHCI_CAPABILITIES); 518 /* Calculate base clock frequency. */ 519 slot->max_clk = 520 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 521 if (slot->max_clk == 0) { 522 slot->max_clk = 50; 523 device_printf(dev, "Hardware doesn't specify base clock " 524 "frequency.\n"); 525 } 526 slot->max_clk *= 1000000; 527 /* Calculate timeout clock frequency. */ 528 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 529 slot->timeout_clk = slot->max_clk / 1000; 530 } else { 531 slot->timeout_clk = 532 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 533 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 534 slot->timeout_clk *= 1000; 535 } 536 537 if (slot->timeout_clk == 0) { 538 device_printf(dev, "Hardware doesn't specify timeout clock " 539 "frequency.\n"); 540 } 541 542 slot->host.f_min = slot->max_clk / 256; 543 slot->host.f_max = slot->max_clk; 544 slot->host.host_ocr = 0; 545 if (caps & SDHCI_CAN_VDD_330) 546 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 547 if (caps & SDHCI_CAN_VDD_300) 548 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 549 if (caps & SDHCI_CAN_VDD_180) 550 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 551 if (slot->host.host_ocr == 0) { 552 device_printf(dev, "Hardware doesn't report any " 553 "support voltages.\n"); 554 } 555 slot->host.caps = MMC_CAP_4_BIT_DATA; 556 if (caps & SDHCI_CAN_DO_HISPD) 557 slot->host.caps |= MMC_CAP_HSPEED; 558 /* Decide if we have usable DMA. */ 559 if (caps & SDHCI_CAN_DO_DMA) 560 slot->opt |= SDHCI_HAVE_DMA; 561 562 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 563 slot->opt &= ~SDHCI_HAVE_DMA; 564 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 565 slot->opt |= SDHCI_HAVE_DMA; 566 567 if (bootverbose || sdhci_debug) { 568 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 569 slot->max_clk / 1000000, 570 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 571 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 572 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 573 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 574 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 575 sdhci_dumpregs(slot); 576 } 577 578 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 579 callout_init(&slot->card_callout, 1); 580 return (0); 581 } 582 583 void 584 sdhci_start_slot(struct sdhci_slot *slot) 585 { 586 sdhci_card_task(slot, 0); 587 } 588 589 int 590 sdhci_cleanup_slot(struct sdhci_slot *slot) 591 { 592 device_t d; 593 594 callout_drain(&slot->card_callout); 595 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 596 597 SDHCI_LOCK(slot); 598 d = slot->dev; 599 slot->dev = NULL; 600 SDHCI_UNLOCK(slot); 601 if (d != NULL) 602 device_delete_child(slot->bus, d); 603 604 SDHCI_LOCK(slot); 605 sdhci_reset(slot, SDHCI_RESET_ALL); 606 SDHCI_UNLOCK(slot); 607 bus_dmamap_unload(slot->dmatag, slot->dmamap); 608 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 609 bus_dma_tag_destroy(slot->dmatag); 610 611 SDHCI_LOCK_DESTROY(slot); 612 613 return (0); 614 } 615 616 int 617 sdhci_generic_suspend(struct sdhci_slot *slot) 618 { 619 sdhci_reset(slot, SDHCI_RESET_ALL); 620 621 return (0); 622 } 623 624 int 625 sdhci_generic_resume(struct sdhci_slot *slot) 626 { 627 sdhci_init(slot); 628 629 return (0); 630 } 631 632 int 633 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 634 { 635 struct sdhci_slot *slot = device_get_ivars(reqdev); 636 struct mmc_ios *ios = &slot->host.ios; 637 638 SDHCI_LOCK(slot); 639 /* Do full reset on bus power down to clear from any state. */ 640 if (ios->power_mode == power_off) { 641 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 642 sdhci_init(slot); 643 } 644 /* Configure the bus. */ 645 sdhci_set_clock(slot, ios->clock); 646 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 647 if (ios->bus_width == bus_width_4) 648 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 649 else 650 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 651 if (ios->timing == bus_timing_hs) 652 slot->hostctrl |= SDHCI_CTRL_HISPD; 653 else 654 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 655 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 656 /* Some controllers like reset after bus changes. */ 657 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 658 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 659 660 SDHCI_UNLOCK(slot); 661 return (0); 662 } 663 664 static void 665 sdhci_set_transfer_mode(struct sdhci_slot *slot, 666 struct mmc_data *data) 667 { 668 uint16_t mode; 669 670 if (data == NULL) 671 return; 672 673 mode = SDHCI_TRNS_BLK_CNT_EN; 674 if (data->len > 512) 675 mode |= SDHCI_TRNS_MULTI; 676 if (data->flags & MMC_DATA_READ) 677 mode |= SDHCI_TRNS_READ; 678 if (slot->req->stop) 679 mode |= SDHCI_TRNS_ACMD12; 680 if (slot->flags & SDHCI_USE_DMA) 681 mode |= SDHCI_TRNS_DMA; 682 683 WR2(slot, SDHCI_TRANSFER_MODE, mode); 684 } 685 686 static void 687 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 688 { 689 struct mmc_request *req = slot->req; 690 int flags, timeout; 691 uint32_t mask, state; 692 693 slot->curcmd = cmd; 694 slot->cmd_done = 0; 695 696 cmd->error = MMC_ERR_NONE; 697 698 /* This flags combination is not supported by controller. */ 699 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 700 slot_printf(slot, "Unsupported response type!\n"); 701 cmd->error = MMC_ERR_FAILED; 702 slot->req = NULL; 703 slot->curcmd = NULL; 704 req->done(req); 705 return; 706 } 707 708 /* Read controller present state. */ 709 state = RD4(slot, SDHCI_PRESENT_STATE); 710 /* Do not issue command if there is no card, clock or power. 711 * Controller will not detect timeout without clock active. */ 712 if ((state & SDHCI_CARD_PRESENT) == 0 || 713 slot->power == 0 || 714 slot->clock == 0) { 715 cmd->error = MMC_ERR_FAILED; 716 slot->req = NULL; 717 slot->curcmd = NULL; 718 req->done(req); 719 return; 720 } 721 /* Always wait for free CMD bus. */ 722 mask = SDHCI_CMD_INHIBIT; 723 /* Wait for free DAT if we have data or busy signal. */ 724 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 725 mask |= SDHCI_DAT_INHIBIT; 726 /* We shouldn't wait for DAT for stop commands. */ 727 if (cmd == slot->req->stop) 728 mask &= ~SDHCI_DAT_INHIBIT; 729 /* Wait for bus no more then 10 ms. */ 730 timeout = 10; 731 while (state & mask) { 732 if (timeout == 0) { 733 slot_printf(slot, "Controller never released " 734 "inhibit bit(s).\n"); 735 sdhci_dumpregs(slot); 736 cmd->error = MMC_ERR_FAILED; 737 slot->req = NULL; 738 slot->curcmd = NULL; 739 req->done(req); 740 return; 741 } 742 timeout--; 743 DELAY(1000); 744 state = RD4(slot, SDHCI_PRESENT_STATE); 745 } 746 747 /* Prepare command flags. */ 748 if (!(cmd->flags & MMC_RSP_PRESENT)) 749 flags = SDHCI_CMD_RESP_NONE; 750 else if (cmd->flags & MMC_RSP_136) 751 flags = SDHCI_CMD_RESP_LONG; 752 else if (cmd->flags & MMC_RSP_BUSY) 753 flags = SDHCI_CMD_RESP_SHORT_BUSY; 754 else 755 flags = SDHCI_CMD_RESP_SHORT; 756 if (cmd->flags & MMC_RSP_CRC) 757 flags |= SDHCI_CMD_CRC; 758 if (cmd->flags & MMC_RSP_OPCODE) 759 flags |= SDHCI_CMD_INDEX; 760 if (cmd->data) 761 flags |= SDHCI_CMD_DATA; 762 if (cmd->opcode == MMC_STOP_TRANSMISSION) 763 flags |= SDHCI_CMD_TYPE_ABORT; 764 /* Prepare data. */ 765 sdhci_start_data(slot, cmd->data); 766 /* 767 * Interrupt aggregation: To reduce total number of interrupts 768 * group response interrupt with data interrupt when possible. 769 * If there going to be data interrupt, mask response one. 770 */ 771 if (slot->data_done == 0) { 772 WR4(slot, SDHCI_SIGNAL_ENABLE, 773 slot->intmask &= ~SDHCI_INT_RESPONSE); 774 } 775 /* Set command argument. */ 776 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 777 /* Set data transfer mode. */ 778 sdhci_set_transfer_mode(slot, cmd->data); 779 /* Start command. */ 780 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 781 } 782 783 static void 784 sdhci_finish_command(struct sdhci_slot *slot) 785 { 786 int i; 787 788 slot->cmd_done = 1; 789 /* Interrupt aggregation: Restore command interrupt. 790 * Main restore point for the case when command interrupt 791 * happened first. */ 792 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 793 /* In case of error - reset host and return. */ 794 if (slot->curcmd->error) { 795 sdhci_reset(slot, SDHCI_RESET_CMD); 796 sdhci_reset(slot, SDHCI_RESET_DATA); 797 sdhci_start(slot); 798 return; 799 } 800 /* If command has response - fetch it. */ 801 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 802 if (slot->curcmd->flags & MMC_RSP_136) { 803 /* CRC is stripped so we need one byte shift. */ 804 uint8_t extra = 0; 805 for (i = 0; i < 4; i++) { 806 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 807 slot->curcmd->resp[3 - i] = (val << 8) + extra; 808 extra = val >> 24; 809 } 810 } else 811 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 812 } 813 /* If data ready - finish. */ 814 if (slot->data_done) 815 sdhci_start(slot); 816 } 817 818 static void 819 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 820 { 821 uint32_t target_timeout, current_timeout; 822 uint8_t div; 823 824 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 825 slot->data_done = 1; 826 return; 827 } 828 829 slot->data_done = 0; 830 831 /* Calculate and set data timeout.*/ 832 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 833 target_timeout = 1000000; 834 div = 0; 835 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 836 while (current_timeout < target_timeout) { 837 div++; 838 current_timeout <<= 1; 839 if (div >= 0xF) 840 break; 841 } 842 /* Compensate for an off-by-one error in the CaFe chip.*/ 843 if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 844 div++; 845 if (div >= 0xF) { 846 slot_printf(slot, "Timeout too large!\n"); 847 div = 0xE; 848 } 849 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 850 div = 0xE; 851 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 852 853 if (data == NULL) 854 return; 855 856 /* Use DMA if possible. */ 857 if ((slot->opt & SDHCI_HAVE_DMA)) 858 slot->flags |= SDHCI_USE_DMA; 859 /* If data is small, broken DMA may return zeroes instead of data, */ 860 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 861 (data->len <= 512)) 862 slot->flags &= ~SDHCI_USE_DMA; 863 /* Some controllers require even block sizes. */ 864 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 865 ((data->len) & 0x3)) 866 slot->flags &= ~SDHCI_USE_DMA; 867 /* Load DMA buffer. */ 868 if (slot->flags & SDHCI_USE_DMA) { 869 if (data->flags & MMC_DATA_READ) 870 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 871 else { 872 memcpy(slot->dmamem, data->data, 873 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 874 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 875 } 876 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 877 /* Interrupt aggregation: Mask border interrupt 878 * for the last page and unmask else. */ 879 if (data->len == DMA_BLOCK_SIZE) 880 slot->intmask &= ~SDHCI_INT_DMA_END; 881 else 882 slot->intmask |= SDHCI_INT_DMA_END; 883 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 884 } 885 /* Current data offset for both PIO and DMA. */ 886 slot->offset = 0; 887 /* Set block size and request IRQ on 4K border. */ 888 WR2(slot, SDHCI_BLOCK_SIZE, 889 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 890 /* Set block count. */ 891 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 892 } 893 894 static void 895 sdhci_finish_data(struct sdhci_slot *slot) 896 { 897 struct mmc_data *data = slot->curcmd->data; 898 899 slot->data_done = 1; 900 /* Interrupt aggregation: Restore command interrupt. 901 * Auxillary restore point for the case when data interrupt 902 * happened first. */ 903 if (!slot->cmd_done) { 904 WR4(slot, SDHCI_SIGNAL_ENABLE, 905 slot->intmask |= SDHCI_INT_RESPONSE); 906 } 907 /* Unload rest of data from DMA buffer. */ 908 if (slot->flags & SDHCI_USE_DMA) { 909 if (data->flags & MMC_DATA_READ) { 910 size_t left = data->len - slot->offset; 911 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 912 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 913 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 914 } else 915 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 916 } 917 /* If there was error - reset the host. */ 918 if (slot->curcmd->error) { 919 sdhci_reset(slot, SDHCI_RESET_CMD); 920 sdhci_reset(slot, SDHCI_RESET_DATA); 921 sdhci_start(slot); 922 return; 923 } 924 /* If we already have command response - finish. */ 925 if (slot->cmd_done) 926 sdhci_start(slot); 927 } 928 929 static void 930 sdhci_start(struct sdhci_slot *slot) 931 { 932 struct mmc_request *req; 933 934 req = slot->req; 935 if (req == NULL) 936 return; 937 938 if (!(slot->flags & CMD_STARTED)) { 939 slot->flags |= CMD_STARTED; 940 sdhci_start_command(slot, req->cmd); 941 return; 942 } 943 /* We don't need this until using Auto-CMD12 feature 944 if (!(slot->flags & STOP_STARTED) && req->stop) { 945 slot->flags |= STOP_STARTED; 946 sdhci_start_command(slot, req->stop); 947 return; 948 } 949 */ 950 if (sdhci_debug > 1) 951 slot_printf(slot, "result: %d\n", req->cmd->error); 952 if (!req->cmd->error && 953 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 954 sdhci_reset(slot, SDHCI_RESET_CMD); 955 sdhci_reset(slot, SDHCI_RESET_DATA); 956 } 957 958 /* We must be done -- bad idea to do this while locked? */ 959 slot->req = NULL; 960 slot->curcmd = NULL; 961 req->done(req); 962 } 963 964 int 965 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 966 { 967 struct sdhci_slot *slot = device_get_ivars(reqdev); 968 969 SDHCI_LOCK(slot); 970 if (slot->req != NULL) { 971 SDHCI_UNLOCK(slot); 972 return (EBUSY); 973 } 974 if (sdhci_debug > 1) { 975 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 976 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 977 (req->cmd->data)?(u_int)req->cmd->data->len:0, 978 (req->cmd->data)?req->cmd->data->flags:0); 979 } 980 slot->req = req; 981 slot->flags = 0; 982 sdhci_start(slot); 983 SDHCI_UNLOCK(slot); 984 if (dumping) { 985 while (slot->req != NULL) { 986 sdhci_generic_intr(slot); 987 DELAY(10); 988 } 989 } 990 return (0); 991 } 992 993 int 994 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 995 { 996 struct sdhci_slot *slot = device_get_ivars(reqdev); 997 uint32_t val; 998 999 SDHCI_LOCK(slot); 1000 val = RD4(slot, SDHCI_PRESENT_STATE); 1001 SDHCI_UNLOCK(slot); 1002 return (!(val & SDHCI_WRITE_PROTECT)); 1003 } 1004 1005 int 1006 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1007 { 1008 struct sdhci_slot *slot = device_get_ivars(reqdev); 1009 int err = 0; 1010 1011 SDHCI_LOCK(slot); 1012 while (slot->bus_busy) 1013 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1014 slot->bus_busy++; 1015 /* Activate led. */ 1016 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1017 SDHCI_UNLOCK(slot); 1018 return (err); 1019 } 1020 1021 int 1022 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1023 { 1024 struct sdhci_slot *slot = device_get_ivars(reqdev); 1025 1026 SDHCI_LOCK(slot); 1027 /* Deactivate led. */ 1028 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1029 slot->bus_busy--; 1030 SDHCI_UNLOCK(slot); 1031 wakeup(slot); 1032 return (0); 1033 } 1034 1035 static void 1036 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1037 { 1038 1039 if (!slot->curcmd) { 1040 slot_printf(slot, "Got command interrupt 0x%08x, but " 1041 "there is no active command.\n", intmask); 1042 sdhci_dumpregs(slot); 1043 return; 1044 } 1045 if (intmask & SDHCI_INT_TIMEOUT) 1046 slot->curcmd->error = MMC_ERR_TIMEOUT; 1047 else if (intmask & SDHCI_INT_CRC) 1048 slot->curcmd->error = MMC_ERR_BADCRC; 1049 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1050 slot->curcmd->error = MMC_ERR_FIFO; 1051 1052 sdhci_finish_command(slot); 1053 } 1054 1055 static void 1056 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1057 { 1058 1059 if (!slot->curcmd) { 1060 slot_printf(slot, "Got data interrupt 0x%08x, but " 1061 "there is no active command.\n", intmask); 1062 sdhci_dumpregs(slot); 1063 return; 1064 } 1065 if (slot->curcmd->data == NULL && 1066 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1067 slot_printf(slot, "Got data interrupt 0x%08x, but " 1068 "there is no active data operation.\n", 1069 intmask); 1070 sdhci_dumpregs(slot); 1071 return; 1072 } 1073 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1074 slot->curcmd->error = MMC_ERR_TIMEOUT; 1075 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1076 slot->curcmd->error = MMC_ERR_BADCRC; 1077 if (slot->curcmd->data == NULL && 1078 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1079 SDHCI_INT_DMA_END))) { 1080 slot_printf(slot, "Got data interrupt 0x%08x, but " 1081 "there is busy-only command.\n", intmask); 1082 sdhci_dumpregs(slot); 1083 slot->curcmd->error = MMC_ERR_INVALID; 1084 } 1085 if (slot->curcmd->error) { 1086 /* No need to continue after any error. */ 1087 sdhci_finish_data(slot); 1088 return; 1089 } 1090 1091 /* Handle PIO interrupt. */ 1092 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1093 sdhci_transfer_pio(slot); 1094 /* Handle DMA border. */ 1095 if (intmask & SDHCI_INT_DMA_END) { 1096 struct mmc_data *data = slot->curcmd->data; 1097 size_t left; 1098 1099 /* Unload DMA buffer... */ 1100 left = data->len - slot->offset; 1101 if (data->flags & MMC_DATA_READ) { 1102 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1103 BUS_DMASYNC_POSTREAD); 1104 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1105 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1106 } else { 1107 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1108 BUS_DMASYNC_POSTWRITE); 1109 } 1110 /* ... and reload it again. */ 1111 slot->offset += DMA_BLOCK_SIZE; 1112 left = data->len - slot->offset; 1113 if (data->flags & MMC_DATA_READ) { 1114 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1115 BUS_DMASYNC_PREREAD); 1116 } else { 1117 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1118 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1119 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1120 BUS_DMASYNC_PREWRITE); 1121 } 1122 /* Interrupt aggregation: Mask border interrupt 1123 * for the last page. */ 1124 if (left == DMA_BLOCK_SIZE) { 1125 slot->intmask &= ~SDHCI_INT_DMA_END; 1126 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1127 } 1128 /* Restart DMA. */ 1129 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1130 } 1131 /* We have got all data. */ 1132 if (intmask & SDHCI_INT_DATA_END) 1133 sdhci_finish_data(slot); 1134 } 1135 1136 static void 1137 sdhci_acmd_irq(struct sdhci_slot *slot) 1138 { 1139 uint16_t err; 1140 1141 err = RD4(slot, SDHCI_ACMD12_ERR); 1142 if (!slot->curcmd) { 1143 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1144 "there is no active command.\n", err); 1145 sdhci_dumpregs(slot); 1146 return; 1147 } 1148 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1149 sdhci_reset(slot, SDHCI_RESET_CMD); 1150 } 1151 1152 void 1153 sdhci_generic_intr(struct sdhci_slot *slot) 1154 { 1155 uint32_t intmask; 1156 1157 SDHCI_LOCK(slot); 1158 /* Read slot interrupt status. */ 1159 intmask = RD4(slot, SDHCI_INT_STATUS); 1160 if (intmask == 0 || intmask == 0xffffffff) { 1161 SDHCI_UNLOCK(slot); 1162 return; 1163 } 1164 if (sdhci_debug > 2) 1165 slot_printf(slot, "Interrupt %#x\n", intmask); 1166 1167 /* Handle card presence interrupts. */ 1168 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1169 WR4(slot, SDHCI_INT_STATUS, intmask & 1170 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1171 1172 if (intmask & SDHCI_INT_CARD_REMOVE) { 1173 if (bootverbose || sdhci_debug) 1174 slot_printf(slot, "Card removed\n"); 1175 callout_stop(&slot->card_callout); 1176 taskqueue_enqueue(taskqueue_swi_giant, 1177 &slot->card_task); 1178 } 1179 if (intmask & SDHCI_INT_CARD_INSERT) { 1180 if (bootverbose || sdhci_debug) 1181 slot_printf(slot, "Card inserted\n"); 1182 callout_reset(&slot->card_callout, hz / 2, 1183 sdhci_card_delay, slot); 1184 } 1185 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1186 } 1187 /* Handle command interrupts. */ 1188 if (intmask & SDHCI_INT_CMD_MASK) { 1189 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1190 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1191 } 1192 /* Handle data interrupts. */ 1193 if (intmask & SDHCI_INT_DATA_MASK) { 1194 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1195 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1196 } 1197 /* Handle AutoCMD12 error interrupt. */ 1198 if (intmask & SDHCI_INT_ACMD12ERR) { 1199 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1200 sdhci_acmd_irq(slot); 1201 } 1202 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1203 intmask &= ~SDHCI_INT_ACMD12ERR; 1204 intmask &= ~SDHCI_INT_ERROR; 1205 /* Handle bus power interrupt. */ 1206 if (intmask & SDHCI_INT_BUS_POWER) { 1207 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1208 slot_printf(slot, 1209 "Card is consuming too much power!\n"); 1210 intmask &= ~SDHCI_INT_BUS_POWER; 1211 } 1212 /* The rest is unknown. */ 1213 if (intmask) { 1214 WR4(slot, SDHCI_INT_STATUS, intmask); 1215 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1216 intmask); 1217 sdhci_dumpregs(slot); 1218 } 1219 1220 SDHCI_UNLOCK(slot); 1221 } 1222 1223 int 1224 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1225 { 1226 struct sdhci_slot *slot = device_get_ivars(child); 1227 1228 switch (which) { 1229 default: 1230 return (EINVAL); 1231 case MMCBR_IVAR_BUS_MODE: 1232 *result = slot->host.ios.bus_mode; 1233 break; 1234 case MMCBR_IVAR_BUS_WIDTH: 1235 *result = slot->host.ios.bus_width; 1236 break; 1237 case MMCBR_IVAR_CHIP_SELECT: 1238 *result = slot->host.ios.chip_select; 1239 break; 1240 case MMCBR_IVAR_CLOCK: 1241 *result = slot->host.ios.clock; 1242 break; 1243 case MMCBR_IVAR_F_MIN: 1244 *result = slot->host.f_min; 1245 break; 1246 case MMCBR_IVAR_F_MAX: 1247 *result = slot->host.f_max; 1248 break; 1249 case MMCBR_IVAR_HOST_OCR: 1250 *result = slot->host.host_ocr; 1251 break; 1252 case MMCBR_IVAR_MODE: 1253 *result = slot->host.mode; 1254 break; 1255 case MMCBR_IVAR_OCR: 1256 *result = slot->host.ocr; 1257 break; 1258 case MMCBR_IVAR_POWER_MODE: 1259 *result = slot->host.ios.power_mode; 1260 break; 1261 case MMCBR_IVAR_VDD: 1262 *result = slot->host.ios.vdd; 1263 break; 1264 case MMCBR_IVAR_CAPS: 1265 *result = slot->host.caps; 1266 break; 1267 case MMCBR_IVAR_TIMING: 1268 *result = slot->host.ios.timing; 1269 break; 1270 case MMCBR_IVAR_MAX_DATA: 1271 *result = 65535; 1272 break; 1273 } 1274 return (0); 1275 } 1276 1277 int 1278 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1279 { 1280 struct sdhci_slot *slot = device_get_ivars(child); 1281 1282 switch (which) { 1283 default: 1284 return (EINVAL); 1285 case MMCBR_IVAR_BUS_MODE: 1286 slot->host.ios.bus_mode = value; 1287 break; 1288 case MMCBR_IVAR_BUS_WIDTH: 1289 slot->host.ios.bus_width = value; 1290 break; 1291 case MMCBR_IVAR_CHIP_SELECT: 1292 slot->host.ios.chip_select = value; 1293 break; 1294 case MMCBR_IVAR_CLOCK: 1295 if (value > 0) { 1296 uint32_t clock = slot->max_clk; 1297 int i; 1298 1299 for (i = 0; i < 8; i++) { 1300 if (clock <= value) 1301 break; 1302 clock >>= 1; 1303 } 1304 slot->host.ios.clock = clock; 1305 } else 1306 slot->host.ios.clock = 0; 1307 break; 1308 case MMCBR_IVAR_MODE: 1309 slot->host.mode = value; 1310 break; 1311 case MMCBR_IVAR_OCR: 1312 slot->host.ocr = value; 1313 break; 1314 case MMCBR_IVAR_POWER_MODE: 1315 slot->host.ios.power_mode = value; 1316 break; 1317 case MMCBR_IVAR_VDD: 1318 slot->host.ios.vdd = value; 1319 break; 1320 case MMCBR_IVAR_TIMING: 1321 slot->host.ios.timing = value; 1322 break; 1323 case MMCBR_IVAR_CAPS: 1324 case MMCBR_IVAR_HOST_OCR: 1325 case MMCBR_IVAR_F_MIN: 1326 case MMCBR_IVAR_F_MAX: 1327 case MMCBR_IVAR_MAX_DATA: 1328 return (EINVAL); 1329 } 1330 return (0); 1331 } 1332 1333 MODULE_VERSION(sdhci, 1); 1334