xref: /freebsd/sys/dev/sdhci/sdhci.c (revision 3a92d97ff0f22d21608e1c19b83104c4937523b6)
1 /*-
2  * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24  */
25 
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/callout.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
42 
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
46 
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
50 
51 #include "mmcbr_if.h"
52 #include "sdhci.h"
53 #include "sdhci_if.h"
54 
55 struct sdhci_softc;
56 
57 struct sdhci_softc {
58 	device_t	dev;		/* Controller device */
59 	struct resource *irq_res;	/* IRQ resource */
60 	int 		irq_rid;
61 	void 		*intrhand;	/* Interrupt handle */
62 
63 	int		num_slots;	/* Number of slots on this controller */
64 	struct sdhci_slot slots[6];
65 };
66 
67 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
68 
69 int	sdhci_debug = 0;
70 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
71 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
72 
73 #define RD1(slot, off)	SDHCI_READ_1((slot)->bus, (slot), (off))
74 #define RD2(slot, off)	SDHCI_READ_2((slot)->bus, (slot), (off))
75 #define RD4(slot, off)	SDHCI_READ_4((slot)->bus, (slot), (off))
76 #define RD_MULTI_4(slot, off, ptr, count)	\
77     SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
78 
79 #define WR1(slot, off, val)	SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
80 #define WR2(slot, off, val)	SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
81 #define WR4(slot, off, val)	SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
82 #define WR_MULTI_4(slot, off, ptr, count)	\
83     SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
84 
85 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
86 static void sdhci_start(struct sdhci_slot *slot);
87 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
88 
89 static void sdhci_card_task(void *, int);
90 
91 /* helper routines */
92 #define SDHCI_LOCK(_slot)		mtx_lock(&(_slot)->mtx)
93 #define	SDHCI_UNLOCK(_slot)		mtx_unlock(&(_slot)->mtx)
94 #define SDHCI_LOCK_INIT(_slot) \
95 	mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
96 #define SDHCI_LOCK_DESTROY(_slot)	mtx_destroy(&_slot->mtx);
97 #define SDHCI_ASSERT_LOCKED(_slot)	mtx_assert(&_slot->mtx, MA_OWNED);
98 #define SDHCI_ASSERT_UNLOCKED(_slot)	mtx_assert(&_slot->mtx, MA_NOTOWNED);
99 
100 #define	SDHCI_DEFAULT_MAX_FREQ	50
101 
102 #define	SDHCI_200_MAX_DIVIDER	256
103 #define	SDHCI_300_MAX_DIVIDER	2046
104 
105 static void
106 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
107 {
108 	if (error != 0) {
109 		printf("getaddr: error %d\n", error);
110 		return;
111 	}
112 	*(bus_addr_t *)arg = segs[0].ds_addr;
113 }
114 
115 static int
116 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
117 {
118 	va_list ap;
119 	int retval;
120 
121     	retval = printf("%s-slot%d: ",
122 	    device_get_nameunit(slot->bus), slot->num);
123 
124 	va_start(ap, fmt);
125 	retval += vprintf(fmt, ap);
126 	va_end(ap);
127 	return (retval);
128 }
129 
130 static void
131 sdhci_dumpregs(struct sdhci_slot *slot)
132 {
133 	slot_printf(slot,
134 	    "============== REGISTER DUMP ==============\n");
135 
136 	slot_printf(slot, "Sys addr: 0x%08x | Version:  0x%08x\n",
137 	    RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
138 	slot_printf(slot, "Blk size: 0x%08x | Blk cnt:  0x%08x\n",
139 	    RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
140 	slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
141 	    RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
142 	slot_printf(slot, "Present:  0x%08x | Host ctl: 0x%08x\n",
143 	    RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
144 	slot_printf(slot, "Power:    0x%08x | Blk gap:  0x%08x\n",
145 	    RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
146 	slot_printf(slot, "Wake-up:  0x%08x | Clock:    0x%08x\n",
147 	    RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
148 	slot_printf(slot, "Timeout:  0x%08x | Int stat: 0x%08x\n",
149 	    RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
150 	slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
151 	    RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
152 	slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
153 	    RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
154 	slot_printf(slot, "Caps:     0x%08x | Max curr: 0x%08x\n",
155 	    RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
156 
157 	slot_printf(slot,
158 	    "===========================================\n");
159 }
160 
161 static void
162 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
163 {
164 	int timeout;
165 	uint8_t res;
166 
167 	if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
168 		if (!(RD4(slot, SDHCI_PRESENT_STATE) &
169 			SDHCI_CARD_PRESENT))
170 			return;
171 	}
172 
173 	/* Some controllers need this kick or reset won't work. */
174 	if ((mask & SDHCI_RESET_ALL) == 0 &&
175 	    (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
176 		uint32_t clock;
177 
178 		/* This is to force an update */
179 		clock = slot->clock;
180 		slot->clock = 0;
181 		sdhci_set_clock(slot, clock);
182 	}
183 
184 	WR1(slot, SDHCI_SOFTWARE_RESET, mask);
185 
186 	if (mask & SDHCI_RESET_ALL) {
187 		slot->clock = 0;
188 		slot->power = 0;
189 	}
190 
191 	/* Wait max 100 ms */
192 	timeout = 100;
193 	/* Controller clears the bits when it's done */
194 	while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
195 		if (timeout == 0) {
196 			slot_printf(slot,
197 			    "Reset 0x%x never completed - 0x%x.\n",
198 			    (int)mask, (int)res);
199 			sdhci_dumpregs(slot);
200 			return;
201 		}
202 		timeout--;
203 		DELAY(1000);
204 	}
205 }
206 
207 static void
208 sdhci_init(struct sdhci_slot *slot)
209 {
210 
211 	sdhci_reset(slot, SDHCI_RESET_ALL);
212 
213 	/* Enable interrupts. */
214 	slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
215 	    SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
216 	    SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
217 	    SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
218 	    SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
219 	    SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
220 	    SDHCI_INT_ACMD12ERR;
221 	WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
222 	WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
223 }
224 
225 static void
226 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
227 {
228 	uint32_t res;
229 	uint16_t clk;
230 	uint16_t div;
231 	int timeout;
232 
233 	if (clock == slot->clock)
234 		return;
235 	slot->clock = clock;
236 
237 	/* Turn off the clock. */
238 	WR2(slot, SDHCI_CLOCK_CONTROL, 0);
239 	/* If no clock requested - left it so. */
240 	if (clock == 0)
241 		return;
242 
243 	/* Recalculate timeout clock frequency based on the new sd clock. */
244 	if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
245 		slot->timeout_clk = slot->clock / 1000;
246 
247 	if (slot->version < SDHCI_SPEC_300) {
248 		/* Looking for highest freq <= clock. */
249 		res = slot->max_clk;
250 		for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
251 			if (res <= clock)
252 				break;
253 			res >>= 1;
254 		}
255 		/* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
256 		div >>= 1;
257 	}
258 	else {
259 		/* Version 3.0 divisors are multiples of two up to 1023*2 */
260 		if (clock >= slot->max_clk)
261 			div = 0;
262 		else {
263 			for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
264 				if ((slot->max_clk / div) <= clock)
265 					break;
266 			}
267 		}
268 		div >>= 1;
269 	}
270 
271 	if (bootverbose || sdhci_debug)
272 		slot_printf(slot, "Divider %d for freq %d (max %d)\n",
273 			div, clock, slot->max_clk);
274 
275 	/* Now we have got divider, set it. */
276 	clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
277 	clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
278 		<< SDHCI_DIVIDER_HI_SHIFT;
279 
280 	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
281 	/* Enable clock. */
282 	clk |= SDHCI_CLOCK_INT_EN;
283 	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
284 	/* Wait up to 10 ms until it stabilize. */
285 	timeout = 10;
286 	while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
287 		& SDHCI_CLOCK_INT_STABLE)) {
288 		if (timeout == 0) {
289 			slot_printf(slot,
290 			    "Internal clock never stabilised.\n");
291 			sdhci_dumpregs(slot);
292 			return;
293 		}
294 		timeout--;
295 		DELAY(1000);
296 	}
297 	/* Pass clock signal to the bus. */
298 	clk |= SDHCI_CLOCK_CARD_EN;
299 	WR2(slot, SDHCI_CLOCK_CONTROL, clk);
300 }
301 
302 static void
303 sdhci_set_power(struct sdhci_slot *slot, u_char power)
304 {
305 	uint8_t pwr;
306 
307 	if (slot->power == power)
308 		return;
309 
310 	slot->power = power;
311 
312 	/* Turn off the power. */
313 	pwr = 0;
314 	WR1(slot, SDHCI_POWER_CONTROL, pwr);
315 	/* If power down requested - left it so. */
316 	if (power == 0)
317 		return;
318 	/* Set voltage. */
319 	switch (1 << power) {
320 	case MMC_OCR_LOW_VOLTAGE:
321 		pwr |= SDHCI_POWER_180;
322 		break;
323 	case MMC_OCR_290_300:
324 	case MMC_OCR_300_310:
325 		pwr |= SDHCI_POWER_300;
326 		break;
327 	case MMC_OCR_320_330:
328 	case MMC_OCR_330_340:
329 		pwr |= SDHCI_POWER_330;
330 		break;
331 	}
332 	WR1(slot, SDHCI_POWER_CONTROL, pwr);
333 	/* Turn on the power. */
334 	pwr |= SDHCI_POWER_ON;
335 	WR1(slot, SDHCI_POWER_CONTROL, pwr);
336 }
337 
338 static void
339 sdhci_read_block_pio(struct sdhci_slot *slot)
340 {
341 	uint32_t data;
342 	char *buffer;
343 	size_t left;
344 
345 	buffer = slot->curcmd->data->data;
346 	buffer += slot->offset;
347 	/* Transfer one block at a time. */
348 	left = min(512, slot->curcmd->data->len - slot->offset);
349 	slot->offset += left;
350 
351 	/* If we are too fast, broken controllers return zeroes. */
352 	if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
353 		DELAY(10);
354 	/* Handle unaligned and aligned buffer cases. */
355 	if ((intptr_t)buffer & 3) {
356 		while (left > 3) {
357 			data = RD4(slot, SDHCI_BUFFER);
358 			buffer[0] = data;
359 			buffer[1] = (data >> 8);
360 			buffer[2] = (data >> 16);
361 			buffer[3] = (data >> 24);
362 			buffer += 4;
363 			left -= 4;
364 		}
365 	} else {
366 		RD_MULTI_4(slot, SDHCI_BUFFER,
367 		    (uint32_t *)buffer, left >> 2);
368 		left &= 3;
369 	}
370 	/* Handle uneven size case. */
371 	if (left > 0) {
372 		data = RD4(slot, SDHCI_BUFFER);
373 		while (left > 0) {
374 			*(buffer++) = data;
375 			data >>= 8;
376 			left--;
377 		}
378 	}
379 }
380 
381 static void
382 sdhci_write_block_pio(struct sdhci_slot *slot)
383 {
384 	uint32_t data = 0;
385 	char *buffer;
386 	size_t left;
387 
388 	buffer = slot->curcmd->data->data;
389 	buffer += slot->offset;
390 	/* Transfer one block at a time. */
391 	left = min(512, slot->curcmd->data->len - slot->offset);
392 	slot->offset += left;
393 
394 	/* Handle unaligned and aligned buffer cases. */
395 	if ((intptr_t)buffer & 3) {
396 		while (left > 3) {
397 			data = buffer[0] +
398 			    (buffer[1] << 8) +
399 			    (buffer[2] << 16) +
400 			    (buffer[3] << 24);
401 			left -= 4;
402 			buffer += 4;
403 			WR4(slot, SDHCI_BUFFER, data);
404 		}
405 	} else {
406 		WR_MULTI_4(slot, SDHCI_BUFFER,
407 		    (uint32_t *)buffer, left >> 2);
408 		left &= 3;
409 	}
410 	/* Handle uneven size case. */
411 	if (left > 0) {
412 		while (left > 0) {
413 			data <<= 8;
414 			data += *(buffer++);
415 			left--;
416 		}
417 		WR4(slot, SDHCI_BUFFER, data);
418 	}
419 }
420 
421 static void
422 sdhci_transfer_pio(struct sdhci_slot *slot)
423 {
424 
425 	/* Read as many blocks as possible. */
426 	if (slot->curcmd->data->flags & MMC_DATA_READ) {
427 		while (RD4(slot, SDHCI_PRESENT_STATE) &
428 		    SDHCI_DATA_AVAILABLE) {
429 			sdhci_read_block_pio(slot);
430 			if (slot->offset >= slot->curcmd->data->len)
431 				break;
432 		}
433 	} else {
434 		while (RD4(slot, SDHCI_PRESENT_STATE) &
435 		    SDHCI_SPACE_AVAILABLE) {
436 			sdhci_write_block_pio(slot);
437 			if (slot->offset >= slot->curcmd->data->len)
438 				break;
439 		}
440 	}
441 }
442 
443 static void
444 sdhci_card_delay(void *arg)
445 {
446 	struct sdhci_slot *slot = arg;
447 
448 	taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
449 }
450 
451 static void
452 sdhci_card_task(void *arg, int pending)
453 {
454 	struct sdhci_slot *slot = arg;
455 
456 	SDHCI_LOCK(slot);
457 	if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
458 		if (slot->dev == NULL) {
459 			/* If card is present - attach mmc bus. */
460 			slot->dev = device_add_child(slot->bus, "mmc", -1);
461 			device_set_ivars(slot->dev, slot);
462 			SDHCI_UNLOCK(slot);
463 			device_probe_and_attach(slot->dev);
464 		} else
465 			SDHCI_UNLOCK(slot);
466 	} else {
467 		if (slot->dev != NULL) {
468 			/* If no card present - detach mmc bus. */
469 			device_t d = slot->dev;
470 			slot->dev = NULL;
471 			SDHCI_UNLOCK(slot);
472 			device_delete_child(slot->bus, d);
473 		} else
474 			SDHCI_UNLOCK(slot);
475 	}
476 }
477 
478 int
479 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
480 {
481 	uint32_t caps, freq;
482 	int err;
483 
484 	SDHCI_LOCK_INIT(slot);
485 	slot->num = num;
486 	slot->bus = dev;
487 
488 	/* Allocate DMA tag. */
489 	err = bus_dma_tag_create(bus_get_dma_tag(dev),
490 	    DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
491 	    BUS_SPACE_MAXADDR, NULL, NULL,
492 	    DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
493 	    BUS_DMA_ALLOCNOW, NULL, NULL,
494 	    &slot->dmatag);
495 	if (err != 0) {
496 		device_printf(dev, "Can't create DMA tag\n");
497 		SDHCI_LOCK_DESTROY(slot);
498 		return (err);
499 	}
500 	/* Allocate DMA memory. */
501 	err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
502 	    BUS_DMA_NOWAIT, &slot->dmamap);
503 	if (err != 0) {
504 		device_printf(dev, "Can't alloc DMA memory\n");
505 		SDHCI_LOCK_DESTROY(slot);
506 		return (err);
507 	}
508 	/* Map the memory. */
509 	err = bus_dmamap_load(slot->dmatag, slot->dmamap,
510 	    (void *)slot->dmamem, DMA_BLOCK_SIZE,
511 	    sdhci_getaddr, &slot->paddr, 0);
512 	if (err != 0 || slot->paddr == 0) {
513 		device_printf(dev, "Can't load DMA memory\n");
514 		SDHCI_LOCK_DESTROY(slot);
515 		if(err)
516 			return (err);
517 		else
518 			return (EFAULT);
519 	}
520 
521 	/* Initialize slot. */
522 	sdhci_init(slot);
523 	slot->version = (RD2(slot, SDHCI_HOST_VERSION)
524 		>> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
525 	if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
526 		caps = slot->caps;
527 	else
528 		caps = RD4(slot, SDHCI_CAPABILITIES);
529 	/* Calculate base clock frequency. */
530 	if (slot->version >= SDHCI_SPEC_300)
531 		freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
532 		    SDHCI_CLOCK_BASE_SHIFT;
533 	else
534 		freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
535 		    SDHCI_CLOCK_BASE_SHIFT;
536 	if (freq != 0)
537 		slot->max_clk = freq * 1000000;
538 	/*
539 	 * If the frequency wasn't in the capabilities and the hardware driver
540 	 * hasn't already set max_clk we're probably not going to work right
541 	 * with an assumption, so complain about it.
542 	 */
543 	if (slot->max_clk == 0) {
544 		slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
545 		device_printf(dev, "Hardware doesn't specify base clock "
546 		    "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
547 	}
548 	/* Calculate timeout clock frequency. */
549 	if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
550 		slot->timeout_clk = slot->max_clk / 1000;
551 	} else {
552 		slot->timeout_clk =
553 			(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
554 		if (caps & SDHCI_TIMEOUT_CLK_UNIT)
555 			slot->timeout_clk *= 1000;
556 	}
557 	/*
558 	 * If the frequency wasn't in the capabilities and the hardware driver
559 	 * hasn't already set timeout_clk we'll probably work okay using the
560 	 * max timeout, but still mention it.
561 	 */
562 	if (slot->timeout_clk == 0) {
563 		device_printf(dev, "Hardware doesn't specify timeout clock "
564 		    "frequency, setting BROKEN_TIMEOUT quirk.\n");
565 		slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
566 	}
567 
568 	slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
569 	slot->host.f_max = slot->max_clk;
570 	slot->host.host_ocr = 0;
571 	if (caps & SDHCI_CAN_VDD_330)
572 	    slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
573 	if (caps & SDHCI_CAN_VDD_300)
574 	    slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
575 	if (caps & SDHCI_CAN_VDD_180)
576 	    slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
577 	if (slot->host.host_ocr == 0) {
578 		device_printf(dev, "Hardware doesn't report any "
579 		    "support voltages.\n");
580 	}
581 	slot->host.caps = MMC_CAP_4_BIT_DATA;
582 	if (caps & SDHCI_CAN_DO_HISPD)
583 		slot->host.caps |= MMC_CAP_HSPEED;
584 	/* Decide if we have usable DMA. */
585 	if (caps & SDHCI_CAN_DO_DMA)
586 		slot->opt |= SDHCI_HAVE_DMA;
587 
588 	if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
589 		slot->opt &= ~SDHCI_HAVE_DMA;
590 	if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
591 		slot->opt |= SDHCI_HAVE_DMA;
592 
593 	/*
594 	 * Use platform-provided transfer backend
595 	 * with PIO as a fallback mechanism
596 	 */
597 	if (slot->opt & SDHCI_PLATFORM_TRANSFER)
598 		slot->opt &= ~SDHCI_HAVE_DMA;
599 
600 	if (bootverbose || sdhci_debug) {
601 		slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
602 		    slot->max_clk / 1000000,
603 		    (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
604 		    (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
605 		    (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
606 		    (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
607 		    (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
608 		sdhci_dumpregs(slot);
609 	}
610 
611 	TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
612 	callout_init(&slot->card_callout, 1);
613 	callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
614 	return (0);
615 }
616 
617 void
618 sdhci_start_slot(struct sdhci_slot *slot)
619 {
620 	sdhci_card_task(slot, 0);
621 }
622 
623 int
624 sdhci_cleanup_slot(struct sdhci_slot *slot)
625 {
626 	device_t d;
627 
628 	callout_drain(&slot->timeout_callout);
629 	callout_drain(&slot->card_callout);
630 	taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
631 
632 	SDHCI_LOCK(slot);
633 	d = slot->dev;
634 	slot->dev = NULL;
635 	SDHCI_UNLOCK(slot);
636 	if (d != NULL)
637 		device_delete_child(slot->bus, d);
638 
639 	SDHCI_LOCK(slot);
640 	sdhci_reset(slot, SDHCI_RESET_ALL);
641 	SDHCI_UNLOCK(slot);
642 	bus_dmamap_unload(slot->dmatag, slot->dmamap);
643 	bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
644 	bus_dma_tag_destroy(slot->dmatag);
645 
646 	SDHCI_LOCK_DESTROY(slot);
647 
648 	return (0);
649 }
650 
651 int
652 sdhci_generic_suspend(struct sdhci_slot *slot)
653 {
654 	sdhci_reset(slot, SDHCI_RESET_ALL);
655 
656 	return (0);
657 }
658 
659 int
660 sdhci_generic_resume(struct sdhci_slot *slot)
661 {
662 	sdhci_init(slot);
663 
664 	return (0);
665 }
666 
667 uint32_t
668 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
669 {
670 	if (slot->version >= SDHCI_SPEC_300)
671 		return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
672 	else
673 		return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
674 }
675 
676 int
677 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
678 {
679 	struct sdhci_slot *slot = device_get_ivars(reqdev);
680 	struct mmc_ios *ios = &slot->host.ios;
681 
682 	SDHCI_LOCK(slot);
683 	/* Do full reset on bus power down to clear from any state. */
684 	if (ios->power_mode == power_off) {
685 		WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
686 		sdhci_init(slot);
687 	}
688 	/* Configure the bus. */
689 	sdhci_set_clock(slot, ios->clock);
690 	sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
691 	if (ios->bus_width == bus_width_4)
692 		slot->hostctrl |= SDHCI_CTRL_4BITBUS;
693 	else
694 		slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
695 	if (ios->timing == bus_timing_hs)
696 		slot->hostctrl |= SDHCI_CTRL_HISPD;
697 	else
698 		slot->hostctrl &= ~SDHCI_CTRL_HISPD;
699 	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
700 	/* Some controllers like reset after bus changes. */
701 	if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
702 		sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
703 
704 	SDHCI_UNLOCK(slot);
705 	return (0);
706 }
707 
708 static void
709 sdhci_req_done(struct sdhci_slot *slot)
710 {
711 	struct mmc_request *req;
712 
713 	if (slot->req != NULL && slot->curcmd != NULL) {
714 		callout_stop(&slot->timeout_callout);
715 		req = slot->req;
716 		slot->req = NULL;
717 		slot->curcmd = NULL;
718 		req->done(req);
719 	}
720 }
721 
722 static void
723 sdhci_timeout(void *arg)
724 {
725 	struct sdhci_slot *slot = arg;
726 
727 	if (slot->curcmd != NULL) {
728 		sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
729 		slot->curcmd->error = MMC_ERR_TIMEOUT;
730 		sdhci_req_done(slot);
731 	}
732 }
733 
734 static void
735 sdhci_set_transfer_mode(struct sdhci_slot *slot,
736 	struct mmc_data *data)
737 {
738 	uint16_t mode;
739 
740 	if (data == NULL)
741 		return;
742 
743 	mode = SDHCI_TRNS_BLK_CNT_EN;
744 	if (data->len > 512)
745 		mode |= SDHCI_TRNS_MULTI;
746 	if (data->flags & MMC_DATA_READ)
747 		mode |= SDHCI_TRNS_READ;
748 	if (slot->req->stop)
749 		mode |= SDHCI_TRNS_ACMD12;
750 	if (slot->flags & SDHCI_USE_DMA)
751 		mode |= SDHCI_TRNS_DMA;
752 
753 	WR2(slot, SDHCI_TRANSFER_MODE, mode);
754 }
755 
756 static void
757 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
758 {
759 	int flags, timeout;
760 	uint32_t mask, state;
761 
762 	slot->curcmd = cmd;
763 	slot->cmd_done = 0;
764 
765 	cmd->error = MMC_ERR_NONE;
766 
767 	/* This flags combination is not supported by controller. */
768 	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
769 		slot_printf(slot, "Unsupported response type!\n");
770 		cmd->error = MMC_ERR_FAILED;
771 		sdhci_req_done(slot);
772 		return;
773 	}
774 
775 	/* Read controller present state. */
776 	state = RD4(slot, SDHCI_PRESENT_STATE);
777 	/* Do not issue command if there is no card, clock or power.
778 	 * Controller will not detect timeout without clock active. */
779 	if ((state & SDHCI_CARD_PRESENT) == 0 ||
780 	    slot->power == 0 ||
781 	    slot->clock == 0) {
782 		cmd->error = MMC_ERR_FAILED;
783 		sdhci_req_done(slot);
784 		return;
785 	}
786 	/* Always wait for free CMD bus. */
787 	mask = SDHCI_CMD_INHIBIT;
788 	/* Wait for free DAT if we have data or busy signal. */
789 	if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
790 		mask |= SDHCI_DAT_INHIBIT;
791 	/* We shouldn't wait for DAT for stop commands. */
792 	if (cmd == slot->req->stop)
793 		mask &= ~SDHCI_DAT_INHIBIT;
794 	/*
795 	 *  Wait for bus no more then 250 ms.  Typically there will be no wait
796 	 *  here at all, but when writing a crash dump we may be bypassing the
797 	 *  host platform's interrupt handler, and in some cases that handler
798 	 *  may be working around hardware quirks such as not respecting r1b
799 	 *  busy indications.  In those cases, this wait-loop serves the purpose
800 	 *  of waiting for the prior command and data transfers to be done, and
801 	 *  SD cards are allowed to take up to 250ms for write and erase ops.
802 	 *  (It's usually more like 20-30ms in the real world.)
803 	 */
804 	timeout = 250;
805 	while (state & mask) {
806 		if (timeout == 0) {
807 			slot_printf(slot, "Controller never released "
808 			    "inhibit bit(s).\n");
809 			sdhci_dumpregs(slot);
810 			cmd->error = MMC_ERR_FAILED;
811 			sdhci_req_done(slot);
812 			return;
813 		}
814 		timeout--;
815 		DELAY(1000);
816 		state = RD4(slot, SDHCI_PRESENT_STATE);
817 	}
818 
819 	/* Prepare command flags. */
820 	if (!(cmd->flags & MMC_RSP_PRESENT))
821 		flags = SDHCI_CMD_RESP_NONE;
822 	else if (cmd->flags & MMC_RSP_136)
823 		flags = SDHCI_CMD_RESP_LONG;
824 	else if (cmd->flags & MMC_RSP_BUSY)
825 		flags = SDHCI_CMD_RESP_SHORT_BUSY;
826 	else
827 		flags = SDHCI_CMD_RESP_SHORT;
828 	if (cmd->flags & MMC_RSP_CRC)
829 		flags |= SDHCI_CMD_CRC;
830 	if (cmd->flags & MMC_RSP_OPCODE)
831 		flags |= SDHCI_CMD_INDEX;
832 	if (cmd->data)
833 		flags |= SDHCI_CMD_DATA;
834 	if (cmd->opcode == MMC_STOP_TRANSMISSION)
835 		flags |= SDHCI_CMD_TYPE_ABORT;
836 	/* Prepare data. */
837 	sdhci_start_data(slot, cmd->data);
838 	/*
839 	 * Interrupt aggregation: To reduce total number of interrupts
840 	 * group response interrupt with data interrupt when possible.
841 	 * If there going to be data interrupt, mask response one.
842 	 */
843 	if (slot->data_done == 0) {
844 		WR4(slot, SDHCI_SIGNAL_ENABLE,
845 		    slot->intmask &= ~SDHCI_INT_RESPONSE);
846 	}
847 	/* Set command argument. */
848 	WR4(slot, SDHCI_ARGUMENT, cmd->arg);
849 	/* Set data transfer mode. */
850 	sdhci_set_transfer_mode(slot, cmd->data);
851 	/* Start command. */
852 	WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
853 	/* Start timeout callout. */
854 	callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot);
855 }
856 
857 static void
858 sdhci_finish_command(struct sdhci_slot *slot)
859 {
860 	int i;
861 
862 	slot->cmd_done = 1;
863 	/* Interrupt aggregation: Restore command interrupt.
864 	 * Main restore point for the case when command interrupt
865 	 * happened first. */
866 	WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
867 	/* In case of error - reset host and return. */
868 	if (slot->curcmd->error) {
869 		sdhci_reset(slot, SDHCI_RESET_CMD);
870 		sdhci_reset(slot, SDHCI_RESET_DATA);
871 		sdhci_start(slot);
872 		return;
873 	}
874 	/* If command has response - fetch it. */
875 	if (slot->curcmd->flags & MMC_RSP_PRESENT) {
876 		if (slot->curcmd->flags & MMC_RSP_136) {
877 			/* CRC is stripped so we need one byte shift. */
878 			uint8_t extra = 0;
879 			for (i = 0; i < 4; i++) {
880 				uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
881 				if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
882 					slot->curcmd->resp[3 - i] = val;
883 				else {
884 					slot->curcmd->resp[3 - i] =
885 					    (val << 8) | extra;
886 					extra = val >> 24;
887 				}
888 			}
889 		} else
890 			slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
891 	}
892 	/* If data ready - finish. */
893 	if (slot->data_done)
894 		sdhci_start(slot);
895 }
896 
897 static void
898 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
899 {
900 	uint32_t target_timeout, current_timeout;
901 	uint8_t div;
902 
903 	if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
904 		slot->data_done = 1;
905 		return;
906 	}
907 
908 	slot->data_done = 0;
909 
910 	/* Calculate and set data timeout.*/
911 	/* XXX: We should have this from mmc layer, now assume 1 sec. */
912 	if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
913 		div = 0xE;
914 	} else {
915 		target_timeout = 1000000;
916 		div = 0;
917 		current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
918 		while (current_timeout < target_timeout && div < 0xE) {
919 			++div;
920 			current_timeout <<= 1;
921 		}
922 		/* Compensate for an off-by-one error in the CaFe chip.*/
923 		if (div < 0xE &&
924 		    (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
925 			++div;
926 		}
927 	}
928 	WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
929 
930 	if (data == NULL)
931 		return;
932 
933 	/* Use DMA if possible. */
934 	if ((slot->opt & SDHCI_HAVE_DMA))
935 		slot->flags |= SDHCI_USE_DMA;
936 	/* If data is small, broken DMA may return zeroes instead of data, */
937 	if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
938 	    (data->len <= 512))
939 		slot->flags &= ~SDHCI_USE_DMA;
940 	/* Some controllers require even block sizes. */
941 	if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
942 	    ((data->len) & 0x3))
943 		slot->flags &= ~SDHCI_USE_DMA;
944 	/* Load DMA buffer. */
945 	if (slot->flags & SDHCI_USE_DMA) {
946 		if (data->flags & MMC_DATA_READ)
947 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
948 			    BUS_DMASYNC_PREREAD);
949 		else {
950 			memcpy(slot->dmamem, data->data,
951 			    (data->len < DMA_BLOCK_SIZE) ?
952 			    data->len : DMA_BLOCK_SIZE);
953 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
954 			    BUS_DMASYNC_PREWRITE);
955 		}
956 		WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
957 		/* Interrupt aggregation: Mask border interrupt
958 		 * for the last page and unmask else. */
959 		if (data->len == DMA_BLOCK_SIZE)
960 			slot->intmask &= ~SDHCI_INT_DMA_END;
961 		else
962 			slot->intmask |= SDHCI_INT_DMA_END;
963 		WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
964 	}
965 	/* Current data offset for both PIO and DMA. */
966 	slot->offset = 0;
967 	/* Set block size and request IRQ on 4K border. */
968 	WR2(slot, SDHCI_BLOCK_SIZE,
969 	    SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
970 	/* Set block count. */
971 	WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
972 }
973 
974 void
975 sdhci_finish_data(struct sdhci_slot *slot)
976 {
977 	struct mmc_data *data = slot->curcmd->data;
978 
979 	slot->data_done = 1;
980 	/* Interrupt aggregation: Restore command interrupt.
981 	 * Auxiliary restore point for the case when data interrupt
982 	 * happened first. */
983 	if (!slot->cmd_done) {
984 		WR4(slot, SDHCI_SIGNAL_ENABLE,
985 		    slot->intmask |= SDHCI_INT_RESPONSE);
986 	}
987 	/* Unload rest of data from DMA buffer. */
988 	if (slot->flags & SDHCI_USE_DMA) {
989 		if (data->flags & MMC_DATA_READ) {
990 			size_t left = data->len - slot->offset;
991 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
992 			    BUS_DMASYNC_POSTREAD);
993 			memcpy((u_char*)data->data + slot->offset, slot->dmamem,
994 			    (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
995 		} else
996 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
997 			    BUS_DMASYNC_POSTWRITE);
998 	}
999 	/* If there was error - reset the host. */
1000 	if (slot->curcmd->error) {
1001 		sdhci_reset(slot, SDHCI_RESET_CMD);
1002 		sdhci_reset(slot, SDHCI_RESET_DATA);
1003 		sdhci_start(slot);
1004 		return;
1005 	}
1006 	/* If we already have command response - finish. */
1007 	if (slot->cmd_done)
1008 		sdhci_start(slot);
1009 }
1010 
1011 static void
1012 sdhci_start(struct sdhci_slot *slot)
1013 {
1014 	struct mmc_request *req;
1015 
1016 	req = slot->req;
1017 	if (req == NULL)
1018 		return;
1019 
1020 	if (!(slot->flags & CMD_STARTED)) {
1021 		slot->flags |= CMD_STARTED;
1022 		sdhci_start_command(slot, req->cmd);
1023 		return;
1024 	}
1025 /* 	We don't need this until using Auto-CMD12 feature
1026 	if (!(slot->flags & STOP_STARTED) && req->stop) {
1027 		slot->flags |= STOP_STARTED;
1028 		sdhci_start_command(slot, req->stop);
1029 		return;
1030 	}
1031 */
1032 	if (sdhci_debug > 1)
1033 		slot_printf(slot, "result: %d\n", req->cmd->error);
1034 	if (!req->cmd->error &&
1035 	    (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1036 		sdhci_reset(slot, SDHCI_RESET_CMD);
1037 		sdhci_reset(slot, SDHCI_RESET_DATA);
1038 	}
1039 
1040 	sdhci_req_done(slot);
1041 }
1042 
1043 int
1044 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1045 {
1046 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1047 
1048 	SDHCI_LOCK(slot);
1049 	if (slot->req != NULL) {
1050 		SDHCI_UNLOCK(slot);
1051 		return (EBUSY);
1052 	}
1053 	if (sdhci_debug > 1) {
1054 		slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1055     		    req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1056     		    (req->cmd->data)?(u_int)req->cmd->data->len:0,
1057 		    (req->cmd->data)?req->cmd->data->flags:0);
1058 	}
1059 	slot->req = req;
1060 	slot->flags = 0;
1061 	sdhci_start(slot);
1062 	SDHCI_UNLOCK(slot);
1063 	if (dumping) {
1064 		while (slot->req != NULL) {
1065 			sdhci_generic_intr(slot);
1066 			DELAY(10);
1067 		}
1068 	}
1069 	return (0);
1070 }
1071 
1072 int
1073 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1074 {
1075 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1076 	uint32_t val;
1077 
1078 	SDHCI_LOCK(slot);
1079 	val = RD4(slot, SDHCI_PRESENT_STATE);
1080 	SDHCI_UNLOCK(slot);
1081 	return (!(val & SDHCI_WRITE_PROTECT));
1082 }
1083 
1084 int
1085 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1086 {
1087 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1088 	int err = 0;
1089 
1090 	SDHCI_LOCK(slot);
1091 	while (slot->bus_busy)
1092 		msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1093 	slot->bus_busy++;
1094 	/* Activate led. */
1095 	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1096 	SDHCI_UNLOCK(slot);
1097 	return (err);
1098 }
1099 
1100 int
1101 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1102 {
1103 	struct sdhci_slot *slot = device_get_ivars(reqdev);
1104 
1105 	SDHCI_LOCK(slot);
1106 	/* Deactivate led. */
1107 	WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1108 	slot->bus_busy--;
1109 	SDHCI_UNLOCK(slot);
1110 	wakeup(slot);
1111 	return (0);
1112 }
1113 
1114 static void
1115 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1116 {
1117 
1118 	if (!slot->curcmd) {
1119 		slot_printf(slot, "Got command interrupt 0x%08x, but "
1120 		    "there is no active command.\n", intmask);
1121 		sdhci_dumpregs(slot);
1122 		return;
1123 	}
1124 	if (intmask & SDHCI_INT_TIMEOUT)
1125 		slot->curcmd->error = MMC_ERR_TIMEOUT;
1126 	else if (intmask & SDHCI_INT_CRC)
1127 		slot->curcmd->error = MMC_ERR_BADCRC;
1128 	else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1129 		slot->curcmd->error = MMC_ERR_FIFO;
1130 
1131 	sdhci_finish_command(slot);
1132 }
1133 
1134 static void
1135 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1136 {
1137 
1138 	if (!slot->curcmd) {
1139 		slot_printf(slot, "Got data interrupt 0x%08x, but "
1140 		    "there is no active command.\n", intmask);
1141 		sdhci_dumpregs(slot);
1142 		return;
1143 	}
1144 	if (slot->curcmd->data == NULL &&
1145 	    (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1146 		slot_printf(slot, "Got data interrupt 0x%08x, but "
1147 		    "there is no active data operation.\n",
1148 		    intmask);
1149 		sdhci_dumpregs(slot);
1150 		return;
1151 	}
1152 	if (intmask & SDHCI_INT_DATA_TIMEOUT)
1153 		slot->curcmd->error = MMC_ERR_TIMEOUT;
1154 	else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1155 		slot->curcmd->error = MMC_ERR_BADCRC;
1156 	if (slot->curcmd->data == NULL &&
1157 	    (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1158 	    SDHCI_INT_DMA_END))) {
1159 		slot_printf(slot, "Got data interrupt 0x%08x, but "
1160 		    "there is busy-only command.\n", intmask);
1161 		sdhci_dumpregs(slot);
1162 		slot->curcmd->error = MMC_ERR_INVALID;
1163 	}
1164 	if (slot->curcmd->error) {
1165 		/* No need to continue after any error. */
1166 		if (slot->flags & PLATFORM_DATA_STARTED) {
1167 			slot->flags &= ~PLATFORM_DATA_STARTED;
1168 			SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1169 		} else
1170 			sdhci_finish_data(slot);
1171 		return;
1172 	}
1173 
1174 	/* Handle PIO interrupt. */
1175 	if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1176 		if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1177 		    SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1178 			SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1179 			slot->flags |= PLATFORM_DATA_STARTED;
1180 		} else
1181 			sdhci_transfer_pio(slot);
1182 	}
1183 	/* Handle DMA border. */
1184 	if (intmask & SDHCI_INT_DMA_END) {
1185 		struct mmc_data *data = slot->curcmd->data;
1186 		size_t left;
1187 
1188 		/* Unload DMA buffer... */
1189 		left = data->len - slot->offset;
1190 		if (data->flags & MMC_DATA_READ) {
1191 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1192 			    BUS_DMASYNC_POSTREAD);
1193 			memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1194 			    (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1195 		} else {
1196 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1197 			    BUS_DMASYNC_POSTWRITE);
1198 		}
1199 		/* ... and reload it again. */
1200 		slot->offset += DMA_BLOCK_SIZE;
1201 		left = data->len - slot->offset;
1202 		if (data->flags & MMC_DATA_READ) {
1203 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1204 			    BUS_DMASYNC_PREREAD);
1205 		} else {
1206 			memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1207 			    (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1208 			bus_dmamap_sync(slot->dmatag, slot->dmamap,
1209 			    BUS_DMASYNC_PREWRITE);
1210 		}
1211 		/* Interrupt aggregation: Mask border interrupt
1212 		 * for the last page. */
1213 		if (left == DMA_BLOCK_SIZE) {
1214 			slot->intmask &= ~SDHCI_INT_DMA_END;
1215 			WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1216 		}
1217 		/* Restart DMA. */
1218 		WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1219 	}
1220 	/* We have got all data. */
1221 	if (intmask & SDHCI_INT_DATA_END) {
1222 		if (slot->flags & PLATFORM_DATA_STARTED) {
1223 			slot->flags &= ~PLATFORM_DATA_STARTED;
1224 			SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1225 		} else
1226 			sdhci_finish_data(slot);
1227 	}
1228 }
1229 
1230 static void
1231 sdhci_acmd_irq(struct sdhci_slot *slot)
1232 {
1233 	uint16_t err;
1234 
1235 	err = RD4(slot, SDHCI_ACMD12_ERR);
1236 	if (!slot->curcmd) {
1237 		slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1238 		    "there is no active command.\n", err);
1239 		sdhci_dumpregs(slot);
1240 		return;
1241 	}
1242 	slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1243 	sdhci_reset(slot, SDHCI_RESET_CMD);
1244 }
1245 
1246 void
1247 sdhci_generic_intr(struct sdhci_slot *slot)
1248 {
1249 	uint32_t intmask;
1250 
1251 	SDHCI_LOCK(slot);
1252 	/* Read slot interrupt status. */
1253 	intmask = RD4(slot, SDHCI_INT_STATUS);
1254 	if (intmask == 0 || intmask == 0xffffffff) {
1255 		SDHCI_UNLOCK(slot);
1256 		return;
1257 	}
1258 	if (sdhci_debug > 2)
1259 		slot_printf(slot, "Interrupt %#x\n", intmask);
1260 
1261 	/* Handle card presence interrupts. */
1262 	if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1263 		WR4(slot, SDHCI_INT_STATUS, intmask &
1264 		    (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1265 
1266 		if (intmask & SDHCI_INT_CARD_REMOVE) {
1267 			if (bootverbose || sdhci_debug)
1268 				slot_printf(slot, "Card removed\n");
1269 			callout_stop(&slot->card_callout);
1270 			taskqueue_enqueue(taskqueue_swi_giant,
1271 			    &slot->card_task);
1272 		}
1273 		if (intmask & SDHCI_INT_CARD_INSERT) {
1274 			if (bootverbose || sdhci_debug)
1275 				slot_printf(slot, "Card inserted\n");
1276 			callout_reset(&slot->card_callout, hz / 2,
1277 			    sdhci_card_delay, slot);
1278 		}
1279 		intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1280 	}
1281 	/* Handle command interrupts. */
1282 	if (intmask & SDHCI_INT_CMD_MASK) {
1283 		WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1284 		sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1285 	}
1286 	/* Handle data interrupts. */
1287 	if (intmask & SDHCI_INT_DATA_MASK) {
1288 		WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1289 		sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1290 	}
1291 	/* Handle AutoCMD12 error interrupt. */
1292 	if (intmask & SDHCI_INT_ACMD12ERR) {
1293 		WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1294 		sdhci_acmd_irq(slot);
1295 	}
1296 	intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1297 	intmask &= ~SDHCI_INT_ACMD12ERR;
1298 	intmask &= ~SDHCI_INT_ERROR;
1299 	/* Handle bus power interrupt. */
1300 	if (intmask & SDHCI_INT_BUS_POWER) {
1301 		WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1302 		slot_printf(slot,
1303 		    "Card is consuming too much power!\n");
1304 		intmask &= ~SDHCI_INT_BUS_POWER;
1305 	}
1306 	/* The rest is unknown. */
1307 	if (intmask) {
1308 		WR4(slot, SDHCI_INT_STATUS, intmask);
1309 		slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1310 		    intmask);
1311 		sdhci_dumpregs(slot);
1312 	}
1313 
1314 	SDHCI_UNLOCK(slot);
1315 }
1316 
1317 int
1318 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1319 {
1320 	struct sdhci_slot *slot = device_get_ivars(child);
1321 
1322 	switch (which) {
1323 	default:
1324 		return (EINVAL);
1325 	case MMCBR_IVAR_BUS_MODE:
1326 		*result = slot->host.ios.bus_mode;
1327 		break;
1328 	case MMCBR_IVAR_BUS_WIDTH:
1329 		*result = slot->host.ios.bus_width;
1330 		break;
1331 	case MMCBR_IVAR_CHIP_SELECT:
1332 		*result = slot->host.ios.chip_select;
1333 		break;
1334 	case MMCBR_IVAR_CLOCK:
1335 		*result = slot->host.ios.clock;
1336 		break;
1337 	case MMCBR_IVAR_F_MIN:
1338 		*result = slot->host.f_min;
1339 		break;
1340 	case MMCBR_IVAR_F_MAX:
1341 		*result = slot->host.f_max;
1342 		break;
1343 	case MMCBR_IVAR_HOST_OCR:
1344 		*result = slot->host.host_ocr;
1345 		break;
1346 	case MMCBR_IVAR_MODE:
1347 		*result = slot->host.mode;
1348 		break;
1349 	case MMCBR_IVAR_OCR:
1350 		*result = slot->host.ocr;
1351 		break;
1352 	case MMCBR_IVAR_POWER_MODE:
1353 		*result = slot->host.ios.power_mode;
1354 		break;
1355 	case MMCBR_IVAR_VDD:
1356 		*result = slot->host.ios.vdd;
1357 		break;
1358 	case MMCBR_IVAR_CAPS:
1359 		*result = slot->host.caps;
1360 		break;
1361 	case MMCBR_IVAR_TIMING:
1362 		*result = slot->host.ios.timing;
1363 		break;
1364 	case MMCBR_IVAR_MAX_DATA:
1365 		*result = 65535;
1366 		break;
1367 	}
1368 	return (0);
1369 }
1370 
1371 int
1372 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1373 {
1374 	struct sdhci_slot *slot = device_get_ivars(child);
1375 
1376 	switch (which) {
1377 	default:
1378 		return (EINVAL);
1379 	case MMCBR_IVAR_BUS_MODE:
1380 		slot->host.ios.bus_mode = value;
1381 		break;
1382 	case MMCBR_IVAR_BUS_WIDTH:
1383 		slot->host.ios.bus_width = value;
1384 		break;
1385 	case MMCBR_IVAR_CHIP_SELECT:
1386 		slot->host.ios.chip_select = value;
1387 		break;
1388 	case MMCBR_IVAR_CLOCK:
1389 		if (value > 0) {
1390 			uint32_t max_clock;
1391 			uint32_t clock;
1392 			int i;
1393 
1394 			max_clock = slot->max_clk;
1395 			clock = max_clock;
1396 
1397 			if (slot->version < SDHCI_SPEC_300) {
1398 				for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1399 				    i <<= 1) {
1400 					if (clock <= value)
1401 						break;
1402 					clock >>= 1;
1403 				}
1404 			}
1405 			else {
1406 				for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1407 				    i += 2) {
1408 					if (clock <= value)
1409 						break;
1410 					clock = max_clock / (i + 2);
1411 				}
1412 			}
1413 
1414 			slot->host.ios.clock = clock;
1415 		} else
1416 			slot->host.ios.clock = 0;
1417 		break;
1418 	case MMCBR_IVAR_MODE:
1419 		slot->host.mode = value;
1420 		break;
1421 	case MMCBR_IVAR_OCR:
1422 		slot->host.ocr = value;
1423 		break;
1424 	case MMCBR_IVAR_POWER_MODE:
1425 		slot->host.ios.power_mode = value;
1426 		break;
1427 	case MMCBR_IVAR_VDD:
1428 		slot->host.ios.vdd = value;
1429 		break;
1430 	case MMCBR_IVAR_TIMING:
1431 		slot->host.ios.timing = value;
1432 		break;
1433 	case MMCBR_IVAR_CAPS:
1434 	case MMCBR_IVAR_HOST_OCR:
1435 	case MMCBR_IVAR_F_MIN:
1436 	case MMCBR_IVAR_F_MAX:
1437 	case MMCBR_IVAR_MAX_DATA:
1438 		return (EINVAL);
1439 	}
1440 	return (0);
1441 }
1442 
1443 MODULE_VERSION(sdhci, 1);
1444