1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include "mmcbr_if.h" 52 #include "sdhci.h" 53 #include "sdhci_if.h" 54 55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 56 57 static int sdhci_debug; 58 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level"); 59 60 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 61 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 62 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 63 #define RD_MULTI_4(slot, off, ptr, count) \ 64 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 65 66 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 67 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 68 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 69 #define WR_MULTI_4(slot, off, ptr, count) \ 70 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 71 72 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 73 static void sdhci_start(struct sdhci_slot *slot); 74 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 75 76 static void sdhci_card_task(void *, int); 77 78 /* helper routines */ 79 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 80 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 81 #define SDHCI_LOCK_INIT(_slot) \ 82 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 83 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 84 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 85 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 86 87 #define SDHCI_DEFAULT_MAX_FREQ 50 88 89 #define SDHCI_200_MAX_DIVIDER 256 90 #define SDHCI_300_MAX_DIVIDER 2046 91 92 /* 93 * Broadcom BCM577xx Controller Constants 94 */ 95 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Maximum divider supported by the default clock source. */ 96 #define BCM577XX_ALT_CLOCK_BASE 63000000 /* Alternative clock's base frequency. */ 97 98 #define BCM577XX_HOST_CONTROL 0x198 99 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 100 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 101 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 102 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 103 104 105 static void 106 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 107 { 108 if (error != 0) { 109 printf("getaddr: error %d\n", error); 110 return; 111 } 112 *(bus_addr_t *)arg = segs[0].ds_addr; 113 } 114 115 static int 116 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 117 { 118 va_list ap; 119 int retval; 120 121 retval = printf("%s-slot%d: ", 122 device_get_nameunit(slot->bus), slot->num); 123 124 va_start(ap, fmt); 125 retval += vprintf(fmt, ap); 126 va_end(ap); 127 return (retval); 128 } 129 130 static void 131 sdhci_dumpregs(struct sdhci_slot *slot) 132 { 133 slot_printf(slot, 134 "============== REGISTER DUMP ==============\n"); 135 136 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 137 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 138 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 139 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 140 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 141 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 142 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 143 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 144 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 145 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 146 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 147 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 148 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 149 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 150 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 151 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 152 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 153 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 154 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 155 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 156 157 slot_printf(slot, 158 "===========================================\n"); 159 } 160 161 static void 162 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 163 { 164 int timeout; 165 166 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 167 if (!(RD4(slot, SDHCI_PRESENT_STATE) & 168 SDHCI_CARD_PRESENT)) 169 return; 170 } 171 172 /* Some controllers need this kick or reset won't work. */ 173 if ((mask & SDHCI_RESET_ALL) == 0 && 174 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 175 uint32_t clock; 176 177 /* This is to force an update */ 178 clock = slot->clock; 179 slot->clock = 0; 180 sdhci_set_clock(slot, clock); 181 } 182 183 if (mask & SDHCI_RESET_ALL) { 184 slot->clock = 0; 185 slot->power = 0; 186 } 187 188 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 189 190 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 191 /* 192 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 193 * specification. The reset bit has internal propagation delay, 194 * so a fast read after write returns 0 even if reset process is 195 * in progress. The workaround is to poll for 1 before polling 196 * for 0. In the worst case, if we miss seeing it asserted the 197 * time we spent waiting is enough to ensure the reset finishes. 198 */ 199 timeout = 10000; 200 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 201 if (timeout <= 0) 202 break; 203 timeout--; 204 DELAY(1); 205 } 206 } 207 208 /* Wait max 100 ms */ 209 timeout = 10000; 210 /* Controller clears the bits when it's done */ 211 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 212 if (timeout <= 0) { 213 slot_printf(slot, "Reset 0x%x never completed.\n", 214 mask); 215 sdhci_dumpregs(slot); 216 return; 217 } 218 timeout--; 219 DELAY(10); 220 } 221 } 222 223 static void 224 sdhci_init(struct sdhci_slot *slot) 225 { 226 227 sdhci_reset(slot, SDHCI_RESET_ALL); 228 229 /* Enable interrupts. */ 230 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 231 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 232 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 233 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 234 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 235 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 236 SDHCI_INT_ACMD12ERR; 237 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 238 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 239 } 240 241 static void 242 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 243 { 244 uint32_t clk_base; 245 uint32_t clk_sel; 246 uint32_t res; 247 uint16_t clk; 248 uint16_t div; 249 int timeout; 250 251 if (clock == slot->clock) 252 return; 253 slot->clock = clock; 254 255 /* Turn off the clock. */ 256 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 257 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 258 /* If no clock requested - left it so. */ 259 if (clock == 0) 260 return; 261 262 /* Determine the clock base frequency */ 263 clk_base = slot->max_clk; 264 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 265 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; 266 267 /* Select clock source appropriate for the requested frequency. */ 268 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 269 clk_base = BCM577XX_ALT_CLOCK_BASE; 270 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); 271 } else { 272 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); 273 } 274 275 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 276 } 277 278 /* Recalculate timeout clock frequency based on the new sd clock. */ 279 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 280 slot->timeout_clk = slot->clock / 1000; 281 282 if (slot->version < SDHCI_SPEC_300) { 283 /* Looking for highest freq <= clock. */ 284 res = clk_base; 285 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 286 if (res <= clock) 287 break; 288 res >>= 1; 289 } 290 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 291 div >>= 1; 292 } 293 else { 294 /* Version 3.0 divisors are multiples of two up to 1023*2 */ 295 if (clock >= clk_base) 296 div = 0; 297 else { 298 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 299 if ((clk_base / div) <= clock) 300 break; 301 } 302 } 303 div >>= 1; 304 } 305 306 if (bootverbose || sdhci_debug) 307 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 308 div, clock, clk_base); 309 310 /* Now we have got divider, set it. */ 311 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 312 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 313 << SDHCI_DIVIDER_HI_SHIFT; 314 315 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 316 /* Enable clock. */ 317 clk |= SDHCI_CLOCK_INT_EN; 318 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 319 /* Wait up to 10 ms until it stabilize. */ 320 timeout = 10; 321 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 322 & SDHCI_CLOCK_INT_STABLE)) { 323 if (timeout == 0) { 324 slot_printf(slot, 325 "Internal clock never stabilised.\n"); 326 sdhci_dumpregs(slot); 327 return; 328 } 329 timeout--; 330 DELAY(1000); 331 } 332 /* Pass clock signal to the bus. */ 333 clk |= SDHCI_CLOCK_CARD_EN; 334 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 335 } 336 337 static void 338 sdhci_set_power(struct sdhci_slot *slot, u_char power) 339 { 340 uint8_t pwr; 341 342 if (slot->power == power) 343 return; 344 345 slot->power = power; 346 347 /* Turn off the power. */ 348 pwr = 0; 349 WR1(slot, SDHCI_POWER_CONTROL, pwr); 350 /* If power down requested - left it so. */ 351 if (power == 0) 352 return; 353 /* Set voltage. */ 354 switch (1 << power) { 355 case MMC_OCR_LOW_VOLTAGE: 356 pwr |= SDHCI_POWER_180; 357 break; 358 case MMC_OCR_290_300: 359 case MMC_OCR_300_310: 360 pwr |= SDHCI_POWER_300; 361 break; 362 case MMC_OCR_320_330: 363 case MMC_OCR_330_340: 364 pwr |= SDHCI_POWER_330; 365 break; 366 } 367 WR1(slot, SDHCI_POWER_CONTROL, pwr); 368 /* Turn on the power. */ 369 pwr |= SDHCI_POWER_ON; 370 WR1(slot, SDHCI_POWER_CONTROL, pwr); 371 } 372 373 static void 374 sdhci_read_block_pio(struct sdhci_slot *slot) 375 { 376 uint32_t data; 377 char *buffer; 378 size_t left; 379 380 buffer = slot->curcmd->data->data; 381 buffer += slot->offset; 382 /* Transfer one block at a time. */ 383 left = min(512, slot->curcmd->data->len - slot->offset); 384 slot->offset += left; 385 386 /* If we are too fast, broken controllers return zeroes. */ 387 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 388 DELAY(10); 389 /* Handle unaligned and aligned buffer cases. */ 390 if ((intptr_t)buffer & 3) { 391 while (left > 3) { 392 data = RD4(slot, SDHCI_BUFFER); 393 buffer[0] = data; 394 buffer[1] = (data >> 8); 395 buffer[2] = (data >> 16); 396 buffer[3] = (data >> 24); 397 buffer += 4; 398 left -= 4; 399 } 400 } else { 401 RD_MULTI_4(slot, SDHCI_BUFFER, 402 (uint32_t *)buffer, left >> 2); 403 left &= 3; 404 } 405 /* Handle uneven size case. */ 406 if (left > 0) { 407 data = RD4(slot, SDHCI_BUFFER); 408 while (left > 0) { 409 *(buffer++) = data; 410 data >>= 8; 411 left--; 412 } 413 } 414 } 415 416 static void 417 sdhci_write_block_pio(struct sdhci_slot *slot) 418 { 419 uint32_t data = 0; 420 char *buffer; 421 size_t left; 422 423 buffer = slot->curcmd->data->data; 424 buffer += slot->offset; 425 /* Transfer one block at a time. */ 426 left = min(512, slot->curcmd->data->len - slot->offset); 427 slot->offset += left; 428 429 /* Handle unaligned and aligned buffer cases. */ 430 if ((intptr_t)buffer & 3) { 431 while (left > 3) { 432 data = buffer[0] + 433 (buffer[1] << 8) + 434 (buffer[2] << 16) + 435 (buffer[3] << 24); 436 left -= 4; 437 buffer += 4; 438 WR4(slot, SDHCI_BUFFER, data); 439 } 440 } else { 441 WR_MULTI_4(slot, SDHCI_BUFFER, 442 (uint32_t *)buffer, left >> 2); 443 left &= 3; 444 } 445 /* Handle uneven size case. */ 446 if (left > 0) { 447 while (left > 0) { 448 data <<= 8; 449 data += *(buffer++); 450 left--; 451 } 452 WR4(slot, SDHCI_BUFFER, data); 453 } 454 } 455 456 static void 457 sdhci_transfer_pio(struct sdhci_slot *slot) 458 { 459 460 /* Read as many blocks as possible. */ 461 if (slot->curcmd->data->flags & MMC_DATA_READ) { 462 while (RD4(slot, SDHCI_PRESENT_STATE) & 463 SDHCI_DATA_AVAILABLE) { 464 sdhci_read_block_pio(slot); 465 if (slot->offset >= slot->curcmd->data->len) 466 break; 467 } 468 } else { 469 while (RD4(slot, SDHCI_PRESENT_STATE) & 470 SDHCI_SPACE_AVAILABLE) { 471 sdhci_write_block_pio(slot); 472 if (slot->offset >= slot->curcmd->data->len) 473 break; 474 } 475 } 476 } 477 478 static void 479 sdhci_card_delay(void *arg) 480 { 481 struct sdhci_slot *slot = arg; 482 483 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 484 } 485 486 static void 487 sdhci_card_task(void *arg, int pending) 488 { 489 struct sdhci_slot *slot = arg; 490 491 SDHCI_LOCK(slot); 492 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 493 if (slot->dev == NULL) { 494 /* If card is present - attach mmc bus. */ 495 slot->dev = device_add_child(slot->bus, "mmc", -1); 496 device_set_ivars(slot->dev, slot); 497 SDHCI_UNLOCK(slot); 498 device_probe_and_attach(slot->dev); 499 } else 500 SDHCI_UNLOCK(slot); 501 } else { 502 if (slot->dev != NULL) { 503 /* If no card present - detach mmc bus. */ 504 device_t d = slot->dev; 505 slot->dev = NULL; 506 SDHCI_UNLOCK(slot); 507 device_delete_child(slot->bus, d); 508 } else 509 SDHCI_UNLOCK(slot); 510 } 511 } 512 513 int 514 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 515 { 516 uint32_t caps, freq; 517 int err; 518 519 SDHCI_LOCK_INIT(slot); 520 slot->num = num; 521 slot->bus = dev; 522 523 /* Allocate DMA tag. */ 524 err = bus_dma_tag_create(bus_get_dma_tag(dev), 525 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 526 BUS_SPACE_MAXADDR, NULL, NULL, 527 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 528 BUS_DMA_ALLOCNOW, NULL, NULL, 529 &slot->dmatag); 530 if (err != 0) { 531 device_printf(dev, "Can't create DMA tag\n"); 532 SDHCI_LOCK_DESTROY(slot); 533 return (err); 534 } 535 /* Allocate DMA memory. */ 536 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 537 BUS_DMA_NOWAIT, &slot->dmamap); 538 if (err != 0) { 539 device_printf(dev, "Can't alloc DMA memory\n"); 540 SDHCI_LOCK_DESTROY(slot); 541 return (err); 542 } 543 /* Map the memory. */ 544 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 545 (void *)slot->dmamem, DMA_BLOCK_SIZE, 546 sdhci_getaddr, &slot->paddr, 0); 547 if (err != 0 || slot->paddr == 0) { 548 device_printf(dev, "Can't load DMA memory\n"); 549 SDHCI_LOCK_DESTROY(slot); 550 if(err) 551 return (err); 552 else 553 return (EFAULT); 554 } 555 556 /* Initialize slot. */ 557 sdhci_init(slot); 558 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 559 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 560 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) 561 caps = slot->caps; 562 else 563 caps = RD4(slot, SDHCI_CAPABILITIES); 564 /* Calculate base clock frequency. */ 565 if (slot->version >= SDHCI_SPEC_300) 566 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 567 SDHCI_CLOCK_BASE_SHIFT; 568 else 569 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 570 SDHCI_CLOCK_BASE_SHIFT; 571 if (freq != 0) 572 slot->max_clk = freq * 1000000; 573 /* 574 * If the frequency wasn't in the capabilities and the hardware driver 575 * hasn't already set max_clk we're probably not going to work right 576 * with an assumption, so complain about it. 577 */ 578 if (slot->max_clk == 0) { 579 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 580 device_printf(dev, "Hardware doesn't specify base clock " 581 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); 582 } 583 /* Calculate timeout clock frequency. */ 584 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 585 slot->timeout_clk = slot->max_clk / 1000; 586 } else { 587 slot->timeout_clk = 588 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 589 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 590 slot->timeout_clk *= 1000; 591 } 592 /* 593 * If the frequency wasn't in the capabilities and the hardware driver 594 * hasn't already set timeout_clk we'll probably work okay using the 595 * max timeout, but still mention it. 596 */ 597 if (slot->timeout_clk == 0) { 598 device_printf(dev, "Hardware doesn't specify timeout clock " 599 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 600 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 601 } 602 603 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 604 slot->host.f_max = slot->max_clk; 605 slot->host.host_ocr = 0; 606 if (caps & SDHCI_CAN_VDD_330) 607 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 608 if (caps & SDHCI_CAN_VDD_300) 609 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 610 if (caps & SDHCI_CAN_VDD_180) 611 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 612 if (slot->host.host_ocr == 0) { 613 device_printf(dev, "Hardware doesn't report any " 614 "support voltages.\n"); 615 } 616 slot->host.caps = MMC_CAP_4_BIT_DATA; 617 if (caps & SDHCI_CAN_DO_8BITBUS) 618 slot->host.caps |= MMC_CAP_8_BIT_DATA; 619 if (caps & SDHCI_CAN_DO_HISPD) 620 slot->host.caps |= MMC_CAP_HSPEED; 621 /* Decide if we have usable DMA. */ 622 if (caps & SDHCI_CAN_DO_DMA) 623 slot->opt |= SDHCI_HAVE_DMA; 624 625 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 626 slot->opt &= ~SDHCI_HAVE_DMA; 627 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 628 slot->opt |= SDHCI_HAVE_DMA; 629 630 /* 631 * Use platform-provided transfer backend 632 * with PIO as a fallback mechanism 633 */ 634 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 635 slot->opt &= ~SDHCI_HAVE_DMA; 636 637 if (bootverbose || sdhci_debug) { 638 slot_printf(slot, "%uMHz%s %s%s%s%s %s\n", 639 slot->max_clk / 1000000, 640 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 641 (caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 642 ((caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 643 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 644 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 645 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 646 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 647 sdhci_dumpregs(slot); 648 } 649 650 slot->timeout = 10; 651 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 652 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 653 "timeout", CTLFLAG_RW, &slot->timeout, 0, 654 "Maximum timeout for SDHCI transfers (in secs)"); 655 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 656 callout_init(&slot->card_callout, 1); 657 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 658 659 return (0); 660 } 661 662 void 663 sdhci_start_slot(struct sdhci_slot *slot) 664 { 665 sdhci_card_task(slot, 0); 666 } 667 668 int 669 sdhci_cleanup_slot(struct sdhci_slot *slot) 670 { 671 device_t d; 672 673 callout_drain(&slot->timeout_callout); 674 callout_drain(&slot->card_callout); 675 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 676 677 SDHCI_LOCK(slot); 678 d = slot->dev; 679 slot->dev = NULL; 680 SDHCI_UNLOCK(slot); 681 if (d != NULL) 682 device_delete_child(slot->bus, d); 683 684 SDHCI_LOCK(slot); 685 sdhci_reset(slot, SDHCI_RESET_ALL); 686 SDHCI_UNLOCK(slot); 687 bus_dmamap_unload(slot->dmatag, slot->dmamap); 688 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 689 bus_dma_tag_destroy(slot->dmatag); 690 691 SDHCI_LOCK_DESTROY(slot); 692 693 return (0); 694 } 695 696 int 697 sdhci_generic_suspend(struct sdhci_slot *slot) 698 { 699 sdhci_reset(slot, SDHCI_RESET_ALL); 700 701 return (0); 702 } 703 704 int 705 sdhci_generic_resume(struct sdhci_slot *slot) 706 { 707 sdhci_init(slot); 708 709 return (0); 710 } 711 712 uint32_t 713 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot) 714 { 715 if (slot->version >= SDHCI_SPEC_300) 716 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 717 else 718 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 719 } 720 721 int 722 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 723 { 724 struct sdhci_slot *slot = device_get_ivars(reqdev); 725 struct mmc_ios *ios = &slot->host.ios; 726 727 SDHCI_LOCK(slot); 728 /* Do full reset on bus power down to clear from any state. */ 729 if (ios->power_mode == power_off) { 730 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 731 sdhci_init(slot); 732 } 733 /* Configure the bus. */ 734 sdhci_set_clock(slot, ios->clock); 735 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 736 if (ios->bus_width == bus_width_8) { 737 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 738 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 739 } else if (ios->bus_width == bus_width_4) { 740 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 741 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 742 } else if (ios->bus_width == bus_width_1) { 743 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 744 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 745 } else { 746 panic("Invalid bus width: %d", ios->bus_width); 747 } 748 if (ios->timing == bus_timing_hs && 749 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 750 slot->hostctrl |= SDHCI_CTRL_HISPD; 751 else 752 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 753 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 754 /* Some controllers like reset after bus changes. */ 755 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 756 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 757 758 SDHCI_UNLOCK(slot); 759 return (0); 760 } 761 762 static void 763 sdhci_req_done(struct sdhci_slot *slot) 764 { 765 struct mmc_request *req; 766 767 if (slot->req != NULL && slot->curcmd != NULL) { 768 callout_stop(&slot->timeout_callout); 769 req = slot->req; 770 slot->req = NULL; 771 slot->curcmd = NULL; 772 req->done(req); 773 } 774 } 775 776 static void 777 sdhci_timeout(void *arg) 778 { 779 struct sdhci_slot *slot = arg; 780 781 if (slot->curcmd != NULL) { 782 slot_printf(slot, " Controller timeout\n"); 783 sdhci_dumpregs(slot); 784 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 785 slot->curcmd->error = MMC_ERR_TIMEOUT; 786 sdhci_req_done(slot); 787 } else { 788 slot_printf(slot, " Spurious timeout - no active command\n"); 789 } 790 } 791 792 static void 793 sdhci_set_transfer_mode(struct sdhci_slot *slot, 794 struct mmc_data *data) 795 { 796 uint16_t mode; 797 798 if (data == NULL) 799 return; 800 801 mode = SDHCI_TRNS_BLK_CNT_EN; 802 if (data->len > 512) 803 mode |= SDHCI_TRNS_MULTI; 804 if (data->flags & MMC_DATA_READ) 805 mode |= SDHCI_TRNS_READ; 806 if (slot->req->stop) 807 mode |= SDHCI_TRNS_ACMD12; 808 if (slot->flags & SDHCI_USE_DMA) 809 mode |= SDHCI_TRNS_DMA; 810 811 WR2(slot, SDHCI_TRANSFER_MODE, mode); 812 } 813 814 static void 815 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 816 { 817 int flags, timeout; 818 uint32_t mask, state; 819 820 slot->curcmd = cmd; 821 slot->cmd_done = 0; 822 823 cmd->error = MMC_ERR_NONE; 824 825 /* This flags combination is not supported by controller. */ 826 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 827 slot_printf(slot, "Unsupported response type!\n"); 828 cmd->error = MMC_ERR_FAILED; 829 sdhci_req_done(slot); 830 return; 831 } 832 833 /* Read controller present state. */ 834 state = RD4(slot, SDHCI_PRESENT_STATE); 835 /* Do not issue command if there is no card, clock or power. 836 * Controller will not detect timeout without clock active. */ 837 if ((state & SDHCI_CARD_PRESENT) == 0 || 838 slot->power == 0 || 839 slot->clock == 0) { 840 cmd->error = MMC_ERR_FAILED; 841 sdhci_req_done(slot); 842 return; 843 } 844 /* Always wait for free CMD bus. */ 845 mask = SDHCI_CMD_INHIBIT; 846 /* Wait for free DAT if we have data or busy signal. */ 847 if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 848 mask |= SDHCI_DAT_INHIBIT; 849 /* We shouldn't wait for DAT for stop commands. */ 850 if (cmd == slot->req->stop) 851 mask &= ~SDHCI_DAT_INHIBIT; 852 /* 853 * Wait for bus no more then 250 ms. Typically there will be no wait 854 * here at all, but when writing a crash dump we may be bypassing the 855 * host platform's interrupt handler, and in some cases that handler 856 * may be working around hardware quirks such as not respecting r1b 857 * busy indications. In those cases, this wait-loop serves the purpose 858 * of waiting for the prior command and data transfers to be done, and 859 * SD cards are allowed to take up to 250ms for write and erase ops. 860 * (It's usually more like 20-30ms in the real world.) 861 */ 862 timeout = 250; 863 while (state & mask) { 864 if (timeout == 0) { 865 slot_printf(slot, "Controller never released " 866 "inhibit bit(s).\n"); 867 sdhci_dumpregs(slot); 868 cmd->error = MMC_ERR_FAILED; 869 sdhci_req_done(slot); 870 return; 871 } 872 timeout--; 873 DELAY(1000); 874 state = RD4(slot, SDHCI_PRESENT_STATE); 875 } 876 877 /* Prepare command flags. */ 878 if (!(cmd->flags & MMC_RSP_PRESENT)) 879 flags = SDHCI_CMD_RESP_NONE; 880 else if (cmd->flags & MMC_RSP_136) 881 flags = SDHCI_CMD_RESP_LONG; 882 else if (cmd->flags & MMC_RSP_BUSY) 883 flags = SDHCI_CMD_RESP_SHORT_BUSY; 884 else 885 flags = SDHCI_CMD_RESP_SHORT; 886 if (cmd->flags & MMC_RSP_CRC) 887 flags |= SDHCI_CMD_CRC; 888 if (cmd->flags & MMC_RSP_OPCODE) 889 flags |= SDHCI_CMD_INDEX; 890 if (cmd->data) 891 flags |= SDHCI_CMD_DATA; 892 if (cmd->opcode == MMC_STOP_TRANSMISSION) 893 flags |= SDHCI_CMD_TYPE_ABORT; 894 /* Prepare data. */ 895 sdhci_start_data(slot, cmd->data); 896 /* 897 * Interrupt aggregation: To reduce total number of interrupts 898 * group response interrupt with data interrupt when possible. 899 * If there going to be data interrupt, mask response one. 900 */ 901 if (slot->data_done == 0) { 902 WR4(slot, SDHCI_SIGNAL_ENABLE, 903 slot->intmask &= ~SDHCI_INT_RESPONSE); 904 } 905 /* Set command argument. */ 906 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 907 /* Set data transfer mode. */ 908 sdhci_set_transfer_mode(slot, cmd->data); 909 /* Start command. */ 910 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 911 /* Start timeout callout. */ 912 callout_reset(&slot->timeout_callout, slot->timeout * hz, 913 sdhci_timeout, slot); 914 } 915 916 static void 917 sdhci_finish_command(struct sdhci_slot *slot) 918 { 919 int i; 920 921 slot->cmd_done = 1; 922 /* Interrupt aggregation: Restore command interrupt. 923 * Main restore point for the case when command interrupt 924 * happened first. */ 925 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 926 /* In case of error - reset host and return. */ 927 if (slot->curcmd->error) { 928 sdhci_reset(slot, SDHCI_RESET_CMD); 929 sdhci_reset(slot, SDHCI_RESET_DATA); 930 sdhci_start(slot); 931 return; 932 } 933 /* If command has response - fetch it. */ 934 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 935 if (slot->curcmd->flags & MMC_RSP_136) { 936 /* CRC is stripped so we need one byte shift. */ 937 uint8_t extra = 0; 938 for (i = 0; i < 4; i++) { 939 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 940 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 941 slot->curcmd->resp[3 - i] = val; 942 else { 943 slot->curcmd->resp[3 - i] = 944 (val << 8) | extra; 945 extra = val >> 24; 946 } 947 } 948 } else 949 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 950 } 951 /* If data ready - finish. */ 952 if (slot->data_done) 953 sdhci_start(slot); 954 } 955 956 static void 957 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 958 { 959 uint32_t target_timeout, current_timeout; 960 uint8_t div; 961 962 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 963 slot->data_done = 1; 964 return; 965 } 966 967 slot->data_done = 0; 968 969 /* Calculate and set data timeout.*/ 970 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 971 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 972 div = 0xE; 973 } else { 974 target_timeout = 1000000; 975 div = 0; 976 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 977 while (current_timeout < target_timeout && div < 0xE) { 978 ++div; 979 current_timeout <<= 1; 980 } 981 /* Compensate for an off-by-one error in the CaFe chip.*/ 982 if (div < 0xE && 983 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 984 ++div; 985 } 986 } 987 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 988 989 if (data == NULL) 990 return; 991 992 /* Use DMA if possible. */ 993 if ((slot->opt & SDHCI_HAVE_DMA)) 994 slot->flags |= SDHCI_USE_DMA; 995 /* If data is small, broken DMA may return zeroes instead of data, */ 996 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 997 (data->len <= 512)) 998 slot->flags &= ~SDHCI_USE_DMA; 999 /* Some controllers require even block sizes. */ 1000 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1001 ((data->len) & 0x3)) 1002 slot->flags &= ~SDHCI_USE_DMA; 1003 /* Load DMA buffer. */ 1004 if (slot->flags & SDHCI_USE_DMA) { 1005 if (data->flags & MMC_DATA_READ) 1006 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1007 BUS_DMASYNC_PREREAD); 1008 else { 1009 memcpy(slot->dmamem, data->data, 1010 (data->len < DMA_BLOCK_SIZE) ? 1011 data->len : DMA_BLOCK_SIZE); 1012 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1013 BUS_DMASYNC_PREWRITE); 1014 } 1015 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1016 /* Interrupt aggregation: Mask border interrupt 1017 * for the last page and unmask else. */ 1018 if (data->len == DMA_BLOCK_SIZE) 1019 slot->intmask &= ~SDHCI_INT_DMA_END; 1020 else 1021 slot->intmask |= SDHCI_INT_DMA_END; 1022 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1023 } 1024 /* Current data offset for both PIO and DMA. */ 1025 slot->offset = 0; 1026 /* Set block size and request IRQ on 4K border. */ 1027 WR2(slot, SDHCI_BLOCK_SIZE, 1028 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 1029 /* Set block count. */ 1030 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1031 } 1032 1033 void 1034 sdhci_finish_data(struct sdhci_slot *slot) 1035 { 1036 struct mmc_data *data = slot->curcmd->data; 1037 1038 /* Interrupt aggregation: Restore command interrupt. 1039 * Auxiliary restore point for the case when data interrupt 1040 * happened first. */ 1041 if (!slot->cmd_done) { 1042 WR4(slot, SDHCI_SIGNAL_ENABLE, 1043 slot->intmask |= SDHCI_INT_RESPONSE); 1044 } 1045 /* Unload rest of data from DMA buffer. */ 1046 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) { 1047 if (data->flags & MMC_DATA_READ) { 1048 size_t left = data->len - slot->offset; 1049 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1050 BUS_DMASYNC_POSTREAD); 1051 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1052 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1053 } else 1054 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1055 BUS_DMASYNC_POSTWRITE); 1056 } 1057 slot->data_done = 1; 1058 /* If there was error - reset the host. */ 1059 if (slot->curcmd->error) { 1060 sdhci_reset(slot, SDHCI_RESET_CMD); 1061 sdhci_reset(slot, SDHCI_RESET_DATA); 1062 sdhci_start(slot); 1063 return; 1064 } 1065 /* If we already have command response - finish. */ 1066 if (slot->cmd_done) 1067 sdhci_start(slot); 1068 } 1069 1070 static void 1071 sdhci_start(struct sdhci_slot *slot) 1072 { 1073 struct mmc_request *req; 1074 1075 req = slot->req; 1076 if (req == NULL) 1077 return; 1078 1079 if (!(slot->flags & CMD_STARTED)) { 1080 slot->flags |= CMD_STARTED; 1081 sdhci_start_command(slot, req->cmd); 1082 return; 1083 } 1084 /* We don't need this until using Auto-CMD12 feature 1085 if (!(slot->flags & STOP_STARTED) && req->stop) { 1086 slot->flags |= STOP_STARTED; 1087 sdhci_start_command(slot, req->stop); 1088 return; 1089 } 1090 */ 1091 if (sdhci_debug > 1) 1092 slot_printf(slot, "result: %d\n", req->cmd->error); 1093 if (!req->cmd->error && 1094 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1095 sdhci_reset(slot, SDHCI_RESET_CMD); 1096 sdhci_reset(slot, SDHCI_RESET_DATA); 1097 } 1098 1099 sdhci_req_done(slot); 1100 } 1101 1102 int 1103 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 1104 { 1105 struct sdhci_slot *slot = device_get_ivars(reqdev); 1106 1107 SDHCI_LOCK(slot); 1108 if (slot->req != NULL) { 1109 SDHCI_UNLOCK(slot); 1110 return (EBUSY); 1111 } 1112 if (sdhci_debug > 1) { 1113 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1114 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1115 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1116 (req->cmd->data)?req->cmd->data->flags:0); 1117 } 1118 slot->req = req; 1119 slot->flags = 0; 1120 sdhci_start(slot); 1121 SDHCI_UNLOCK(slot); 1122 if (dumping) { 1123 while (slot->req != NULL) { 1124 sdhci_generic_intr(slot); 1125 DELAY(10); 1126 } 1127 } 1128 return (0); 1129 } 1130 1131 int 1132 sdhci_generic_get_ro(device_t brdev, device_t reqdev) 1133 { 1134 struct sdhci_slot *slot = device_get_ivars(reqdev); 1135 uint32_t val; 1136 1137 SDHCI_LOCK(slot); 1138 val = RD4(slot, SDHCI_PRESENT_STATE); 1139 SDHCI_UNLOCK(slot); 1140 return (!(val & SDHCI_WRITE_PROTECT)); 1141 } 1142 1143 int 1144 sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 1145 { 1146 struct sdhci_slot *slot = device_get_ivars(reqdev); 1147 int err = 0; 1148 1149 SDHCI_LOCK(slot); 1150 while (slot->bus_busy) 1151 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1152 slot->bus_busy++; 1153 /* Activate led. */ 1154 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1155 SDHCI_UNLOCK(slot); 1156 return (err); 1157 } 1158 1159 int 1160 sdhci_generic_release_host(device_t brdev, device_t reqdev) 1161 { 1162 struct sdhci_slot *slot = device_get_ivars(reqdev); 1163 1164 SDHCI_LOCK(slot); 1165 /* Deactivate led. */ 1166 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1167 slot->bus_busy--; 1168 SDHCI_UNLOCK(slot); 1169 wakeup(slot); 1170 return (0); 1171 } 1172 1173 static void 1174 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1175 { 1176 1177 if (!slot->curcmd) { 1178 slot_printf(slot, "Got command interrupt 0x%08x, but " 1179 "there is no active command.\n", intmask); 1180 sdhci_dumpregs(slot); 1181 return; 1182 } 1183 if (intmask & SDHCI_INT_TIMEOUT) 1184 slot->curcmd->error = MMC_ERR_TIMEOUT; 1185 else if (intmask & SDHCI_INT_CRC) 1186 slot->curcmd->error = MMC_ERR_BADCRC; 1187 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1188 slot->curcmd->error = MMC_ERR_FIFO; 1189 1190 sdhci_finish_command(slot); 1191 } 1192 1193 static void 1194 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1195 { 1196 1197 if (!slot->curcmd) { 1198 slot_printf(slot, "Got data interrupt 0x%08x, but " 1199 "there is no active command.\n", intmask); 1200 sdhci_dumpregs(slot); 1201 return; 1202 } 1203 if (slot->curcmd->data == NULL && 1204 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1205 slot_printf(slot, "Got data interrupt 0x%08x, but " 1206 "there is no active data operation.\n", 1207 intmask); 1208 sdhci_dumpregs(slot); 1209 return; 1210 } 1211 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1212 slot->curcmd->error = MMC_ERR_TIMEOUT; 1213 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1214 slot->curcmd->error = MMC_ERR_BADCRC; 1215 if (slot->curcmd->data == NULL && 1216 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1217 SDHCI_INT_DMA_END))) { 1218 slot_printf(slot, "Got data interrupt 0x%08x, but " 1219 "there is busy-only command.\n", intmask); 1220 sdhci_dumpregs(slot); 1221 slot->curcmd->error = MMC_ERR_INVALID; 1222 } 1223 if (slot->curcmd->error) { 1224 /* No need to continue after any error. */ 1225 goto done; 1226 } 1227 1228 /* Handle PIO interrupt. */ 1229 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1230 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1231 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1232 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); 1233 slot->flags |= PLATFORM_DATA_STARTED; 1234 } else 1235 sdhci_transfer_pio(slot); 1236 } 1237 /* Handle DMA border. */ 1238 if (intmask & SDHCI_INT_DMA_END) { 1239 struct mmc_data *data = slot->curcmd->data; 1240 size_t left; 1241 1242 /* Unload DMA buffer... */ 1243 left = data->len - slot->offset; 1244 if (data->flags & MMC_DATA_READ) { 1245 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1246 BUS_DMASYNC_POSTREAD); 1247 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1248 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1249 } else { 1250 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1251 BUS_DMASYNC_POSTWRITE); 1252 } 1253 /* ... and reload it again. */ 1254 slot->offset += DMA_BLOCK_SIZE; 1255 left = data->len - slot->offset; 1256 if (data->flags & MMC_DATA_READ) { 1257 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1258 BUS_DMASYNC_PREREAD); 1259 } else { 1260 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1261 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1262 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1263 BUS_DMASYNC_PREWRITE); 1264 } 1265 /* Interrupt aggregation: Mask border interrupt 1266 * for the last page. */ 1267 if (left == DMA_BLOCK_SIZE) { 1268 slot->intmask &= ~SDHCI_INT_DMA_END; 1269 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1270 } 1271 /* Restart DMA. */ 1272 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1273 } 1274 /* We have got all data. */ 1275 if (intmask & SDHCI_INT_DATA_END) { 1276 if (slot->flags & PLATFORM_DATA_STARTED) { 1277 slot->flags &= ~PLATFORM_DATA_STARTED; 1278 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1279 } else 1280 sdhci_finish_data(slot); 1281 } 1282 done: 1283 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1284 if (slot->flags & PLATFORM_DATA_STARTED) { 1285 slot->flags &= ~PLATFORM_DATA_STARTED; 1286 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1287 } else 1288 sdhci_finish_data(slot); 1289 return; 1290 } 1291 } 1292 1293 static void 1294 sdhci_acmd_irq(struct sdhci_slot *slot) 1295 { 1296 uint16_t err; 1297 1298 err = RD4(slot, SDHCI_ACMD12_ERR); 1299 if (!slot->curcmd) { 1300 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1301 "there is no active command.\n", err); 1302 sdhci_dumpregs(slot); 1303 return; 1304 } 1305 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1306 sdhci_reset(slot, SDHCI_RESET_CMD); 1307 } 1308 1309 void 1310 sdhci_generic_intr(struct sdhci_slot *slot) 1311 { 1312 uint32_t intmask; 1313 1314 SDHCI_LOCK(slot); 1315 /* Read slot interrupt status. */ 1316 intmask = RD4(slot, SDHCI_INT_STATUS); 1317 if (intmask == 0 || intmask == 0xffffffff) { 1318 SDHCI_UNLOCK(slot); 1319 return; 1320 } 1321 if (sdhci_debug > 2) 1322 slot_printf(slot, "Interrupt %#x\n", intmask); 1323 1324 /* Handle card presence interrupts. */ 1325 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1326 WR4(slot, SDHCI_INT_STATUS, intmask & 1327 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1328 1329 if (intmask & SDHCI_INT_CARD_REMOVE) { 1330 if (bootverbose || sdhci_debug) 1331 slot_printf(slot, "Card removed\n"); 1332 callout_stop(&slot->card_callout); 1333 taskqueue_enqueue(taskqueue_swi_giant, 1334 &slot->card_task); 1335 } 1336 if (intmask & SDHCI_INT_CARD_INSERT) { 1337 if (bootverbose || sdhci_debug) 1338 slot_printf(slot, "Card inserted\n"); 1339 callout_reset(&slot->card_callout, hz / 2, 1340 sdhci_card_delay, slot); 1341 } 1342 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1343 } 1344 /* Handle command interrupts. */ 1345 if (intmask & SDHCI_INT_CMD_MASK) { 1346 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1347 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1348 } 1349 /* Handle data interrupts. */ 1350 if (intmask & SDHCI_INT_DATA_MASK) { 1351 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1352 /* Dont call data_irq in case of errored command */ 1353 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1354 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1355 } 1356 /* Handle AutoCMD12 error interrupt. */ 1357 if (intmask & SDHCI_INT_ACMD12ERR) { 1358 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1359 sdhci_acmd_irq(slot); 1360 } 1361 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1362 intmask &= ~SDHCI_INT_ACMD12ERR; 1363 intmask &= ~SDHCI_INT_ERROR; 1364 /* Handle bus power interrupt. */ 1365 if (intmask & SDHCI_INT_BUS_POWER) { 1366 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1367 slot_printf(slot, 1368 "Card is consuming too much power!\n"); 1369 intmask &= ~SDHCI_INT_BUS_POWER; 1370 } 1371 /* The rest is unknown. */ 1372 if (intmask) { 1373 WR4(slot, SDHCI_INT_STATUS, intmask); 1374 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1375 intmask); 1376 sdhci_dumpregs(slot); 1377 } 1378 1379 SDHCI_UNLOCK(slot); 1380 } 1381 1382 int 1383 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1384 { 1385 struct sdhci_slot *slot = device_get_ivars(child); 1386 1387 switch (which) { 1388 default: 1389 return (EINVAL); 1390 case MMCBR_IVAR_BUS_MODE: 1391 *result = slot->host.ios.bus_mode; 1392 break; 1393 case MMCBR_IVAR_BUS_WIDTH: 1394 *result = slot->host.ios.bus_width; 1395 break; 1396 case MMCBR_IVAR_CHIP_SELECT: 1397 *result = slot->host.ios.chip_select; 1398 break; 1399 case MMCBR_IVAR_CLOCK: 1400 *result = slot->host.ios.clock; 1401 break; 1402 case MMCBR_IVAR_F_MIN: 1403 *result = slot->host.f_min; 1404 break; 1405 case MMCBR_IVAR_F_MAX: 1406 *result = slot->host.f_max; 1407 break; 1408 case MMCBR_IVAR_HOST_OCR: 1409 *result = slot->host.host_ocr; 1410 break; 1411 case MMCBR_IVAR_MODE: 1412 *result = slot->host.mode; 1413 break; 1414 case MMCBR_IVAR_OCR: 1415 *result = slot->host.ocr; 1416 break; 1417 case MMCBR_IVAR_POWER_MODE: 1418 *result = slot->host.ios.power_mode; 1419 break; 1420 case MMCBR_IVAR_VDD: 1421 *result = slot->host.ios.vdd; 1422 break; 1423 case MMCBR_IVAR_CAPS: 1424 *result = slot->host.caps; 1425 break; 1426 case MMCBR_IVAR_TIMING: 1427 *result = slot->host.ios.timing; 1428 break; 1429 case MMCBR_IVAR_MAX_DATA: 1430 *result = 65535; 1431 break; 1432 } 1433 return (0); 1434 } 1435 1436 int 1437 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1438 { 1439 struct sdhci_slot *slot = device_get_ivars(child); 1440 1441 switch (which) { 1442 default: 1443 return (EINVAL); 1444 case MMCBR_IVAR_BUS_MODE: 1445 slot->host.ios.bus_mode = value; 1446 break; 1447 case MMCBR_IVAR_BUS_WIDTH: 1448 slot->host.ios.bus_width = value; 1449 break; 1450 case MMCBR_IVAR_CHIP_SELECT: 1451 slot->host.ios.chip_select = value; 1452 break; 1453 case MMCBR_IVAR_CLOCK: 1454 if (value > 0) { 1455 uint32_t max_clock; 1456 uint32_t clock; 1457 int i; 1458 1459 max_clock = slot->max_clk; 1460 clock = max_clock; 1461 1462 if (slot->version < SDHCI_SPEC_300) { 1463 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1464 i <<= 1) { 1465 if (clock <= value) 1466 break; 1467 clock >>= 1; 1468 } 1469 } 1470 else { 1471 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1472 i += 2) { 1473 if (clock <= value) 1474 break; 1475 clock = max_clock / (i + 2); 1476 } 1477 } 1478 1479 slot->host.ios.clock = clock; 1480 } else 1481 slot->host.ios.clock = 0; 1482 break; 1483 case MMCBR_IVAR_MODE: 1484 slot->host.mode = value; 1485 break; 1486 case MMCBR_IVAR_OCR: 1487 slot->host.ocr = value; 1488 break; 1489 case MMCBR_IVAR_POWER_MODE: 1490 slot->host.ios.power_mode = value; 1491 break; 1492 case MMCBR_IVAR_VDD: 1493 slot->host.ios.vdd = value; 1494 break; 1495 case MMCBR_IVAR_TIMING: 1496 slot->host.ios.timing = value; 1497 break; 1498 case MMCBR_IVAR_CAPS: 1499 case MMCBR_IVAR_HOST_OCR: 1500 case MMCBR_IVAR_F_MIN: 1501 case MMCBR_IVAR_F_MAX: 1502 case MMCBR_IVAR_MAX_DATA: 1503 return (EINVAL); 1504 } 1505 return (0); 1506 } 1507 1508 MODULE_VERSION(sdhci, 1); 1509