1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/callout.h> 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/kobj.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/stdarg.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcreg.h> 52 #include <dev/mmc/mmcbrvar.h> 53 54 #include <dev/sdhci/sdhci.h> 55 56 #include <cam/cam.h> 57 #include <cam/cam_ccb.h> 58 #include <cam/cam_debug.h> 59 #include <cam/cam_sim.h> 60 #include <cam/cam_xpt_sim.h> 61 62 #include "mmcbr_if.h" 63 #include "sdhci_if.h" 64 65 #include "opt_mmccam.h" 66 67 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 68 69 static int sdhci_debug = 0; 70 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 71 "Debug level"); 72 u_int sdhci_quirk_clear = 0; 73 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 74 0, "Mask of quirks to clear"); 75 u_int sdhci_quirk_set = 0; 76 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 77 "Mask of quirks to set"); 78 79 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 80 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 81 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 82 #define RD_MULTI_4(slot, off, ptr, count) \ 83 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 84 85 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 86 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 87 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 88 #define WR_MULTI_4(slot, off, ptr, count) \ 89 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 90 91 static void sdhci_card_poll(void *arg); 92 static void sdhci_card_task(void *arg, int pending); 93 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); 94 static void sdhci_req_wakeup(struct mmc_request *req); 95 static void sdhci_retune(void *arg); 96 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 97 static void sdhci_start(struct sdhci_slot *slot); 98 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 99 100 #ifdef MMCCAM 101 /* CAM-related */ 102 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock); 103 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 104 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 105 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 106 static void sdhci_cam_poll(struct cam_sim *sim); 107 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 108 #endif 109 110 /* helper routines */ 111 static void sdhci_dumpregs(struct sdhci_slot *slot); 112 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 113 __printflike(2, 3); 114 static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot); 115 116 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 117 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 118 #define SDHCI_LOCK_INIT(_slot) \ 119 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 120 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 121 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 122 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 123 124 #define SDHCI_DEFAULT_MAX_FREQ 50 125 126 #define SDHCI_200_MAX_DIVIDER 256 127 #define SDHCI_300_MAX_DIVIDER 2046 128 129 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 130 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 131 132 /* 133 * Broadcom BCM577xx Controller Constants 134 */ 135 /* Maximum divider supported by the default clock source. */ 136 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 137 /* Alternative clock's base frequency. */ 138 #define BCM577XX_ALT_CLOCK_BASE 63000000 139 140 #define BCM577XX_HOST_CONTROL 0x198 141 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 142 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 143 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 144 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 145 146 static void 147 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 148 { 149 150 if (error != 0) { 151 printf("getaddr: error %d\n", error); 152 return; 153 } 154 *(bus_addr_t *)arg = segs[0].ds_addr; 155 } 156 157 static int 158 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 159 { 160 va_list ap; 161 int retval; 162 163 retval = printf("%s-slot%d: ", 164 device_get_nameunit(slot->bus), slot->num); 165 166 va_start(ap, fmt); 167 retval += vprintf(fmt, ap); 168 va_end(ap); 169 return (retval); 170 } 171 172 static void 173 sdhci_dumpregs(struct sdhci_slot *slot) 174 { 175 176 slot_printf(slot, 177 "============== REGISTER DUMP ==============\n"); 178 179 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 180 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 181 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 182 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 183 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 184 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 185 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 186 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 187 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 188 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 189 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 190 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 191 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 192 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 193 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 194 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 195 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", 196 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 197 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 198 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 199 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 200 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 201 slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n", 202 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 203 204 slot_printf(slot, 205 "===========================================\n"); 206 } 207 208 static void 209 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 210 { 211 int timeout; 212 uint32_t clock; 213 214 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 215 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 216 return; 217 } 218 219 /* Some controllers need this kick or reset won't work. */ 220 if ((mask & SDHCI_RESET_ALL) == 0 && 221 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 222 /* This is to force an update */ 223 clock = slot->clock; 224 slot->clock = 0; 225 sdhci_set_clock(slot, clock); 226 } 227 228 if (mask & SDHCI_RESET_ALL) { 229 slot->clock = 0; 230 slot->power = 0; 231 } 232 233 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 234 235 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 236 /* 237 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 238 * specification. The reset bit has internal propagation delay, 239 * so a fast read after write returns 0 even if reset process is 240 * in progress. The workaround is to poll for 1 before polling 241 * for 0. In the worst case, if we miss seeing it asserted the 242 * time we spent waiting is enough to ensure the reset finishes. 243 */ 244 timeout = 10000; 245 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 246 if (timeout <= 0) 247 break; 248 timeout--; 249 DELAY(1); 250 } 251 } 252 253 /* Wait max 100 ms */ 254 timeout = 10000; 255 /* Controller clears the bits when it's done */ 256 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 257 if (timeout <= 0) { 258 slot_printf(slot, "Reset 0x%x never completed.\n", 259 mask); 260 sdhci_dumpregs(slot); 261 return; 262 } 263 timeout--; 264 DELAY(10); 265 } 266 } 267 268 static uint32_t 269 sdhci_tuning_intmask(struct sdhci_slot *slot) 270 { 271 uint32_t intmask; 272 273 intmask = 0; 274 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 275 intmask |= SDHCI_INT_TUNEERR; 276 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || 277 slot->retune_mode == SDHCI_RETUNE_MODE_3) 278 intmask |= SDHCI_INT_RETUNE; 279 } 280 return (intmask); 281 } 282 283 static void 284 sdhci_init(struct sdhci_slot *slot) 285 { 286 287 sdhci_reset(slot, SDHCI_RESET_ALL); 288 289 /* Enable interrupts. */ 290 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 291 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 292 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 293 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 294 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 295 SDHCI_INT_ACMD12ERR; 296 297 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 298 !(slot->opt & SDHCI_NON_REMOVABLE)) { 299 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 300 } 301 302 WR4(slot, SDHCI_INT_ENABLE, slot->intmask | sdhci_tuning_intmask(slot)); 303 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 304 } 305 306 static void 307 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 308 { 309 uint32_t clk_base; 310 uint32_t clk_sel; 311 uint32_t res; 312 uint16_t clk; 313 uint16_t div; 314 int timeout; 315 316 if (clock == slot->clock) 317 return; 318 slot->clock = clock; 319 320 /* Turn off the clock. */ 321 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 322 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 323 /* If no clock requested - leave it so. */ 324 if (clock == 0) 325 return; 326 327 /* Determine the clock base frequency */ 328 clk_base = slot->max_clk; 329 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 330 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 331 BCM577XX_CTRL_CLKSEL_MASK; 332 333 /* 334 * Select clock source appropriate for the requested frequency. 335 */ 336 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 337 clk_base = BCM577XX_ALT_CLOCK_BASE; 338 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 339 BCM577XX_CTRL_CLKSEL_SHIFT); 340 } else { 341 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 342 BCM577XX_CTRL_CLKSEL_SHIFT); 343 } 344 345 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 346 } 347 348 /* Recalculate timeout clock frequency based on the new sd clock. */ 349 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 350 slot->timeout_clk = slot->clock / 1000; 351 352 if (slot->version < SDHCI_SPEC_300) { 353 /* Looking for highest freq <= clock. */ 354 res = clk_base; 355 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 356 if (res <= clock) 357 break; 358 res >>= 1; 359 } 360 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 361 div >>= 1; 362 } else { 363 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 364 if (clock >= clk_base) 365 div = 0; 366 else { 367 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 368 if ((clk_base / div) <= clock) 369 break; 370 } 371 } 372 div >>= 1; 373 } 374 375 if (bootverbose || sdhci_debug) 376 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 377 div, clock, clk_base); 378 379 /* Now we have got divider, set it. */ 380 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 381 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 382 << SDHCI_DIVIDER_HI_SHIFT; 383 384 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 385 /* Enable clock. */ 386 clk |= SDHCI_CLOCK_INT_EN; 387 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 388 /* Wait up to 10 ms until it stabilize. */ 389 timeout = 10; 390 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 391 & SDHCI_CLOCK_INT_STABLE)) { 392 if (timeout == 0) { 393 slot_printf(slot, 394 "Internal clock never stabilised.\n"); 395 sdhci_dumpregs(slot); 396 return; 397 } 398 timeout--; 399 DELAY(1000); 400 } 401 /* Pass clock signal to the bus. */ 402 clk |= SDHCI_CLOCK_CARD_EN; 403 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 404 } 405 406 static void 407 sdhci_set_power(struct sdhci_slot *slot, u_char power) 408 { 409 int i; 410 uint8_t pwr; 411 412 if (slot->power == power) 413 return; 414 415 slot->power = power; 416 417 /* Turn off the power. */ 418 pwr = 0; 419 WR1(slot, SDHCI_POWER_CONTROL, pwr); 420 /* If power down requested - leave it so. */ 421 if (power == 0) 422 return; 423 /* Set voltage. */ 424 switch (1 << power) { 425 case MMC_OCR_LOW_VOLTAGE: 426 pwr |= SDHCI_POWER_180; 427 break; 428 case MMC_OCR_290_300: 429 case MMC_OCR_300_310: 430 pwr |= SDHCI_POWER_300; 431 break; 432 case MMC_OCR_320_330: 433 case MMC_OCR_330_340: 434 pwr |= SDHCI_POWER_330; 435 break; 436 } 437 WR1(slot, SDHCI_POWER_CONTROL, pwr); 438 /* 439 * Turn on VDD1 power. Note that at least some Intel controllers can 440 * fail to enable bus power on the first try after transiting from D3 441 * to D0, so we give them up to 2 ms. 442 */ 443 pwr |= SDHCI_POWER_ON; 444 for (i = 0; i < 20; i++) { 445 WR1(slot, SDHCI_POWER_CONTROL, pwr); 446 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 447 break; 448 DELAY(100); 449 } 450 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 451 slot_printf(slot, "Bus power failed to enable"); 452 453 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 454 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 455 DELAY(10); 456 WR1(slot, SDHCI_POWER_CONTROL, pwr); 457 DELAY(300); 458 } 459 } 460 461 static void 462 sdhci_read_block_pio(struct sdhci_slot *slot) 463 { 464 uint32_t data; 465 char *buffer; 466 size_t left; 467 468 buffer = slot->curcmd->data->data; 469 buffer += slot->offset; 470 /* Transfer one block at a time. */ 471 left = min(512, slot->curcmd->data->len - slot->offset); 472 slot->offset += left; 473 474 /* If we are too fast, broken controllers return zeroes. */ 475 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 476 DELAY(10); 477 /* Handle unaligned and aligned buffer cases. */ 478 if ((intptr_t)buffer & 3) { 479 while (left > 3) { 480 data = RD4(slot, SDHCI_BUFFER); 481 buffer[0] = data; 482 buffer[1] = (data >> 8); 483 buffer[2] = (data >> 16); 484 buffer[3] = (data >> 24); 485 buffer += 4; 486 left -= 4; 487 } 488 } else { 489 RD_MULTI_4(slot, SDHCI_BUFFER, 490 (uint32_t *)buffer, left >> 2); 491 left &= 3; 492 } 493 /* Handle uneven size case. */ 494 if (left > 0) { 495 data = RD4(slot, SDHCI_BUFFER); 496 while (left > 0) { 497 *(buffer++) = data; 498 data >>= 8; 499 left--; 500 } 501 } 502 } 503 504 static void 505 sdhci_write_block_pio(struct sdhci_slot *slot) 506 { 507 uint32_t data = 0; 508 char *buffer; 509 size_t left; 510 511 buffer = slot->curcmd->data->data; 512 buffer += slot->offset; 513 /* Transfer one block at a time. */ 514 left = min(512, slot->curcmd->data->len - slot->offset); 515 slot->offset += left; 516 517 /* Handle unaligned and aligned buffer cases. */ 518 if ((intptr_t)buffer & 3) { 519 while (left > 3) { 520 data = buffer[0] + 521 (buffer[1] << 8) + 522 (buffer[2] << 16) + 523 (buffer[3] << 24); 524 left -= 4; 525 buffer += 4; 526 WR4(slot, SDHCI_BUFFER, data); 527 } 528 } else { 529 WR_MULTI_4(slot, SDHCI_BUFFER, 530 (uint32_t *)buffer, left >> 2); 531 left &= 3; 532 } 533 /* Handle uneven size case. */ 534 if (left > 0) { 535 while (left > 0) { 536 data <<= 8; 537 data += *(buffer++); 538 left--; 539 } 540 WR4(slot, SDHCI_BUFFER, data); 541 } 542 } 543 544 static void 545 sdhci_transfer_pio(struct sdhci_slot *slot) 546 { 547 548 /* Read as many blocks as possible. */ 549 if (slot->curcmd->data->flags & MMC_DATA_READ) { 550 while (RD4(slot, SDHCI_PRESENT_STATE) & 551 SDHCI_DATA_AVAILABLE) { 552 sdhci_read_block_pio(slot); 553 if (slot->offset >= slot->curcmd->data->len) 554 break; 555 } 556 } else { 557 while (RD4(slot, SDHCI_PRESENT_STATE) & 558 SDHCI_SPACE_AVAILABLE) { 559 sdhci_write_block_pio(slot); 560 if (slot->offset >= slot->curcmd->data->len) 561 break; 562 } 563 } 564 } 565 566 static void 567 sdhci_card_task(void *arg, int pending __unused) 568 { 569 struct sdhci_slot *slot = arg; 570 device_t d; 571 572 SDHCI_LOCK(slot); 573 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 574 #ifdef MMCCAM 575 if (slot->card_present == 0) { 576 #else 577 if (slot->dev == NULL) { 578 #endif 579 /* If card is present - attach mmc bus. */ 580 if (bootverbose || sdhci_debug) 581 slot_printf(slot, "Card inserted\n"); 582 #ifdef MMCCAM 583 slot->card_present = 1; 584 union ccb *ccb; 585 uint32_t pathid; 586 pathid = cam_sim_path(slot->sim); 587 ccb = xpt_alloc_ccb_nowait(); 588 if (ccb == NULL) { 589 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 590 SDHCI_UNLOCK(slot); 591 return; 592 } 593 594 /* 595 * We create a rescan request for BUS:0:0, since the card 596 * will be at lun 0. 597 */ 598 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 599 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 600 slot_printf(slot, "Unable to create path for rescan\n"); 601 SDHCI_UNLOCK(slot); 602 xpt_free_ccb(ccb); 603 return; 604 } 605 SDHCI_UNLOCK(slot); 606 xpt_rescan(ccb); 607 #else 608 d = slot->dev = device_add_child(slot->bus, "mmc", -1); 609 SDHCI_UNLOCK(slot); 610 if (d) { 611 device_set_ivars(d, slot); 612 (void)device_probe_and_attach(d); 613 } 614 #endif 615 } else 616 SDHCI_UNLOCK(slot); 617 } else { 618 #ifdef MMCCAM 619 if (slot->card_present == 1) { 620 #else 621 if (slot->dev != NULL) { 622 #endif 623 /* If no card present - detach mmc bus. */ 624 if (bootverbose || sdhci_debug) 625 slot_printf(slot, "Card removed\n"); 626 d = slot->dev; 627 slot->dev = NULL; 628 #ifdef MMCCAM 629 slot->card_present = 0; 630 union ccb *ccb; 631 uint32_t pathid; 632 pathid = cam_sim_path(slot->sim); 633 ccb = xpt_alloc_ccb_nowait(); 634 if (ccb == NULL) { 635 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 636 SDHCI_UNLOCK(slot); 637 return; 638 } 639 640 /* 641 * We create a rescan request for BUS:0:0, since the card 642 * will be at lun 0. 643 */ 644 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 645 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 646 slot_printf(slot, "Unable to create path for rescan\n"); 647 SDHCI_UNLOCK(slot); 648 xpt_free_ccb(ccb); 649 return; 650 } 651 SDHCI_UNLOCK(slot); 652 xpt_rescan(ccb); 653 #else 654 slot->intmask &= ~sdhci_tuning_intmask(slot); 655 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 656 slot->opt &= ~SDHCI_TUNING_ENABLED; 657 SDHCI_UNLOCK(slot); 658 callout_drain(&slot->retune_callout); 659 device_delete_child(slot->bus, d); 660 #endif 661 } else 662 SDHCI_UNLOCK(slot); 663 } 664 } 665 666 static void 667 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 668 { 669 bool was_present; 670 671 /* 672 * If there was no card and now there is one, schedule the task to 673 * create the child device after a short delay. The delay is to 674 * debounce the card insert (sometimes the card detect pin stabilizes 675 * before the other pins have made good contact). 676 * 677 * If there was a card present and now it's gone, immediately schedule 678 * the task to delete the child device. No debouncing -- gone is gone, 679 * because once power is removed, a full card re-init is needed, and 680 * that happens by deleting and recreating the child device. 681 */ 682 #ifdef MMCCAM 683 was_present = slot->card_present; 684 #else 685 was_present = slot->dev != NULL; 686 #endif 687 if (!was_present && is_present) { 688 taskqueue_enqueue_timeout(taskqueue_swi_giant, 689 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 690 } else if (was_present && !is_present) { 691 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 692 } 693 } 694 695 void 696 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 697 { 698 699 SDHCI_LOCK(slot); 700 sdhci_handle_card_present_locked(slot, is_present); 701 SDHCI_UNLOCK(slot); 702 } 703 704 static void 705 sdhci_card_poll(void *arg) 706 { 707 struct sdhci_slot *slot = arg; 708 709 sdhci_handle_card_present(slot, 710 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 711 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 712 sdhci_card_poll, slot); 713 } 714 715 int 716 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 717 { 718 kobjop_desc_t kobj_desc; 719 kobj_method_t *kobj_method; 720 uint32_t caps, caps2, freq, host_caps; 721 int err; 722 723 SDHCI_LOCK_INIT(slot); 724 725 slot->num = num; 726 slot->bus = dev; 727 728 /* Allocate DMA tag. */ 729 err = bus_dma_tag_create(bus_get_dma_tag(dev), 730 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 731 BUS_SPACE_MAXADDR, NULL, NULL, 732 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 733 BUS_DMA_ALLOCNOW, NULL, NULL, 734 &slot->dmatag); 735 if (err != 0) { 736 device_printf(dev, "Can't create DMA tag\n"); 737 SDHCI_LOCK_DESTROY(slot); 738 return (err); 739 } 740 /* Allocate DMA memory. */ 741 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 742 BUS_DMA_NOWAIT, &slot->dmamap); 743 if (err != 0) { 744 device_printf(dev, "Can't alloc DMA memory\n"); 745 bus_dma_tag_destroy(slot->dmatag); 746 SDHCI_LOCK_DESTROY(slot); 747 return (err); 748 } 749 /* Map the memory. */ 750 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 751 (void *)slot->dmamem, DMA_BLOCK_SIZE, 752 sdhci_getaddr, &slot->paddr, 0); 753 if (err != 0 || slot->paddr == 0) { 754 device_printf(dev, "Can't load DMA memory\n"); 755 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 756 bus_dma_tag_destroy(slot->dmatag); 757 SDHCI_LOCK_DESTROY(slot); 758 if (err) 759 return (err); 760 else 761 return (EFAULT); 762 } 763 764 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 765 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 766 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 767 caps = slot->caps; 768 caps2 = slot->caps2; 769 } else { 770 caps = RD4(slot, SDHCI_CAPABILITIES); 771 if (slot->version >= SDHCI_SPEC_300) 772 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 773 else 774 caps2 = 0; 775 } 776 if (slot->version >= SDHCI_SPEC_300) { 777 if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && 778 (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { 779 device_printf(dev, 780 "Driver doesn't support shared bus slots\n"); 781 bus_dmamap_unload(slot->dmatag, slot->dmamap); 782 bus_dmamem_free(slot->dmatag, slot->dmamem, 783 slot->dmamap); 784 bus_dma_tag_destroy(slot->dmatag); 785 SDHCI_LOCK_DESTROY(slot); 786 return (ENXIO); 787 } else if ((caps & SDHCI_SLOTTYPE_MASK) == 788 SDHCI_SLOTTYPE_EMBEDDED) { 789 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; 790 } 791 } 792 /* Calculate base clock frequency. */ 793 if (slot->version >= SDHCI_SPEC_300) 794 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 795 SDHCI_CLOCK_BASE_SHIFT; 796 else 797 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 798 SDHCI_CLOCK_BASE_SHIFT; 799 if (freq != 0) 800 slot->max_clk = freq * 1000000; 801 /* 802 * If the frequency wasn't in the capabilities and the hardware driver 803 * hasn't already set max_clk we're probably not going to work right 804 * with an assumption, so complain about it. 805 */ 806 if (slot->max_clk == 0) { 807 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 808 device_printf(dev, "Hardware doesn't specify base clock " 809 "frequency, using %dMHz as default.\n", 810 SDHCI_DEFAULT_MAX_FREQ); 811 } 812 /* Calculate/set timeout clock frequency. */ 813 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 814 slot->timeout_clk = slot->max_clk / 1000; 815 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 816 slot->timeout_clk = 1000; 817 } else { 818 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 819 SDHCI_TIMEOUT_CLK_SHIFT; 820 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 821 slot->timeout_clk *= 1000; 822 } 823 /* 824 * If the frequency wasn't in the capabilities and the hardware driver 825 * hasn't already set timeout_clk we'll probably work okay using the 826 * max timeout, but still mention it. 827 */ 828 if (slot->timeout_clk == 0) { 829 device_printf(dev, "Hardware doesn't specify timeout clock " 830 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 831 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 832 } 833 834 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 835 slot->host.f_max = slot->max_clk; 836 slot->host.host_ocr = 0; 837 if (caps & SDHCI_CAN_VDD_330) 838 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 839 if (caps & SDHCI_CAN_VDD_300) 840 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 841 /* 1.8V VDD is not supposed to be used for removable cards. */ 842 if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) 843 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 844 if (slot->host.host_ocr == 0) { 845 device_printf(dev, "Hardware doesn't report any " 846 "support voltages.\n"); 847 } 848 849 host_caps = MMC_CAP_4_BIT_DATA; 850 if (caps & SDHCI_CAN_DO_8BITBUS) 851 host_caps |= MMC_CAP_8_BIT_DATA; 852 if (caps & SDHCI_CAN_DO_HISPD) 853 host_caps |= MMC_CAP_HSPEED; 854 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 855 host_caps |= MMC_CAP_BOOT_NOACC; 856 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 857 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 858 859 /* Determine supported UHS-I and eMMC modes. */ 860 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 861 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 862 if (caps2 & SDHCI_CAN_SDR104) { 863 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 864 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 865 host_caps |= MMC_CAP_MMC_HS200; 866 } else if (caps2 & SDHCI_CAN_SDR50) 867 host_caps |= MMC_CAP_UHS_SDR50; 868 if (caps2 & SDHCI_CAN_DDR50 && 869 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 870 host_caps |= MMC_CAP_UHS_DDR50; 871 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 872 host_caps |= MMC_CAP_MMC_DDR52; 873 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 874 caps2 & SDHCI_CAN_MMC_HS400) 875 host_caps |= MMC_CAP_MMC_HS400; 876 877 /* 878 * Disable UHS-I and eMMC modes if the set_uhs_timing method is the 879 * default NULL implementation. 880 */ 881 kobj_desc = &sdhci_set_uhs_timing_desc; 882 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 883 kobj_desc); 884 if (kobj_method == &kobj_desc->deflt) 885 host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 886 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 887 MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); 888 889 #define SDHCI_CAP_MODES_TUNING(caps2) \ 890 (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ 891 MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ 892 MMC_CAP_MMC_HS400) 893 894 /* 895 * Disable UHS-I and eMMC modes that require (re-)tuning if either 896 * the tune or re-tune method is the default NULL implementation. 897 */ 898 kobj_desc = &mmcbr_tune_desc; 899 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 900 kobj_desc); 901 if (kobj_method == &kobj_desc->deflt) 902 goto no_tuning; 903 kobj_desc = &mmcbr_retune_desc; 904 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 905 kobj_desc); 906 if (kobj_method == &kobj_desc->deflt) { 907 no_tuning: 908 host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); 909 } 910 911 /* Allocate tuning structures and determine tuning parameters. */ 912 if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { 913 slot->opt |= SDHCI_TUNING_SUPPORTED; 914 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, 915 M_WAITOK); 916 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, 917 M_WAITOK); 918 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, 919 M_WAITOK); 920 if (caps2 & SDHCI_TUNE_SDR50) 921 slot->opt |= SDHCI_SDR50_NEEDS_TUNING; 922 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> 923 SDHCI_RETUNE_MODES_SHIFT; 924 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { 925 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> 926 SDHCI_RETUNE_CNT_SHIFT; 927 if (slot->retune_count > 0xb) { 928 device_printf(dev, "Unknown re-tuning count " 929 "%x, using 1 sec\n", slot->retune_count); 930 slot->retune_count = 1; 931 } else if (slot->retune_count != 0) 932 slot->retune_count = 933 1 << (slot->retune_count - 1); 934 } 935 } 936 937 #undef SDHCI_CAP_MODES_TUNING 938 939 /* Determine supported VCCQ signaling levels. */ 940 host_caps |= MMC_CAP_SIGNALING_330; 941 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 942 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | 943 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 944 MMC_CAP_MMC_HS400_180)) 945 host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; 946 947 /* 948 * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the 949 * default NULL implementation. Disable 1.2 V support if it's the 950 * generic SDHCI implementation. 951 */ 952 kobj_desc = &mmcbr_switch_vccq_desc; 953 kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, 954 kobj_desc); 955 if (kobj_method == &kobj_desc->deflt) 956 host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); 957 else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) 958 host_caps &= ~MMC_CAP_SIGNALING_120; 959 960 /* Determine supported driver types (type B is always mandatory). */ 961 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 962 host_caps |= MMC_CAP_DRIVER_TYPE_A; 963 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 964 host_caps |= MMC_CAP_DRIVER_TYPE_C; 965 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 966 host_caps |= MMC_CAP_DRIVER_TYPE_D; 967 slot->host.caps = host_caps; 968 969 /* Decide if we have usable DMA. */ 970 if (caps & SDHCI_CAN_DO_DMA) 971 slot->opt |= SDHCI_HAVE_DMA; 972 973 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 974 slot->opt &= ~SDHCI_HAVE_DMA; 975 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 976 slot->opt |= SDHCI_HAVE_DMA; 977 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 978 slot->opt |= SDHCI_NON_REMOVABLE; 979 980 /* 981 * Use platform-provided transfer backend 982 * with PIO as a fallback mechanism 983 */ 984 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 985 slot->opt &= ~SDHCI_HAVE_DMA; 986 987 if (bootverbose || sdhci_debug) { 988 slot_printf(slot, 989 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", 990 slot->max_clk / 1000000, 991 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 992 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 993 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 994 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 995 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 996 ((caps & SDHCI_CAN_VDD_180) && 997 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", 998 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 999 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 1000 (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", 1001 (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", 1002 (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", 1003 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", 1004 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : 1005 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : 1006 "removable"); 1007 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 1008 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 1009 slot_printf(slot, "eMMC:%s%s%s%s\n", 1010 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 1011 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 1012 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 1013 ((host_caps & 1014 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 1015 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 1016 " HS400ES" : ""); 1017 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 1018 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 1019 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 1020 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 1021 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 1022 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 1023 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 1024 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 1025 if (slot->opt & SDHCI_TUNING_SUPPORTED) 1026 slot_printf(slot, "Re-tuning count %d secs, mode %d\n", 1027 slot->retune_count, slot->retune_mode + 1); 1028 sdhci_dumpregs(slot); 1029 } 1030 1031 slot->timeout = 10; 1032 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 1033 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 1034 "timeout", CTLFLAG_RW, &slot->timeout, 0, 1035 "Maximum timeout for SDHCI transfers (in secs)"); 1036 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 1037 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 1038 sdhci_card_task, slot); 1039 callout_init(&slot->card_poll_callout, 1); 1040 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 1041 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); 1042 1043 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 1044 !(slot->opt & SDHCI_NON_REMOVABLE)) { 1045 callout_reset(&slot->card_poll_callout, 1046 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 1047 } 1048 1049 sdhci_init(slot); 1050 1051 return (0); 1052 } 1053 1054 #ifndef MMCCAM 1055 void 1056 sdhci_start_slot(struct sdhci_slot *slot) 1057 { 1058 1059 sdhci_card_task(slot, 0); 1060 } 1061 #endif 1062 1063 int 1064 sdhci_cleanup_slot(struct sdhci_slot *slot) 1065 { 1066 device_t d; 1067 1068 callout_drain(&slot->timeout_callout); 1069 callout_drain(&slot->card_poll_callout); 1070 callout_drain(&slot->retune_callout); 1071 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 1072 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 1073 1074 SDHCI_LOCK(slot); 1075 d = slot->dev; 1076 slot->dev = NULL; 1077 SDHCI_UNLOCK(slot); 1078 if (d != NULL) 1079 device_delete_child(slot->bus, d); 1080 1081 SDHCI_LOCK(slot); 1082 sdhci_reset(slot, SDHCI_RESET_ALL); 1083 SDHCI_UNLOCK(slot); 1084 bus_dmamap_unload(slot->dmatag, slot->dmamap); 1085 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 1086 bus_dma_tag_destroy(slot->dmatag); 1087 if (slot->opt & SDHCI_TUNING_SUPPORTED) { 1088 free(slot->tune_req, M_DEVBUF); 1089 free(slot->tune_cmd, M_DEVBUF); 1090 free(slot->tune_data, M_DEVBUF); 1091 } 1092 1093 SDHCI_LOCK_DESTROY(slot); 1094 1095 return (0); 1096 } 1097 1098 int 1099 sdhci_generic_suspend(struct sdhci_slot *slot) 1100 { 1101 1102 /* 1103 * We expect the MMC layer to issue initial tuning after resume. 1104 * Otherwise, we'd need to indicate re-tuning including circuit reset 1105 * being required at least for re-tuning modes 1 and 2 ourselves. 1106 */ 1107 callout_drain(&slot->retune_callout); 1108 SDHCI_LOCK(slot); 1109 slot->opt &= ~SDHCI_TUNING_ENABLED; 1110 sdhci_reset(slot, SDHCI_RESET_ALL); 1111 SDHCI_UNLOCK(slot); 1112 1113 return (0); 1114 } 1115 1116 int 1117 sdhci_generic_resume(struct sdhci_slot *slot) 1118 { 1119 1120 SDHCI_LOCK(slot); 1121 sdhci_init(slot); 1122 SDHCI_UNLOCK(slot); 1123 1124 return (0); 1125 } 1126 1127 uint32_t 1128 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 1129 { 1130 1131 if (slot->version >= SDHCI_SPEC_300) 1132 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 1133 else 1134 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 1135 } 1136 1137 bool 1138 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 1139 { 1140 1141 if (slot->opt & SDHCI_NON_REMOVABLE) 1142 return true; 1143 1144 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1145 } 1146 1147 void 1148 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 1149 { 1150 struct mmc_ios *ios; 1151 uint16_t hostctrl2; 1152 1153 if (slot->version < SDHCI_SPEC_300) 1154 return; 1155 1156 SDHCI_ASSERT_LOCKED(slot); 1157 ios = &slot->host.ios; 1158 sdhci_set_clock(slot, 0); 1159 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1160 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 1161 if (ios->clock > SD_SDR50_MAX) { 1162 if (ios->timing == bus_timing_mmc_hs400 || 1163 ios->timing == bus_timing_mmc_hs400es) 1164 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1165 else 1166 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1167 } 1168 else if (ios->clock > SD_SDR25_MAX) 1169 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1170 else if (ios->clock > SD_SDR12_MAX) { 1171 if (ios->timing == bus_timing_uhs_ddr50 || 1172 ios->timing == bus_timing_mmc_ddr52) 1173 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1174 else 1175 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1176 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1177 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1178 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1179 sdhci_set_clock(slot, ios->clock); 1180 } 1181 1182 int 1183 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1184 { 1185 struct sdhci_slot *slot = device_get_ivars(reqdev); 1186 struct mmc_ios *ios = &slot->host.ios; 1187 1188 SDHCI_LOCK(slot); 1189 /* Do full reset on bus power down to clear from any state. */ 1190 if (ios->power_mode == power_off) { 1191 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1192 sdhci_init(slot); 1193 } 1194 /* Configure the bus. */ 1195 sdhci_set_clock(slot, ios->clock); 1196 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1197 if (ios->bus_width == bus_width_8) { 1198 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1199 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1200 } else if (ios->bus_width == bus_width_4) { 1201 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1202 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1203 } else if (ios->bus_width == bus_width_1) { 1204 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1205 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1206 } else { 1207 panic("Invalid bus width: %d", ios->bus_width); 1208 } 1209 if (ios->clock > SD_SDR12_MAX && 1210 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1211 slot->hostctrl |= SDHCI_CTRL_HISPD; 1212 else 1213 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1214 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1215 SDHCI_SET_UHS_TIMING(brdev, slot); 1216 /* Some controllers like reset after bus changes. */ 1217 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1218 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1219 1220 SDHCI_UNLOCK(slot); 1221 return (0); 1222 } 1223 1224 int 1225 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1226 { 1227 struct sdhci_slot *slot = device_get_ivars(reqdev); 1228 enum mmc_vccq vccq; 1229 int err; 1230 uint16_t hostctrl2; 1231 1232 if (slot->version < SDHCI_SPEC_300) 1233 return (0); 1234 1235 err = 0; 1236 vccq = slot->host.ios.vccq; 1237 SDHCI_LOCK(slot); 1238 sdhci_set_clock(slot, 0); 1239 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1240 switch (vccq) { 1241 case vccq_330: 1242 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1243 goto done; 1244 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1245 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1246 DELAY(5000); 1247 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1248 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1249 goto done; 1250 err = EAGAIN; 1251 break; 1252 case vccq_180: 1253 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1254 err = EINVAL; 1255 goto done; 1256 } 1257 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1258 goto done; 1259 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1260 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1261 DELAY(5000); 1262 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1263 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1264 goto done; 1265 err = EAGAIN; 1266 break; 1267 default: 1268 slot_printf(slot, 1269 "Attempt to set unsupported signaling voltage\n"); 1270 err = EINVAL; 1271 break; 1272 } 1273 done: 1274 sdhci_set_clock(slot, slot->host.ios.clock); 1275 SDHCI_UNLOCK(slot); 1276 return (err); 1277 } 1278 1279 int 1280 sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) 1281 { 1282 struct sdhci_slot *slot = device_get_ivars(reqdev); 1283 struct mmc_ios *ios = &slot->host.ios; 1284 struct mmc_command *tune_cmd; 1285 struct mmc_data *tune_data; 1286 uint32_t opcode; 1287 int err; 1288 1289 if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) 1290 return (0); 1291 1292 slot->retune_ticks = slot->retune_count * hz; 1293 opcode = MMC_SEND_TUNING_BLOCK; 1294 SDHCI_LOCK(slot); 1295 switch (ios->timing) { 1296 case bus_timing_mmc_hs400: 1297 slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); 1298 SDHCI_UNLOCK(slot); 1299 return (EINVAL); 1300 case bus_timing_mmc_hs200: 1301 /* 1302 * In HS400 mode, controllers use the data strobe line to 1303 * latch data from the devices so periodic re-tuning isn't 1304 * expected to be required. 1305 */ 1306 if (hs400) 1307 slot->retune_ticks = 0; 1308 opcode = MMC_SEND_TUNING_BLOCK_HS200; 1309 break; 1310 case bus_timing_uhs_ddr50: 1311 case bus_timing_uhs_sdr104: 1312 break; 1313 case bus_timing_uhs_sdr50: 1314 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) 1315 break; 1316 /* FALLTHROUGH */ 1317 default: 1318 SDHCI_UNLOCK(slot); 1319 return (0); 1320 } 1321 1322 tune_cmd = slot->tune_cmd; 1323 memset(tune_cmd, 0, sizeof(*tune_cmd)); 1324 tune_cmd->opcode = opcode; 1325 tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1326 tune_data = tune_cmd->data = slot->tune_data; 1327 memset(tune_data, 0, sizeof(*tune_data)); 1328 tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 1329 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : 1330 MMC_TUNING_LEN; 1331 tune_data->flags = MMC_DATA_READ; 1332 tune_data->mrq = tune_cmd->mrq = slot->tune_req; 1333 1334 slot->opt &= ~SDHCI_TUNING_ENABLED; 1335 err = sdhci_exec_tuning(slot, true); 1336 if (err == 0) { 1337 slot->opt |= SDHCI_TUNING_ENABLED; 1338 slot->intmask |= sdhci_tuning_intmask(slot); 1339 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1340 if (slot->retune_ticks) { 1341 callout_reset(&slot->retune_callout, slot->retune_ticks, 1342 sdhci_retune, slot); 1343 } 1344 } 1345 SDHCI_UNLOCK(slot); 1346 return (err); 1347 } 1348 1349 int 1350 sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) 1351 { 1352 struct sdhci_slot *slot = device_get_ivars(reqdev); 1353 int err; 1354 1355 if (!(slot->opt & SDHCI_TUNING_ENABLED)) 1356 return (0); 1357 1358 /* HS400 must be tuned in HS200 mode. */ 1359 if (slot->host.ios.timing == bus_timing_mmc_hs400) 1360 return (EINVAL); 1361 1362 SDHCI_LOCK(slot); 1363 err = sdhci_exec_tuning(slot, reset); 1364 /* 1365 * There are two ways sdhci_exec_tuning() can fail: 1366 * EBUSY should not actually happen when requests are only issued 1367 * with the host properly acquired, and 1368 * EIO re-tuning failed (but it did work initially). 1369 * 1370 * In both cases, we should retry at later point if periodic re-tuning 1371 * is enabled. Note that due to slot->retune_req not being cleared in 1372 * these failure cases, the MMC layer should trigger another attempt at 1373 * re-tuning with the next request anyway, though. 1374 */ 1375 if (slot->retune_ticks) { 1376 callout_reset(&slot->retune_callout, slot->retune_ticks, 1377 sdhci_retune, slot); 1378 } 1379 SDHCI_UNLOCK(slot); 1380 return (err); 1381 } 1382 1383 static int 1384 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) 1385 { 1386 struct mmc_request *tune_req; 1387 struct mmc_command *tune_cmd; 1388 int i; 1389 uint32_t intmask; 1390 uint16_t hostctrl2; 1391 u_char opt; 1392 1393 SDHCI_ASSERT_LOCKED(slot); 1394 if (slot->req != NULL) 1395 return (EBUSY); 1396 1397 /* Tuning doesn't work with DMA enabled. */ 1398 opt = slot->opt; 1399 slot->opt = opt & ~SDHCI_HAVE_DMA; 1400 1401 /* 1402 * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only 1403 * kind of interrupt we receive in response to a tuning request. 1404 */ 1405 intmask = slot->intmask; 1406 slot->intmask = SDHCI_INT_DATA_AVAIL; 1407 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); 1408 1409 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1410 if (reset) 1411 hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; 1412 else 1413 hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; 1414 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); 1415 1416 tune_req = slot->tune_req; 1417 tune_cmd = slot->tune_cmd; 1418 for (i = 0; i < MMC_TUNING_MAX; i++) { 1419 memset(tune_req, 0, sizeof(*tune_req)); 1420 tune_req->cmd = tune_cmd; 1421 tune_req->done = sdhci_req_wakeup; 1422 tune_req->done_data = slot; 1423 slot->req = tune_req; 1424 slot->flags = 0; 1425 sdhci_start(slot); 1426 while (!(tune_req->flags & MMC_REQ_DONE)) 1427 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); 1428 if (!(tune_req->flags & MMC_TUNE_DONE)) 1429 break; 1430 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1431 if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) 1432 break; 1433 if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) 1434 DELAY(1000); 1435 } 1436 1437 slot->opt = opt; 1438 slot->intmask = intmask; 1439 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); 1440 1441 if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | 1442 SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { 1443 slot->retune_req = 0; 1444 return (0); 1445 } 1446 1447 slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); 1448 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | 1449 SDHCI_CTRL2_SAMPLING_CLOCK)); 1450 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1451 return (EIO); 1452 } 1453 1454 static void 1455 sdhci_retune(void *arg) 1456 { 1457 struct sdhci_slot *slot = arg; 1458 1459 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 1460 } 1461 1462 #ifdef MMCCAM 1463 static void 1464 sdhci_req_done(struct sdhci_slot *slot) 1465 { 1466 union ccb *ccb; 1467 1468 if (__predict_false(sdhci_debug > 1)) 1469 slot_printf(slot, "%s\n", __func__); 1470 if (slot->ccb != NULL && slot->curcmd != NULL) { 1471 callout_stop(&slot->timeout_callout); 1472 ccb = slot->ccb; 1473 slot->ccb = NULL; 1474 slot->curcmd = NULL; 1475 1476 /* Tell CAM the request is finished */ 1477 struct ccb_mmcio *mmcio; 1478 mmcio = &ccb->mmcio; 1479 1480 ccb->ccb_h.status = 1481 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1482 xpt_done(ccb); 1483 } 1484 } 1485 #else 1486 static void 1487 sdhci_req_done(struct sdhci_slot *slot) 1488 { 1489 struct mmc_request *req; 1490 1491 if (slot->req != NULL && slot->curcmd != NULL) { 1492 callout_stop(&slot->timeout_callout); 1493 req = slot->req; 1494 slot->req = NULL; 1495 slot->curcmd = NULL; 1496 req->done(req); 1497 } 1498 } 1499 #endif 1500 1501 static void 1502 sdhci_req_wakeup(struct mmc_request *req) 1503 { 1504 struct sdhci_slot *slot; 1505 1506 slot = req->done_data; 1507 req->flags |= MMC_REQ_DONE; 1508 wakeup(req); 1509 } 1510 1511 static void 1512 sdhci_timeout(void *arg) 1513 { 1514 struct sdhci_slot *slot = arg; 1515 1516 if (slot->curcmd != NULL) { 1517 slot_printf(slot, "Controller timeout\n"); 1518 sdhci_dumpregs(slot); 1519 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1520 slot->curcmd->error = MMC_ERR_TIMEOUT; 1521 sdhci_req_done(slot); 1522 } else { 1523 slot_printf(slot, "Spurious timeout - no active command\n"); 1524 } 1525 } 1526 1527 static void 1528 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1529 { 1530 uint16_t mode; 1531 1532 if (data == NULL) 1533 return; 1534 1535 mode = SDHCI_TRNS_BLK_CNT_EN; 1536 if (data->len > 512) 1537 mode |= SDHCI_TRNS_MULTI; 1538 if (data->flags & MMC_DATA_READ) 1539 mode |= SDHCI_TRNS_READ; 1540 #ifdef MMCCAM 1541 struct ccb_mmcio *mmcio; 1542 mmcio = &slot->ccb->mmcio; 1543 if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION 1544 && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1545 mode |= SDHCI_TRNS_ACMD12; 1546 #else 1547 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1548 mode |= SDHCI_TRNS_ACMD12; 1549 #endif 1550 if (slot->flags & SDHCI_USE_DMA) 1551 mode |= SDHCI_TRNS_DMA; 1552 1553 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1554 } 1555 1556 static void 1557 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1558 { 1559 int flags, timeout; 1560 uint32_t mask; 1561 1562 slot->curcmd = cmd; 1563 slot->cmd_done = 0; 1564 1565 cmd->error = MMC_ERR_NONE; 1566 1567 /* This flags combination is not supported by controller. */ 1568 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1569 slot_printf(slot, "Unsupported response type!\n"); 1570 cmd->error = MMC_ERR_FAILED; 1571 sdhci_req_done(slot); 1572 return; 1573 } 1574 1575 /* 1576 * Do not issue command if there is no card, clock or power. 1577 * Controller will not detect timeout without clock active. 1578 */ 1579 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1580 slot->power == 0 || 1581 slot->clock == 0) { 1582 slot_printf(slot, 1583 "Cannot issue a command (power=%d clock=%d)", 1584 slot->power, slot->clock); 1585 cmd->error = MMC_ERR_FAILED; 1586 sdhci_req_done(slot); 1587 return; 1588 } 1589 /* Always wait for free CMD bus. */ 1590 mask = SDHCI_CMD_INHIBIT; 1591 /* Wait for free DAT if we have data or busy signal. */ 1592 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1593 mask |= SDHCI_DAT_INHIBIT; 1594 /* 1595 * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note 1596 * that these latter are also special in that SDHCI_CMD_DATA should 1597 * be set below but no actual data is ever read from the controller. 1598 */ 1599 #ifdef MMCCAM 1600 if (cmd == &slot->ccb->mmcio.stop || 1601 #else 1602 if (cmd == slot->req->stop || 1603 #endif 1604 __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || 1605 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) 1606 mask &= ~SDHCI_DAT_INHIBIT; 1607 /* 1608 * Wait for bus no more then 250 ms. Typically there will be no wait 1609 * here at all, but when writing a crash dump we may be bypassing the 1610 * host platform's interrupt handler, and in some cases that handler 1611 * may be working around hardware quirks such as not respecting r1b 1612 * busy indications. In those cases, this wait-loop serves the purpose 1613 * of waiting for the prior command and data transfers to be done, and 1614 * SD cards are allowed to take up to 250ms for write and erase ops. 1615 * (It's usually more like 20-30ms in the real world.) 1616 */ 1617 timeout = 250; 1618 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1619 if (timeout == 0) { 1620 slot_printf(slot, "Controller never released " 1621 "inhibit bit(s).\n"); 1622 sdhci_dumpregs(slot); 1623 cmd->error = MMC_ERR_FAILED; 1624 sdhci_req_done(slot); 1625 return; 1626 } 1627 timeout--; 1628 DELAY(1000); 1629 } 1630 1631 /* Prepare command flags. */ 1632 if (!(cmd->flags & MMC_RSP_PRESENT)) 1633 flags = SDHCI_CMD_RESP_NONE; 1634 else if (cmd->flags & MMC_RSP_136) 1635 flags = SDHCI_CMD_RESP_LONG; 1636 else if (cmd->flags & MMC_RSP_BUSY) 1637 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1638 else 1639 flags = SDHCI_CMD_RESP_SHORT; 1640 if (cmd->flags & MMC_RSP_CRC) 1641 flags |= SDHCI_CMD_CRC; 1642 if (cmd->flags & MMC_RSP_OPCODE) 1643 flags |= SDHCI_CMD_INDEX; 1644 if (cmd->data != NULL) 1645 flags |= SDHCI_CMD_DATA; 1646 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1647 flags |= SDHCI_CMD_TYPE_ABORT; 1648 /* Prepare data. */ 1649 sdhci_start_data(slot, cmd->data); 1650 /* 1651 * Interrupt aggregation: To reduce total number of interrupts 1652 * group response interrupt with data interrupt when possible. 1653 * If there going to be data interrupt, mask response one. 1654 */ 1655 if (slot->data_done == 0) { 1656 WR4(slot, SDHCI_SIGNAL_ENABLE, 1657 slot->intmask &= ~SDHCI_INT_RESPONSE); 1658 } 1659 /* Set command argument. */ 1660 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1661 /* Set data transfer mode. */ 1662 sdhci_set_transfer_mode(slot, cmd->data); 1663 if (__predict_false(sdhci_debug > 1)) 1664 slot_printf(slot, "Starting command!\n"); 1665 /* Start command. */ 1666 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1667 /* Start timeout callout. */ 1668 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1669 sdhci_timeout, slot); 1670 } 1671 1672 static void 1673 sdhci_finish_command(struct sdhci_slot *slot) 1674 { 1675 int i; 1676 uint32_t val; 1677 uint8_t extra; 1678 1679 if (__predict_false(sdhci_debug > 1)) 1680 slot_printf(slot, "%s: called, err %d flags %d\n", 1681 __func__, slot->curcmd->error, slot->curcmd->flags); 1682 slot->cmd_done = 1; 1683 /* 1684 * Interrupt aggregation: Restore command interrupt. 1685 * Main restore point for the case when command interrupt 1686 * happened first. 1687 */ 1688 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && 1689 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1690 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= 1691 SDHCI_INT_RESPONSE); 1692 /* In case of error - reset host and return. */ 1693 if (slot->curcmd->error) { 1694 if (slot->curcmd->error == MMC_ERR_BADCRC) 1695 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1696 sdhci_reset(slot, SDHCI_RESET_CMD); 1697 sdhci_reset(slot, SDHCI_RESET_DATA); 1698 sdhci_start(slot); 1699 return; 1700 } 1701 /* If command has response - fetch it. */ 1702 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1703 if (slot->curcmd->flags & MMC_RSP_136) { 1704 /* CRC is stripped so we need one byte shift. */ 1705 extra = 0; 1706 for (i = 0; i < 4; i++) { 1707 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1708 if (slot->quirks & 1709 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1710 slot->curcmd->resp[3 - i] = val; 1711 else { 1712 slot->curcmd->resp[3 - i] = 1713 (val << 8) | extra; 1714 extra = val >> 24; 1715 } 1716 } 1717 } else 1718 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1719 } 1720 if (__predict_false(sdhci_debug > 1)) 1721 printf("Resp: %02x %02x %02x %02x\n", 1722 slot->curcmd->resp[0], slot->curcmd->resp[1], 1723 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1724 1725 /* If data ready - finish. */ 1726 if (slot->data_done) 1727 sdhci_start(slot); 1728 } 1729 1730 static void 1731 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1732 { 1733 uint32_t target_timeout, current_timeout; 1734 uint8_t div; 1735 1736 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1737 slot->data_done = 1; 1738 return; 1739 } 1740 1741 slot->data_done = 0; 1742 1743 /* Calculate and set data timeout.*/ 1744 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1745 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1746 div = 0xE; 1747 } else { 1748 target_timeout = 1000000; 1749 div = 0; 1750 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1751 while (current_timeout < target_timeout && div < 0xE) { 1752 ++div; 1753 current_timeout <<= 1; 1754 } 1755 /* Compensate for an off-by-one error in the CaFe chip.*/ 1756 if (div < 0xE && 1757 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1758 ++div; 1759 } 1760 } 1761 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1762 1763 if (data == NULL) 1764 return; 1765 1766 /* Use DMA if possible. */ 1767 if ((slot->opt & SDHCI_HAVE_DMA)) 1768 slot->flags |= SDHCI_USE_DMA; 1769 /* If data is small, broken DMA may return zeroes instead of data, */ 1770 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1771 (data->len <= 512)) 1772 slot->flags &= ~SDHCI_USE_DMA; 1773 /* Some controllers require even block sizes. */ 1774 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1775 ((data->len) & 0x3)) 1776 slot->flags &= ~SDHCI_USE_DMA; 1777 /* Load DMA buffer. */ 1778 if (slot->flags & SDHCI_USE_DMA) { 1779 if (data->flags & MMC_DATA_READ) 1780 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1781 BUS_DMASYNC_PREREAD); 1782 else { 1783 memcpy(slot->dmamem, data->data, 1784 (data->len < DMA_BLOCK_SIZE) ? 1785 data->len : DMA_BLOCK_SIZE); 1786 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1787 BUS_DMASYNC_PREWRITE); 1788 } 1789 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1790 /* Interrupt aggregation: Mask border interrupt 1791 * for the last page and unmask else. */ 1792 if (data->len == DMA_BLOCK_SIZE) 1793 slot->intmask &= ~SDHCI_INT_DMA_END; 1794 else 1795 slot->intmask |= SDHCI_INT_DMA_END; 1796 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1797 } 1798 /* Current data offset for both PIO and DMA. */ 1799 slot->offset = 0; 1800 /* Set block size and request IRQ on 4K border. */ 1801 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1802 (data->len < 512) ? data->len : 512)); 1803 /* Set block count. */ 1804 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1805 1806 if (__predict_false(sdhci_debug > 1)) 1807 slot_printf(slot, "Block size: %02x, count %lu\n", 1808 (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512), 1809 (unsigned long)(data->len + 511) / 512); 1810 } 1811 1812 void 1813 sdhci_finish_data(struct sdhci_slot *slot) 1814 { 1815 struct mmc_data *data = slot->curcmd->data; 1816 size_t left; 1817 1818 /* Interrupt aggregation: Restore command interrupt. 1819 * Auxiliary restore point for the case when data interrupt 1820 * happened first. */ 1821 if (!slot->cmd_done) { 1822 WR4(slot, SDHCI_SIGNAL_ENABLE, 1823 slot->intmask |= SDHCI_INT_RESPONSE); 1824 } 1825 /* Unload rest of data from DMA buffer. */ 1826 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1827 slot->curcmd->data != NULL) { 1828 if (data->flags & MMC_DATA_READ) { 1829 left = data->len - slot->offset; 1830 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1831 BUS_DMASYNC_POSTREAD); 1832 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1833 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1834 } else 1835 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1836 BUS_DMASYNC_POSTWRITE); 1837 } 1838 slot->data_done = 1; 1839 /* If there was error - reset the host. */ 1840 if (slot->curcmd->error) { 1841 if (slot->curcmd->error == MMC_ERR_BADCRC) 1842 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 1843 sdhci_reset(slot, SDHCI_RESET_CMD); 1844 sdhci_reset(slot, SDHCI_RESET_DATA); 1845 sdhci_start(slot); 1846 return; 1847 } 1848 /* If we already have command response - finish. */ 1849 if (slot->cmd_done) 1850 sdhci_start(slot); 1851 } 1852 1853 #ifdef MMCCAM 1854 static void 1855 sdhci_start(struct sdhci_slot *slot) 1856 { 1857 union ccb *ccb; 1858 1859 ccb = slot->ccb; 1860 if (ccb == NULL) 1861 return; 1862 1863 struct ccb_mmcio *mmcio; 1864 mmcio = &ccb->mmcio; 1865 1866 if (!(slot->flags & CMD_STARTED)) { 1867 slot->flags |= CMD_STARTED; 1868 sdhci_start_command(slot, &mmcio->cmd); 1869 return; 1870 } 1871 1872 /* 1873 * Old stack doesn't use this! 1874 * Enabling this code causes significant performance degradation 1875 * and IRQ storms on BBB, Wandboard behaves fine. 1876 * Not using this code does no harm... 1877 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1878 slot->flags |= STOP_STARTED; 1879 sdhci_start_command(slot, &mmcio->stop); 1880 return; 1881 } 1882 */ 1883 if (__predict_false(sdhci_debug > 1)) 1884 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1885 if (mmcio->cmd.error == 0 && 1886 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1887 sdhci_reset(slot, SDHCI_RESET_CMD); 1888 sdhci_reset(slot, SDHCI_RESET_DATA); 1889 } 1890 1891 sdhci_req_done(slot); 1892 } 1893 #else 1894 static void 1895 sdhci_start(struct sdhci_slot *slot) 1896 { 1897 struct mmc_request *req; 1898 1899 req = slot->req; 1900 if (req == NULL) 1901 return; 1902 1903 if (!(slot->flags & CMD_STARTED)) { 1904 slot->flags |= CMD_STARTED; 1905 sdhci_start_command(slot, req->cmd); 1906 return; 1907 } 1908 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1909 !(slot->flags & STOP_STARTED) && req->stop) { 1910 slot->flags |= STOP_STARTED; 1911 sdhci_start_command(slot, req->stop); 1912 return; 1913 } 1914 if (__predict_false(sdhci_debug > 1)) 1915 slot_printf(slot, "result: %d\n", req->cmd->error); 1916 if (!req->cmd->error && 1917 ((slot->curcmd == req->stop && 1918 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1919 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1920 sdhci_reset(slot, SDHCI_RESET_CMD); 1921 sdhci_reset(slot, SDHCI_RESET_DATA); 1922 } 1923 1924 sdhci_req_done(slot); 1925 } 1926 #endif 1927 1928 int 1929 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1930 struct mmc_request *req) 1931 { 1932 struct sdhci_slot *slot = device_get_ivars(reqdev); 1933 1934 SDHCI_LOCK(slot); 1935 if (slot->req != NULL) { 1936 SDHCI_UNLOCK(slot); 1937 return (EBUSY); 1938 } 1939 if (__predict_false(sdhci_debug > 1)) { 1940 slot_printf(slot, 1941 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1942 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1943 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1944 (req->cmd->data)?req->cmd->data->flags:0); 1945 } 1946 slot->req = req; 1947 slot->flags = 0; 1948 sdhci_start(slot); 1949 SDHCI_UNLOCK(slot); 1950 if (dumping) { 1951 while (slot->req != NULL) { 1952 sdhci_generic_intr(slot); 1953 DELAY(10); 1954 } 1955 } 1956 return (0); 1957 } 1958 1959 int 1960 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1961 { 1962 struct sdhci_slot *slot = device_get_ivars(reqdev); 1963 uint32_t val; 1964 1965 SDHCI_LOCK(slot); 1966 val = RD4(slot, SDHCI_PRESENT_STATE); 1967 SDHCI_UNLOCK(slot); 1968 return (!(val & SDHCI_WRITE_PROTECT)); 1969 } 1970 1971 int 1972 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1973 { 1974 struct sdhci_slot *slot = device_get_ivars(reqdev); 1975 int err = 0; 1976 1977 SDHCI_LOCK(slot); 1978 while (slot->bus_busy) 1979 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1980 slot->bus_busy++; 1981 /* Activate led. */ 1982 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1983 SDHCI_UNLOCK(slot); 1984 return (err); 1985 } 1986 1987 int 1988 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1989 { 1990 struct sdhci_slot *slot = device_get_ivars(reqdev); 1991 1992 SDHCI_LOCK(slot); 1993 /* Deactivate led. */ 1994 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1995 slot->bus_busy--; 1996 SDHCI_UNLOCK(slot); 1997 wakeup(slot); 1998 return (0); 1999 } 2000 2001 static void 2002 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 2003 { 2004 2005 if (!slot->curcmd) { 2006 slot_printf(slot, "Got command interrupt 0x%08x, but " 2007 "there is no active command.\n", intmask); 2008 sdhci_dumpregs(slot); 2009 return; 2010 } 2011 if (intmask & SDHCI_INT_TIMEOUT) 2012 slot->curcmd->error = MMC_ERR_TIMEOUT; 2013 else if (intmask & SDHCI_INT_CRC) 2014 slot->curcmd->error = MMC_ERR_BADCRC; 2015 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 2016 slot->curcmd->error = MMC_ERR_FIFO; 2017 2018 sdhci_finish_command(slot); 2019 } 2020 2021 static void 2022 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 2023 { 2024 struct mmc_data *data; 2025 size_t left; 2026 2027 if (!slot->curcmd) { 2028 slot_printf(slot, "Got data interrupt 0x%08x, but " 2029 "there is no active command.\n", intmask); 2030 sdhci_dumpregs(slot); 2031 return; 2032 } 2033 if (slot->curcmd->data == NULL && 2034 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 2035 slot_printf(slot, "Got data interrupt 0x%08x, but " 2036 "there is no active data operation.\n", 2037 intmask); 2038 sdhci_dumpregs(slot); 2039 return; 2040 } 2041 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2042 slot->curcmd->error = MMC_ERR_TIMEOUT; 2043 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 2044 slot->curcmd->error = MMC_ERR_BADCRC; 2045 if (slot->curcmd->data == NULL && 2046 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 2047 SDHCI_INT_DMA_END))) { 2048 slot_printf(slot, "Got data interrupt 0x%08x, but " 2049 "there is busy-only command.\n", intmask); 2050 sdhci_dumpregs(slot); 2051 slot->curcmd->error = MMC_ERR_INVALID; 2052 } 2053 if (slot->curcmd->error) { 2054 /* No need to continue after any error. */ 2055 goto done; 2056 } 2057 2058 /* Handle tuning completion interrupt. */ 2059 if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && 2060 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || 2061 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { 2062 slot->req->flags |= MMC_TUNE_DONE; 2063 sdhci_finish_command(slot); 2064 sdhci_finish_data(slot); 2065 return; 2066 } 2067 /* Handle PIO interrupt. */ 2068 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 2069 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 2070 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 2071 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 2072 &intmask); 2073 slot->flags |= PLATFORM_DATA_STARTED; 2074 } else 2075 sdhci_transfer_pio(slot); 2076 } 2077 /* Handle DMA border. */ 2078 if (intmask & SDHCI_INT_DMA_END) { 2079 data = slot->curcmd->data; 2080 2081 /* Unload DMA buffer ... */ 2082 left = data->len - slot->offset; 2083 if (data->flags & MMC_DATA_READ) { 2084 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2085 BUS_DMASYNC_POSTREAD); 2086 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 2087 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 2088 } else { 2089 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2090 BUS_DMASYNC_POSTWRITE); 2091 } 2092 /* ... and reload it again. */ 2093 slot->offset += DMA_BLOCK_SIZE; 2094 left = data->len - slot->offset; 2095 if (data->flags & MMC_DATA_READ) { 2096 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2097 BUS_DMASYNC_PREREAD); 2098 } else { 2099 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 2100 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 2101 bus_dmamap_sync(slot->dmatag, slot->dmamap, 2102 BUS_DMASYNC_PREWRITE); 2103 } 2104 /* Interrupt aggregation: Mask border interrupt 2105 * for the last page. */ 2106 if (left == DMA_BLOCK_SIZE) { 2107 slot->intmask &= ~SDHCI_INT_DMA_END; 2108 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2109 } 2110 /* Restart DMA. */ 2111 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 2112 } 2113 /* We have got all data. */ 2114 if (intmask & SDHCI_INT_DATA_END) { 2115 if (slot->flags & PLATFORM_DATA_STARTED) { 2116 slot->flags &= ~PLATFORM_DATA_STARTED; 2117 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2118 } else 2119 sdhci_finish_data(slot); 2120 } 2121 done: 2122 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 2123 if (slot->flags & PLATFORM_DATA_STARTED) { 2124 slot->flags &= ~PLATFORM_DATA_STARTED; 2125 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 2126 } else 2127 sdhci_finish_data(slot); 2128 } 2129 } 2130 2131 static void 2132 sdhci_acmd_irq(struct sdhci_slot *slot) 2133 { 2134 uint16_t err; 2135 2136 err = RD4(slot, SDHCI_ACMD12_ERR); 2137 if (!slot->curcmd) { 2138 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 2139 "there is no active command.\n", err); 2140 sdhci_dumpregs(slot); 2141 return; 2142 } 2143 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 2144 sdhci_reset(slot, SDHCI_RESET_CMD); 2145 } 2146 2147 void 2148 sdhci_generic_intr(struct sdhci_slot *slot) 2149 { 2150 uint32_t intmask, present; 2151 2152 SDHCI_LOCK(slot); 2153 /* Read slot interrupt status. */ 2154 intmask = RD4(slot, SDHCI_INT_STATUS); 2155 if (intmask == 0 || intmask == 0xffffffff) { 2156 SDHCI_UNLOCK(slot); 2157 return; 2158 } 2159 if (__predict_false(sdhci_debug > 2)) 2160 slot_printf(slot, "Interrupt %#x\n", intmask); 2161 2162 /* Handle tuning error interrupt. */ 2163 if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { 2164 slot_printf(slot, "Tuning error indicated\n"); 2165 slot->retune_req |= SDHCI_RETUNE_REQ_RESET; 2166 if (slot->curcmd) { 2167 slot->curcmd->error = MMC_ERR_BADCRC; 2168 sdhci_finish_command(slot); 2169 } 2170 } 2171 /* Handle re-tuning interrupt. */ 2172 if (__predict_false(intmask & SDHCI_INT_RETUNE)) 2173 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; 2174 /* Handle card presence interrupts. */ 2175 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2176 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 2177 slot->intmask &= 2178 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2179 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 2180 SDHCI_INT_CARD_INSERT; 2181 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 2182 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 2183 WR4(slot, SDHCI_INT_STATUS, intmask & 2184 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 2185 sdhci_handle_card_present_locked(slot, present); 2186 } 2187 /* Handle command interrupts. */ 2188 if (intmask & SDHCI_INT_CMD_MASK) { 2189 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 2190 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 2191 } 2192 /* Handle data interrupts. */ 2193 if (intmask & SDHCI_INT_DATA_MASK) { 2194 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 2195 /* Don't call data_irq in case of errored command. */ 2196 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 2197 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 2198 } 2199 /* Handle AutoCMD12 error interrupt. */ 2200 if (intmask & SDHCI_INT_ACMD12ERR) { 2201 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 2202 sdhci_acmd_irq(slot); 2203 } 2204 /* Handle bus power interrupt. */ 2205 if (intmask & SDHCI_INT_BUS_POWER) { 2206 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 2207 slot_printf(slot, "Card is consuming too much power!\n"); 2208 } 2209 intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | 2210 SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | 2211 SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); 2212 /* The rest is unknown. */ 2213 if (intmask) { 2214 WR4(slot, SDHCI_INT_STATUS, intmask); 2215 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 2216 intmask); 2217 sdhci_dumpregs(slot); 2218 } 2219 2220 SDHCI_UNLOCK(slot); 2221 } 2222 2223 int 2224 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 2225 uintptr_t *result) 2226 { 2227 struct sdhci_slot *slot = device_get_ivars(child); 2228 2229 switch (which) { 2230 default: 2231 return (EINVAL); 2232 case MMCBR_IVAR_BUS_MODE: 2233 *result = slot->host.ios.bus_mode; 2234 break; 2235 case MMCBR_IVAR_BUS_WIDTH: 2236 *result = slot->host.ios.bus_width; 2237 break; 2238 case MMCBR_IVAR_CHIP_SELECT: 2239 *result = slot->host.ios.chip_select; 2240 break; 2241 case MMCBR_IVAR_CLOCK: 2242 *result = slot->host.ios.clock; 2243 break; 2244 case MMCBR_IVAR_F_MIN: 2245 *result = slot->host.f_min; 2246 break; 2247 case MMCBR_IVAR_F_MAX: 2248 *result = slot->host.f_max; 2249 break; 2250 case MMCBR_IVAR_HOST_OCR: 2251 *result = slot->host.host_ocr; 2252 break; 2253 case MMCBR_IVAR_MODE: 2254 *result = slot->host.mode; 2255 break; 2256 case MMCBR_IVAR_OCR: 2257 *result = slot->host.ocr; 2258 break; 2259 case MMCBR_IVAR_POWER_MODE: 2260 *result = slot->host.ios.power_mode; 2261 break; 2262 case MMCBR_IVAR_VDD: 2263 *result = slot->host.ios.vdd; 2264 break; 2265 case MMCBR_IVAR_RETUNE_REQ: 2266 if (slot->opt & SDHCI_TUNING_ENABLED) { 2267 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { 2268 *result = retune_req_reset; 2269 break; 2270 } 2271 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { 2272 *result = retune_req_normal; 2273 break; 2274 } 2275 } 2276 *result = retune_req_none; 2277 break; 2278 case MMCBR_IVAR_VCCQ: 2279 *result = slot->host.ios.vccq; 2280 break; 2281 case MMCBR_IVAR_CAPS: 2282 *result = slot->host.caps; 2283 break; 2284 case MMCBR_IVAR_TIMING: 2285 *result = slot->host.ios.timing; 2286 break; 2287 case MMCBR_IVAR_MAX_DATA: 2288 /* 2289 * Re-tuning modes 1 and 2 restrict the maximum data length 2290 * per read/write command to 4 MiB. 2291 */ 2292 if (slot->opt & SDHCI_TUNING_ENABLED && 2293 (slot->retune_mode == SDHCI_RETUNE_MODE_1 || 2294 slot->retune_mode == SDHCI_RETUNE_MODE_2)) { 2295 *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; 2296 break; 2297 } 2298 *result = 65535; 2299 break; 2300 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 2301 /* 2302 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 2303 */ 2304 *result = 1000000; 2305 break; 2306 } 2307 return (0); 2308 } 2309 2310 int 2311 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 2312 uintptr_t value) 2313 { 2314 struct sdhci_slot *slot = device_get_ivars(child); 2315 uint32_t clock, max_clock; 2316 int i; 2317 2318 if (sdhci_debug > 1) 2319 slot_printf(slot, "%s: var=%d\n", __func__, which); 2320 switch (which) { 2321 default: 2322 return (EINVAL); 2323 case MMCBR_IVAR_BUS_MODE: 2324 slot->host.ios.bus_mode = value; 2325 break; 2326 case MMCBR_IVAR_BUS_WIDTH: 2327 slot->host.ios.bus_width = value; 2328 break; 2329 case MMCBR_IVAR_CHIP_SELECT: 2330 slot->host.ios.chip_select = value; 2331 break; 2332 case MMCBR_IVAR_CLOCK: 2333 if (value > 0) { 2334 max_clock = slot->max_clk; 2335 clock = max_clock; 2336 2337 if (slot->version < SDHCI_SPEC_300) { 2338 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2339 i <<= 1) { 2340 if (clock <= value) 2341 break; 2342 clock >>= 1; 2343 } 2344 } else { 2345 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2346 i += 2) { 2347 if (clock <= value) 2348 break; 2349 clock = max_clock / (i + 2); 2350 } 2351 } 2352 2353 slot->host.ios.clock = clock; 2354 } else 2355 slot->host.ios.clock = 0; 2356 break; 2357 case MMCBR_IVAR_MODE: 2358 slot->host.mode = value; 2359 break; 2360 case MMCBR_IVAR_OCR: 2361 slot->host.ocr = value; 2362 break; 2363 case MMCBR_IVAR_POWER_MODE: 2364 slot->host.ios.power_mode = value; 2365 break; 2366 case MMCBR_IVAR_VDD: 2367 slot->host.ios.vdd = value; 2368 break; 2369 case MMCBR_IVAR_VCCQ: 2370 slot->host.ios.vccq = value; 2371 break; 2372 case MMCBR_IVAR_TIMING: 2373 slot->host.ios.timing = value; 2374 break; 2375 case MMCBR_IVAR_CAPS: 2376 case MMCBR_IVAR_HOST_OCR: 2377 case MMCBR_IVAR_F_MIN: 2378 case MMCBR_IVAR_F_MAX: 2379 case MMCBR_IVAR_MAX_DATA: 2380 case MMCBR_IVAR_RETUNE_REQ: 2381 return (EINVAL); 2382 } 2383 return (0); 2384 } 2385 2386 #ifdef MMCCAM 2387 void 2388 sdhci_start_slot(struct sdhci_slot *slot) 2389 { 2390 if ((slot->devq = cam_simq_alloc(1)) == NULL) { 2391 goto fail; 2392 } 2393 2394 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 2395 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 2396 "sdhci_slot", slot, device_get_unit(slot->bus), 2397 &slot->sim_mtx, 1, 1, slot->devq); 2398 2399 if (slot->sim == NULL) { 2400 cam_simq_free(slot->devq); 2401 slot_printf(slot, "cannot allocate CAM SIM\n"); 2402 goto fail; 2403 } 2404 2405 mtx_lock(&slot->sim_mtx); 2406 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2407 slot_printf(slot, 2408 "cannot register SCSI pass-through bus\n"); 2409 cam_sim_free(slot->sim, FALSE); 2410 cam_simq_free(slot->devq); 2411 mtx_unlock(&slot->sim_mtx); 2412 goto fail; 2413 } 2414 2415 mtx_unlock(&slot->sim_mtx); 2416 /* End CAM-specific init */ 2417 slot->card_present = 0; 2418 sdhci_card_task(slot, 0); 2419 return; 2420 2421 fail: 2422 if (slot->sim != NULL) { 2423 mtx_lock(&slot->sim_mtx); 2424 xpt_bus_deregister(cam_sim_path(slot->sim)); 2425 cam_sim_free(slot->sim, FALSE); 2426 mtx_unlock(&slot->sim_mtx); 2427 } 2428 2429 if (slot->devq != NULL) 2430 cam_simq_free(slot->devq); 2431 } 2432 2433 static void 2434 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2435 { 2436 struct sdhci_slot *slot; 2437 2438 slot = cam_sim_softc(sim); 2439 2440 sdhci_cam_request(slot, ccb); 2441 } 2442 2443 void 2444 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2445 { 2446 struct sdhci_slot *slot; 2447 2448 slot = cam_sim_softc(sim); 2449 if (slot == NULL) { 2450 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2451 xpt_done(ccb); 2452 return; 2453 } 2454 2455 mtx_assert(&slot->sim_mtx, MA_OWNED); 2456 2457 switch (ccb->ccb_h.func_code) { 2458 case XPT_PATH_INQ: 2459 { 2460 struct ccb_pathinq *cpi; 2461 2462 cpi = &ccb->cpi; 2463 cpi->version_num = 1; 2464 cpi->hba_inquiry = 0; 2465 cpi->target_sprt = 0; 2466 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2467 cpi->hba_eng_cnt = 0; 2468 cpi->max_target = 0; 2469 cpi->max_lun = 0; 2470 cpi->initiator_id = 1; 2471 cpi->maxio = MAXPHYS; 2472 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2473 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2474 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2475 cpi->unit_number = cam_sim_unit(sim); 2476 cpi->bus_id = cam_sim_bus(sim); 2477 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2478 cpi->protocol = PROTO_MMCSD; 2479 cpi->protocol_version = SCSI_REV_0; 2480 cpi->transport = XPORT_MMCSD; 2481 cpi->transport_version = 0; 2482 2483 cpi->ccb_h.status = CAM_REQ_CMP; 2484 break; 2485 } 2486 case XPT_GET_TRAN_SETTINGS: 2487 { 2488 struct ccb_trans_settings *cts = &ccb->cts; 2489 2490 if (sdhci_debug > 1) 2491 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2492 2493 cts->protocol = PROTO_MMCSD; 2494 cts->protocol_version = 1; 2495 cts->transport = XPORT_MMCSD; 2496 cts->transport_version = 1; 2497 cts->xport_specific.valid = 0; 2498 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2499 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2500 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2501 cts->proto_specific.mmc.host_caps = slot->host.caps; 2502 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2503 ccb->ccb_h.status = CAM_REQ_CMP; 2504 break; 2505 } 2506 case XPT_SET_TRAN_SETTINGS: 2507 { 2508 if (sdhci_debug > 1) 2509 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2510 sdhci_cam_settran_settings(slot, ccb); 2511 ccb->ccb_h.status = CAM_REQ_CMP; 2512 break; 2513 } 2514 case XPT_RESET_BUS: 2515 if (sdhci_debug > 1) 2516 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2517 ccb->ccb_h.status = CAM_REQ_CMP; 2518 break; 2519 case XPT_MMC_IO: 2520 /* 2521 * Here is the HW-dependent part of 2522 * sending the command to the underlying h/w 2523 * At some point in the future an interrupt comes. 2524 * Then the request will be marked as completed. 2525 */ 2526 if (__predict_false(sdhci_debug > 1)) 2527 slot_printf(slot, "Got XPT_MMC_IO\n"); 2528 ccb->ccb_h.status = CAM_REQ_INPROG; 2529 2530 sdhci_cam_handle_mmcio(sim, ccb); 2531 return; 2532 /* NOTREACHED */ 2533 break; 2534 default: 2535 ccb->ccb_h.status = CAM_REQ_INVALID; 2536 break; 2537 } 2538 xpt_done(ccb); 2539 return; 2540 } 2541 2542 void 2543 sdhci_cam_poll(struct cam_sim *sim) 2544 { 2545 return; 2546 } 2547 2548 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) { 2549 int max_clock, clock, i; 2550 2551 if (proposed_clock == 0) 2552 return 0; 2553 max_clock = slot->max_clk; 2554 clock = max_clock; 2555 2556 if (slot->version < SDHCI_SPEC_300) { 2557 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2558 i <<= 1) { 2559 if (clock <= proposed_clock) 2560 break; 2561 clock >>= 1; 2562 } 2563 } else { 2564 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2565 i += 2) { 2566 if (clock <= proposed_clock) 2567 break; 2568 clock = max_clock / (i + 2); 2569 } 2570 } 2571 return clock; 2572 } 2573 2574 int 2575 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2576 { 2577 struct mmc_ios *ios; 2578 struct mmc_ios *new_ios; 2579 struct ccb_trans_settings_mmc *cts; 2580 2581 ios = &slot->host.ios; 2582 2583 cts = &ccb->cts.proto_specific.mmc; 2584 new_ios = &cts->ios; 2585 2586 /* Update only requested fields */ 2587 if (cts->ios_valid & MMC_CLK) { 2588 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2589 slot_printf(slot, "Clock => %d\n", ios->clock); 2590 } 2591 if (cts->ios_valid & MMC_VDD) { 2592 ios->vdd = new_ios->vdd; 2593 slot_printf(slot, "VDD => %d\n", ios->vdd); 2594 } 2595 if (cts->ios_valid & MMC_CS) { 2596 ios->chip_select = new_ios->chip_select; 2597 slot_printf(slot, "CS => %d\n", ios->chip_select); 2598 } 2599 if (cts->ios_valid & MMC_BW) { 2600 ios->bus_width = new_ios->bus_width; 2601 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2602 } 2603 if (cts->ios_valid & MMC_PM) { 2604 ios->power_mode = new_ios->power_mode; 2605 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2606 } 2607 if (cts->ios_valid & MMC_BT) { 2608 ios->timing = new_ios->timing; 2609 slot_printf(slot, "Timing => %d\n", ios->timing); 2610 } 2611 if (cts->ios_valid & MMC_BM) { 2612 ios->bus_mode = new_ios->bus_mode; 2613 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2614 } 2615 2616 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2617 return (sdhci_cam_update_ios(slot)); 2618 } 2619 2620 int 2621 sdhci_cam_update_ios(struct sdhci_slot *slot) 2622 { 2623 struct mmc_ios *ios = &slot->host.ios; 2624 2625 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2626 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2627 SDHCI_LOCK(slot); 2628 /* Do full reset on bus power down to clear from any state. */ 2629 if (ios->power_mode == power_off) { 2630 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2631 sdhci_init(slot); 2632 } 2633 /* Configure the bus. */ 2634 sdhci_set_clock(slot, ios->clock); 2635 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2636 if (ios->bus_width == bus_width_8) { 2637 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2638 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2639 } else if (ios->bus_width == bus_width_4) { 2640 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2641 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2642 } else if (ios->bus_width == bus_width_1) { 2643 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2644 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2645 } else { 2646 panic("Invalid bus width: %d", ios->bus_width); 2647 } 2648 if (ios->timing == bus_timing_hs && 2649 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2650 slot->hostctrl |= SDHCI_CTRL_HISPD; 2651 else 2652 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2653 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2654 /* Some controllers like reset after bus changes. */ 2655 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2656 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2657 2658 SDHCI_UNLOCK(slot); 2659 return (0); 2660 } 2661 2662 int 2663 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2664 { 2665 struct ccb_mmcio *mmcio; 2666 2667 mmcio = &ccb->mmcio; 2668 2669 SDHCI_LOCK(slot); 2670 /* if (slot->req != NULL) { 2671 SDHCI_UNLOCK(slot); 2672 return (EBUSY); 2673 } 2674 */ 2675 if (__predict_false(sdhci_debug > 1)) { 2676 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2677 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2678 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2679 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 2680 } 2681 if (mmcio->cmd.data != NULL) { 2682 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2683 panic("data->len = %d, data->flags = %d -- something is b0rked", 2684 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2685 } 2686 slot->ccb = ccb; 2687 slot->flags = 0; 2688 sdhci_start(slot); 2689 SDHCI_UNLOCK(slot); 2690 if (dumping) { 2691 while (slot->ccb != NULL) { 2692 sdhci_generic_intr(slot); 2693 DELAY(10); 2694 } 2695 } 2696 return (0); 2697 } 2698 #endif /* MMCCAM */ 2699 2700 MODULE_VERSION(sdhci, 1); 2701