1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/callout.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/stdarg.h> 46 47 #include <dev/mmc/bridge.h> 48 #include <dev/mmc/mmcreg.h> 49 #include <dev/mmc/mmcbrvar.h> 50 51 #include <cam/cam.h> 52 #include <cam/cam_ccb.h> 53 #include <cam/cam_debug.h> 54 #include <cam/cam_sim.h> 55 #include <cam/cam_xpt_sim.h> 56 57 #include "mmcbr_if.h" 58 #include "sdhci.h" 59 #include "sdhci_if.h" 60 61 #include "opt_mmccam.h" 62 63 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 64 65 static int sdhci_debug = 0; 66 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, 67 "Debug level"); 68 u_int sdhci_quirk_clear = 0; 69 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 70 0, "Mask of quirks to clear"); 71 u_int sdhci_quirk_set = 0; 72 SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, 73 "Mask of quirks to set"); 74 75 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 76 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 77 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 78 #define RD_MULTI_4(slot, off, ptr, count) \ 79 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 80 81 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 82 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 83 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 84 #define WR_MULTI_4(slot, off, ptr, count) \ 85 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 86 87 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 88 static void sdhci_start(struct sdhci_slot *slot); 89 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 90 91 static void sdhci_card_poll(void *); 92 static void sdhci_card_task(void *, int); 93 94 /* CAM-related */ 95 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock); 96 static int sdhci_cam_update_ios(struct sdhci_slot *slot); 97 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); 98 static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); 99 static void sdhci_cam_poll(struct cam_sim *sim); 100 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); 101 102 /* helper routines */ 103 static void sdhci_dumpregs(struct sdhci_slot *slot); 104 static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 105 __printflike(2, 3); 106 107 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 108 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 109 #define SDHCI_LOCK_INIT(_slot) \ 110 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 111 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 112 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 113 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 114 115 #define SDHCI_DEFAULT_MAX_FREQ 50 116 117 #define SDHCI_200_MAX_DIVIDER 256 118 #define SDHCI_300_MAX_DIVIDER 2046 119 120 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) 121 #define SDHCI_INSERT_DELAY_TICKS (hz / 2) 122 123 /* 124 * Broadcom BCM577xx Controller Constants 125 */ 126 /* Maximum divider supported by the default clock source. */ 127 #define BCM577XX_DEFAULT_MAX_DIVIDER 256 128 /* Alternative clock's base frequency. */ 129 #define BCM577XX_ALT_CLOCK_BASE 63000000 130 131 #define BCM577XX_HOST_CONTROL 0x198 132 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF 133 #define BCM577XX_CTRL_CLKSEL_SHIFT 12 134 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 135 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 136 137 static void 138 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 139 { 140 141 if (error != 0) { 142 printf("getaddr: error %d\n", error); 143 return; 144 } 145 *(bus_addr_t *)arg = segs[0].ds_addr; 146 } 147 148 static int 149 slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 150 { 151 va_list ap; 152 int retval; 153 154 retval = printf("%s-slot%d: ", 155 device_get_nameunit(slot->bus), slot->num); 156 157 va_start(ap, fmt); 158 retval += vprintf(fmt, ap); 159 va_end(ap); 160 return (retval); 161 } 162 163 static void 164 sdhci_dumpregs(struct sdhci_slot *slot) 165 { 166 167 slot_printf(slot, 168 "============== REGISTER DUMP ==============\n"); 169 170 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 171 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 172 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 173 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 174 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 175 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 176 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 177 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 178 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 179 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 180 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 181 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 182 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 183 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 184 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 185 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 186 slot_printf(slot, "AC12 err: 0x%08x | Host ctl2: 0x%08x\n", 187 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); 188 slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", 189 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); 190 slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", 191 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); 192 slot_printf(slot, "ADMA addr: 0x%08x | Slot int: 0x%08x\n", 193 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); 194 195 slot_printf(slot, 196 "===========================================\n"); 197 } 198 199 static void 200 sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 201 { 202 int timeout; 203 uint32_t clock; 204 205 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 206 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) 207 return; 208 } 209 210 /* Some controllers need this kick or reset won't work. */ 211 if ((mask & SDHCI_RESET_ALL) == 0 && 212 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 213 /* This is to force an update */ 214 clock = slot->clock; 215 slot->clock = 0; 216 sdhci_set_clock(slot, clock); 217 } 218 219 if (mask & SDHCI_RESET_ALL) { 220 slot->clock = 0; 221 slot->power = 0; 222 } 223 224 WR1(slot, SDHCI_SOFTWARE_RESET, mask); 225 226 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { 227 /* 228 * Resets on TI OMAPs and AM335x are incompatible with SDHCI 229 * specification. The reset bit has internal propagation delay, 230 * so a fast read after write returns 0 even if reset process is 231 * in progress. The workaround is to poll for 1 before polling 232 * for 0. In the worst case, if we miss seeing it asserted the 233 * time we spent waiting is enough to ensure the reset finishes. 234 */ 235 timeout = 10000; 236 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { 237 if (timeout <= 0) 238 break; 239 timeout--; 240 DELAY(1); 241 } 242 } 243 244 /* Wait max 100 ms */ 245 timeout = 10000; 246 /* Controller clears the bits when it's done */ 247 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { 248 if (timeout <= 0) { 249 slot_printf(slot, "Reset 0x%x never completed.\n", 250 mask); 251 sdhci_dumpregs(slot); 252 return; 253 } 254 timeout--; 255 DELAY(10); 256 } 257 } 258 259 static void 260 sdhci_init(struct sdhci_slot *slot) 261 { 262 263 sdhci_reset(slot, SDHCI_RESET_ALL); 264 265 /* Enable interrupts. */ 266 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 267 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 268 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 269 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 270 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 271 SDHCI_INT_ACMD12ERR | SDHCI_INT_CARD_INT; 272 273 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 274 !(slot->opt & SDHCI_NON_REMOVABLE)) { 275 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 276 } 277 278 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 279 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 280 } 281 282 static void 283 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 284 { 285 uint32_t clk_base; 286 uint32_t clk_sel; 287 uint32_t res; 288 uint16_t clk; 289 uint16_t div; 290 int timeout; 291 292 if (clock == slot->clock) 293 return; 294 slot->clock = clock; 295 296 /* Turn off the clock. */ 297 clk = RD2(slot, SDHCI_CLOCK_CONTROL); 298 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); 299 /* If no clock requested - leave it so. */ 300 if (clock == 0) 301 return; 302 303 /* Determine the clock base frequency */ 304 clk_base = slot->max_clk; 305 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { 306 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & 307 BCM577XX_CTRL_CLKSEL_MASK; 308 309 /* 310 * Select clock source appropriate for the requested frequency. 311 */ 312 if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { 313 clk_base = BCM577XX_ALT_CLOCK_BASE; 314 clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << 315 BCM577XX_CTRL_CLKSEL_SHIFT); 316 } else { 317 clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << 318 BCM577XX_CTRL_CLKSEL_SHIFT); 319 } 320 321 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); 322 } 323 324 /* Recalculate timeout clock frequency based on the new sd clock. */ 325 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 326 slot->timeout_clk = slot->clock / 1000; 327 328 if (slot->version < SDHCI_SPEC_300) { 329 /* Looking for highest freq <= clock. */ 330 res = clk_base; 331 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { 332 if (res <= clock) 333 break; 334 res >>= 1; 335 } 336 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 337 div >>= 1; 338 } else { 339 /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ 340 if (clock >= clk_base) 341 div = 0; 342 else { 343 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { 344 if ((clk_base / div) <= clock) 345 break; 346 } 347 } 348 div >>= 1; 349 } 350 351 if (bootverbose || sdhci_debug) 352 slot_printf(slot, "Divider %d for freq %d (base %d)\n", 353 div, clock, clk_base); 354 355 /* Now we have got divider, set it. */ 356 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 357 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) 358 << SDHCI_DIVIDER_HI_SHIFT; 359 360 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 361 /* Enable clock. */ 362 clk |= SDHCI_CLOCK_INT_EN; 363 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 364 /* Wait up to 10 ms until it stabilize. */ 365 timeout = 10; 366 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 367 & SDHCI_CLOCK_INT_STABLE)) { 368 if (timeout == 0) { 369 slot_printf(slot, 370 "Internal clock never stabilised.\n"); 371 sdhci_dumpregs(slot); 372 return; 373 } 374 timeout--; 375 DELAY(1000); 376 } 377 /* Pass clock signal to the bus. */ 378 clk |= SDHCI_CLOCK_CARD_EN; 379 WR2(slot, SDHCI_CLOCK_CONTROL, clk); 380 } 381 382 static void 383 sdhci_set_power(struct sdhci_slot *slot, u_char power) 384 { 385 int i; 386 uint8_t pwr; 387 388 if (slot->power == power) 389 return; 390 391 slot->power = power; 392 393 /* Turn off the power. */ 394 pwr = 0; 395 WR1(slot, SDHCI_POWER_CONTROL, pwr); 396 /* If power down requested - leave it so. */ 397 if (power == 0) 398 return; 399 /* Set voltage. */ 400 switch (1 << power) { 401 case MMC_OCR_LOW_VOLTAGE: 402 pwr |= SDHCI_POWER_180; 403 break; 404 case MMC_OCR_290_300: 405 case MMC_OCR_300_310: 406 pwr |= SDHCI_POWER_300; 407 break; 408 case MMC_OCR_320_330: 409 case MMC_OCR_330_340: 410 pwr |= SDHCI_POWER_330; 411 break; 412 } 413 WR1(slot, SDHCI_POWER_CONTROL, pwr); 414 /* 415 * Turn on VDD1 power. Note that at least some Intel controllers can 416 * fail to enable bus power on the first try after transiting from D3 417 * to D0, so we give them up to 2 ms. 418 */ 419 pwr |= SDHCI_POWER_ON; 420 for (i = 0; i < 20; i++) { 421 WR1(slot, SDHCI_POWER_CONTROL, pwr); 422 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) 423 break; 424 DELAY(100); 425 } 426 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) 427 slot_printf(slot, "Bus power failed to enable"); 428 429 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { 430 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); 431 DELAY(10); 432 WR1(slot, SDHCI_POWER_CONTROL, pwr); 433 DELAY(300); 434 } 435 } 436 437 static void 438 sdhci_read_block_pio(struct sdhci_slot *slot) 439 { 440 uint32_t data; 441 char *buffer; 442 size_t left; 443 444 buffer = slot->curcmd->data->data; 445 buffer += slot->offset; 446 /* Transfer one block at a time. */ 447 left = min(512, slot->curcmd->data->len - slot->offset); 448 slot->offset += left; 449 450 /* If we are too fast, broken controllers return zeroes. */ 451 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 452 DELAY(10); 453 /* Handle unaligned and aligned buffer cases. */ 454 if ((intptr_t)buffer & 3) { 455 while (left > 3) { 456 data = RD4(slot, SDHCI_BUFFER); 457 buffer[0] = data; 458 buffer[1] = (data >> 8); 459 buffer[2] = (data >> 16); 460 buffer[3] = (data >> 24); 461 buffer += 4; 462 left -= 4; 463 } 464 } else { 465 RD_MULTI_4(slot, SDHCI_BUFFER, 466 (uint32_t *)buffer, left >> 2); 467 left &= 3; 468 } 469 /* Handle uneven size case. */ 470 if (left > 0) { 471 data = RD4(slot, SDHCI_BUFFER); 472 while (left > 0) { 473 *(buffer++) = data; 474 data >>= 8; 475 left--; 476 } 477 } 478 } 479 480 static void 481 sdhci_write_block_pio(struct sdhci_slot *slot) 482 { 483 uint32_t data = 0; 484 char *buffer; 485 size_t left; 486 487 buffer = slot->curcmd->data->data; 488 buffer += slot->offset; 489 /* Transfer one block at a time. */ 490 left = min(512, slot->curcmd->data->len - slot->offset); 491 slot->offset += left; 492 493 /* Handle unaligned and aligned buffer cases. */ 494 if ((intptr_t)buffer & 3) { 495 while (left > 3) { 496 data = buffer[0] + 497 (buffer[1] << 8) + 498 (buffer[2] << 16) + 499 (buffer[3] << 24); 500 left -= 4; 501 buffer += 4; 502 WR4(slot, SDHCI_BUFFER, data); 503 } 504 } else { 505 WR_MULTI_4(slot, SDHCI_BUFFER, 506 (uint32_t *)buffer, left >> 2); 507 left &= 3; 508 } 509 /* Handle uneven size case. */ 510 if (left > 0) { 511 while (left > 0) { 512 data <<= 8; 513 data += *(buffer++); 514 left--; 515 } 516 WR4(slot, SDHCI_BUFFER, data); 517 } 518 } 519 520 static void 521 sdhci_transfer_pio(struct sdhci_slot *slot) 522 { 523 524 /* Read as many blocks as possible. */ 525 if (slot->curcmd->data->flags & MMC_DATA_READ) { 526 while (RD4(slot, SDHCI_PRESENT_STATE) & 527 SDHCI_DATA_AVAILABLE) { 528 sdhci_read_block_pio(slot); 529 if (slot->offset >= slot->curcmd->data->len) 530 break; 531 } 532 } else { 533 while (RD4(slot, SDHCI_PRESENT_STATE) & 534 SDHCI_SPACE_AVAILABLE) { 535 sdhci_write_block_pio(slot); 536 if (slot->offset >= slot->curcmd->data->len) 537 break; 538 } 539 } 540 } 541 542 static void 543 sdhci_card_task(void *arg, int pending __unused) 544 { 545 struct sdhci_slot *slot = arg; 546 device_t d; 547 548 SDHCI_LOCK(slot); 549 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { 550 #ifdef MMCCAM 551 if (slot->card_present == 0) { 552 #else 553 if (slot->dev == NULL) { 554 #endif 555 /* If card is present - attach mmc bus. */ 556 if (bootverbose || sdhci_debug) 557 slot_printf(slot, "Card inserted\n"); 558 #ifdef MMCCAM 559 slot->card_present = 1; 560 union ccb *ccb; 561 uint32_t pathid; 562 pathid = cam_sim_path(slot->sim); 563 ccb = xpt_alloc_ccb_nowait(); 564 if (ccb == NULL) { 565 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 566 SDHCI_UNLOCK(slot); 567 return; 568 } 569 570 /* 571 * We create a rescan request for BUS:0:0, since the card 572 * will be at lun 0. 573 */ 574 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 575 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 576 slot_printf(slot, "Unable to create path for rescan\n"); 577 SDHCI_UNLOCK(slot); 578 xpt_free_ccb(ccb); 579 return; 580 } 581 SDHCI_UNLOCK(slot); 582 xpt_rescan(ccb); 583 #else 584 slot->dev = device_add_child(slot->bus, "mmc", -1); 585 device_set_ivars(slot->dev, slot); 586 SDHCI_UNLOCK(slot); 587 device_probe_and_attach(slot->dev); 588 #endif 589 } else 590 SDHCI_UNLOCK(slot); 591 } else { 592 #ifdef MMCCAM 593 if (slot->card_present == 1) { 594 #else 595 if (slot->dev != NULL) { 596 #endif 597 /* If no card present - detach mmc bus. */ 598 if (bootverbose || sdhci_debug) 599 slot_printf(slot, "Card removed\n"); 600 d = slot->dev; 601 slot->dev = NULL; 602 #ifdef MMCCAM 603 slot->card_present = 0; 604 union ccb *ccb; 605 uint32_t pathid; 606 pathid = cam_sim_path(slot->sim); 607 ccb = xpt_alloc_ccb_nowait(); 608 if (ccb == NULL) { 609 slot_printf(slot, "Unable to alloc CCB for rescan\n"); 610 SDHCI_UNLOCK(slot); 611 return; 612 } 613 614 /* 615 * We create a rescan request for BUS:0:0, since the card 616 * will be at lun 0. 617 */ 618 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 619 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 620 slot_printf(slot, "Unable to create path for rescan\n"); 621 SDHCI_UNLOCK(slot); 622 xpt_free_ccb(ccb); 623 return; 624 } 625 SDHCI_UNLOCK(slot); 626 xpt_rescan(ccb); 627 #else 628 SDHCI_UNLOCK(slot); 629 device_delete_child(slot->bus, d); 630 #endif 631 } else 632 SDHCI_UNLOCK(slot); 633 } 634 } 635 636 static void 637 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) 638 { 639 bool was_present; 640 641 /* 642 * If there was no card and now there is one, schedule the task to 643 * create the child device after a short delay. The delay is to 644 * debounce the card insert (sometimes the card detect pin stabilizes 645 * before the other pins have made good contact). 646 * 647 * If there was a card present and now it's gone, immediately schedule 648 * the task to delete the child device. No debouncing -- gone is gone, 649 * because once power is removed, a full card re-init is needed, and 650 * that happens by deleting and recreating the child device. 651 */ 652 #ifdef MMCCAM 653 was_present = slot->card_present; 654 #else 655 was_present = slot->dev != NULL; 656 #endif 657 if (!was_present && is_present) { 658 taskqueue_enqueue_timeout(taskqueue_swi_giant, 659 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); 660 } else if (was_present && !is_present) { 661 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 662 } 663 } 664 665 void 666 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) 667 { 668 669 SDHCI_LOCK(slot); 670 sdhci_handle_card_present_locked(slot, is_present); 671 SDHCI_UNLOCK(slot); 672 } 673 674 static void 675 sdhci_card_poll(void *arg) 676 { 677 struct sdhci_slot *slot = arg; 678 679 sdhci_handle_card_present(slot, 680 SDHCI_GET_CARD_PRESENT(slot->bus, slot)); 681 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, 682 sdhci_card_poll, slot); 683 } 684 685 int 686 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 687 { 688 uint32_t caps, caps2, freq, host_caps; 689 int err; 690 691 SDHCI_LOCK_INIT(slot); 692 693 slot->num = num; 694 slot->bus = dev; 695 696 /* Allocate DMA tag. */ 697 err = bus_dma_tag_create(bus_get_dma_tag(dev), 698 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 699 BUS_SPACE_MAXADDR, NULL, NULL, 700 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 701 BUS_DMA_ALLOCNOW, NULL, NULL, 702 &slot->dmatag); 703 if (err != 0) { 704 device_printf(dev, "Can't create DMA tag\n"); 705 SDHCI_LOCK_DESTROY(slot); 706 return (err); 707 } 708 /* Allocate DMA memory. */ 709 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 710 BUS_DMA_NOWAIT, &slot->dmamap); 711 if (err != 0) { 712 device_printf(dev, "Can't alloc DMA memory\n"); 713 SDHCI_LOCK_DESTROY(slot); 714 return (err); 715 } 716 /* Map the memory. */ 717 err = bus_dmamap_load(slot->dmatag, slot->dmamap, 718 (void *)slot->dmamem, DMA_BLOCK_SIZE, 719 sdhci_getaddr, &slot->paddr, 0); 720 if (err != 0 || slot->paddr == 0) { 721 device_printf(dev, "Can't load DMA memory\n"); 722 SDHCI_LOCK_DESTROY(slot); 723 if (err) 724 return (err); 725 else 726 return (EFAULT); 727 } 728 729 /* Initialize slot. */ 730 sdhci_init(slot); 731 slot->version = (RD2(slot, SDHCI_HOST_VERSION) 732 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 733 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { 734 caps = slot->caps; 735 caps2 = slot->caps2; 736 } else { 737 caps = RD4(slot, SDHCI_CAPABILITIES); 738 if (slot->version >= SDHCI_SPEC_300) 739 caps2 = RD4(slot, SDHCI_CAPABILITIES2); 740 else 741 caps2 = 0; 742 } 743 /* Calculate base clock frequency. */ 744 if (slot->version >= SDHCI_SPEC_300) 745 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 746 SDHCI_CLOCK_BASE_SHIFT; 747 else 748 freq = (caps & SDHCI_CLOCK_BASE_MASK) >> 749 SDHCI_CLOCK_BASE_SHIFT; 750 if (freq != 0) 751 slot->max_clk = freq * 1000000; 752 /* 753 * If the frequency wasn't in the capabilities and the hardware driver 754 * hasn't already set max_clk we're probably not going to work right 755 * with an assumption, so complain about it. 756 */ 757 if (slot->max_clk == 0) { 758 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; 759 device_printf(dev, "Hardware doesn't specify base clock " 760 "frequency, using %dMHz as default.\n", 761 SDHCI_DEFAULT_MAX_FREQ); 762 } 763 /* Calculate/set timeout clock frequency. */ 764 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { 765 slot->timeout_clk = slot->max_clk / 1000; 766 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { 767 slot->timeout_clk = 1000; 768 } else { 769 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> 770 SDHCI_TIMEOUT_CLK_SHIFT; 771 if (caps & SDHCI_TIMEOUT_CLK_UNIT) 772 slot->timeout_clk *= 1000; 773 } 774 /* 775 * If the frequency wasn't in the capabilities and the hardware driver 776 * hasn't already set timeout_clk we'll probably work okay using the 777 * max timeout, but still mention it. 778 */ 779 if (slot->timeout_clk == 0) { 780 device_printf(dev, "Hardware doesn't specify timeout clock " 781 "frequency, setting BROKEN_TIMEOUT quirk.\n"); 782 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 783 } 784 785 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); 786 slot->host.f_max = slot->max_clk; 787 slot->host.host_ocr = 0; 788 if (caps & SDHCI_CAN_VDD_330) 789 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 790 if (caps & SDHCI_CAN_VDD_300) 791 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 792 if (caps & SDHCI_CAN_VDD_180) 793 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 794 if (slot->host.host_ocr == 0) { 795 device_printf(dev, "Hardware doesn't report any " 796 "support voltages.\n"); 797 } 798 host_caps = MMC_CAP_4_BIT_DATA; 799 if (caps & SDHCI_CAN_DO_8BITBUS) 800 host_caps |= MMC_CAP_8_BIT_DATA; 801 if (caps & SDHCI_CAN_DO_HISPD) 802 host_caps |= MMC_CAP_HSPEED; 803 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) 804 host_caps |= MMC_CAP_BOOT_NOACC; 805 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) 806 host_caps |= MMC_CAP_WAIT_WHILE_BUSY; 807 if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) 808 host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 809 if (caps2 & SDHCI_CAN_SDR104) { 810 host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 811 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) 812 host_caps |= MMC_CAP_MMC_HS200; 813 } else if (caps2 & SDHCI_CAN_SDR50) 814 host_caps |= MMC_CAP_UHS_SDR50; 815 if (caps2 & SDHCI_CAN_DDR50 && 816 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) 817 host_caps |= MMC_CAP_UHS_DDR50; 818 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) 819 host_caps |= MMC_CAP_MMC_DDR52; 820 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && 821 caps2 & SDHCI_CAN_MMC_HS400) 822 host_caps |= MMC_CAP_MMC_HS400; 823 host_caps |= MMC_CAP_SIGNALING_330; 824 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 825 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | 826 MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | 827 MMC_CAP_MMC_HS400_180)) 828 host_caps |= MMC_CAP_SIGNALING_180; 829 if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) 830 host_caps |= MMC_CAP_DRIVER_TYPE_A; 831 if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) 832 host_caps |= MMC_CAP_DRIVER_TYPE_C; 833 if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) 834 host_caps |= MMC_CAP_DRIVER_TYPE_D; 835 slot->host.caps = host_caps; 836 837 /* Decide if we have usable DMA. */ 838 if (caps & SDHCI_CAN_DO_DMA) 839 slot->opt |= SDHCI_HAVE_DMA; 840 841 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 842 slot->opt &= ~SDHCI_HAVE_DMA; 843 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 844 slot->opt |= SDHCI_HAVE_DMA; 845 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) 846 slot->opt |= SDHCI_NON_REMOVABLE; 847 848 /* 849 * Use platform-provided transfer backend 850 * with PIO as a fallback mechanism 851 */ 852 if (slot->opt & SDHCI_PLATFORM_TRANSFER) 853 slot->opt &= ~SDHCI_HAVE_DMA; 854 855 if (bootverbose || sdhci_debug) { 856 slot_printf(slot, 857 "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s\n", 858 slot->max_clk / 1000000, 859 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 860 (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : 861 ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), 862 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 863 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 864 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 865 (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", 866 (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", 867 (caps2 & SDHCI_CAN_DRIVE_TYPE_A) ? "A" : "", 868 (caps2 & SDHCI_CAN_DRIVE_TYPE_C) ? "C" : "", 869 (caps2 & SDHCI_CAN_DRIVE_TYPE_D) ? "D" : "", 870 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 871 if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | 872 MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) 873 slot_printf(slot, "eMMC:%s%s%s%s\n", 874 (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", 875 (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", 876 (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", 877 ((host_caps & 878 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == 879 (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? 880 " HS400ES" : ""); 881 if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 882 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) 883 slot_printf(slot, "UHS-I:%s%s%s%s%s\n", 884 (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", 885 (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", 886 (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", 887 (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", 888 (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); 889 sdhci_dumpregs(slot); 890 } 891 892 slot->timeout = 10; 893 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), 894 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, 895 "timeout", CTLFLAG_RW, &slot->timeout, 0, 896 "Maximum timeout for SDHCI transfers (in secs)"); 897 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 898 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, 899 sdhci_card_task, slot); 900 callout_init(&slot->card_poll_callout, 1); 901 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); 902 903 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && 904 !(slot->opt & SDHCI_NON_REMOVABLE)) { 905 callout_reset(&slot->card_poll_callout, 906 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); 907 } 908 909 return (0); 910 } 911 912 void 913 sdhci_start_slot(struct sdhci_slot *slot) 914 { 915 916 sdhci_card_task(slot, 0); 917 } 918 919 int 920 sdhci_cleanup_slot(struct sdhci_slot *slot) 921 { 922 device_t d; 923 924 callout_drain(&slot->timeout_callout); 925 callout_drain(&slot->card_poll_callout); 926 taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 927 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); 928 929 SDHCI_LOCK(slot); 930 d = slot->dev; 931 slot->dev = NULL; 932 SDHCI_UNLOCK(slot); 933 if (d != NULL) 934 device_delete_child(slot->bus, d); 935 936 SDHCI_LOCK(slot); 937 sdhci_reset(slot, SDHCI_RESET_ALL); 938 SDHCI_UNLOCK(slot); 939 bus_dmamap_unload(slot->dmatag, slot->dmamap); 940 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 941 bus_dma_tag_destroy(slot->dmatag); 942 943 SDHCI_LOCK_DESTROY(slot); 944 945 return (0); 946 } 947 948 int 949 sdhci_generic_suspend(struct sdhci_slot *slot) 950 { 951 952 sdhci_reset(slot, SDHCI_RESET_ALL); 953 954 return (0); 955 } 956 957 int 958 sdhci_generic_resume(struct sdhci_slot *slot) 959 { 960 961 sdhci_init(slot); 962 963 return (0); 964 } 965 966 uint32_t 967 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) 968 { 969 970 if (slot->version >= SDHCI_SPEC_300) 971 return (slot->max_clk / SDHCI_300_MAX_DIVIDER); 972 else 973 return (slot->max_clk / SDHCI_200_MAX_DIVIDER); 974 } 975 976 bool 977 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) 978 { 979 980 if (slot->opt & SDHCI_NON_REMOVABLE) 981 return true; 982 983 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 984 } 985 986 void 987 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) 988 { 989 struct mmc_ios *ios; 990 uint16_t hostctrl2; 991 992 if (slot->version < SDHCI_SPEC_300) 993 return; 994 995 ios = &slot->host.ios; 996 sdhci_set_clock(slot, 0); 997 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 998 hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; 999 if (ios->timing == bus_timing_mmc_hs400 || 1000 ios->timing == bus_timing_mmc_hs400es) 1001 hostctrl2 |= SDHCI_CTRL2_MMC_HS400; 1002 else if (ios->clock > SD_SDR50_MAX) 1003 hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; 1004 else if (ios->clock > SD_SDR25_MAX) 1005 hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; 1006 else if (ios->clock > SD_SDR12_MAX) { 1007 if (ios->timing == bus_timing_uhs_ddr50 || 1008 ios->timing == bus_timing_mmc_ddr52) 1009 hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; 1010 else 1011 hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; 1012 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) 1013 hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; 1014 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1015 sdhci_set_clock(slot, ios->clock); 1016 } 1017 1018 int 1019 sdhci_generic_update_ios(device_t brdev, device_t reqdev) 1020 { 1021 struct sdhci_slot *slot = device_get_ivars(reqdev); 1022 struct mmc_ios *ios = &slot->host.ios; 1023 1024 device_printf(brdev, "This is a bridge device\n"); 1025 device_printf(reqdev, "This is a request device\n"); 1026 1027 slot_printf(slot, " <--- The locking slot is this\n"); 1028 SDHCI_LOCK(slot); 1029 /* Do full reset on bus power down to clear from any state. */ 1030 if (ios->power_mode == power_off) { 1031 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1032 sdhci_init(slot); 1033 } 1034 /* Configure the bus. */ 1035 sdhci_set_clock(slot, ios->clock); 1036 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 1037 if (ios->bus_width == bus_width_8) { 1038 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 1039 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1040 } else if (ios->bus_width == bus_width_4) { 1041 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1042 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 1043 } else if (ios->bus_width == bus_width_1) { 1044 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 1045 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 1046 } else { 1047 panic("Invalid bus width: %d", ios->bus_width); 1048 } 1049 if (ios->clock > SD_SDR12_MAX && 1050 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 1051 slot->hostctrl |= SDHCI_CTRL_HISPD; 1052 else 1053 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 1054 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 1055 SDHCI_SET_UHS_TIMING(brdev, slot); 1056 /* Some controllers like reset after bus changes. */ 1057 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 1058 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1059 1060 SDHCI_UNLOCK(slot); 1061 return (0); 1062 } 1063 1064 int 1065 sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) 1066 { 1067 struct sdhci_slot *slot = device_get_ivars(reqdev); 1068 enum mmc_vccq vccq; 1069 int err; 1070 uint16_t hostctrl2; 1071 1072 if (slot->version < SDHCI_SPEC_300) 1073 return (0); 1074 1075 err = 0; 1076 vccq = slot->host.ios.vccq; 1077 SDHCI_LOCK(slot); 1078 sdhci_set_clock(slot, 0); 1079 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1080 switch (vccq) { 1081 case vccq_330: 1082 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1083 goto done; 1084 hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; 1085 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1086 DELAY(5000); 1087 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1088 if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) 1089 goto done; 1090 err = EAGAIN; 1091 break; 1092 case vccq_180: 1093 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { 1094 err = EINVAL; 1095 goto done; 1096 } 1097 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1098 goto done; 1099 hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; 1100 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); 1101 DELAY(5000); 1102 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); 1103 if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) 1104 goto done; 1105 err = EAGAIN; 1106 break; 1107 default: 1108 slot_printf(slot, 1109 "Attempt to set unsupported signaling voltage\n"); 1110 err = EINVAL; 1111 break; 1112 } 1113 done: 1114 sdhci_set_clock(slot, slot->host.ios.clock); 1115 SDHCI_UNLOCK(slot); 1116 return (err); 1117 } 1118 1119 #ifdef MMCCAM 1120 static void 1121 sdhci_req_done(struct sdhci_slot *slot) 1122 { 1123 union ccb *ccb; 1124 if (sdhci_debug > 1) 1125 slot_printf(slot, "sdhci_req_done()\n"); 1126 if (slot->ccb != NULL && slot->curcmd != NULL) { 1127 callout_stop(&slot->timeout_callout); 1128 ccb = slot->ccb; 1129 slot->ccb = NULL; 1130 slot->curcmd = NULL; 1131 1132 /* Tell CAM the request is finished */ 1133 struct ccb_mmcio *mmcio; 1134 mmcio = &ccb->mmcio; 1135 1136 ccb->ccb_h.status = 1137 (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 1138 xpt_done(ccb); 1139 } 1140 } 1141 #else 1142 static void 1143 sdhci_req_done(struct sdhci_slot *slot) 1144 { 1145 struct mmc_request *req; 1146 1147 if (slot->req != NULL && slot->curcmd != NULL) { 1148 callout_stop(&slot->timeout_callout); 1149 req = slot->req; 1150 slot->req = NULL; 1151 slot->curcmd = NULL; 1152 req->done(req); 1153 } 1154 } 1155 #endif 1156 1157 static void 1158 sdhci_timeout(void *arg) 1159 { 1160 struct sdhci_slot *slot = arg; 1161 1162 if (slot->curcmd != NULL) { 1163 slot_printf(slot, " Controller timeout\n"); 1164 sdhci_dumpregs(slot); 1165 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1166 slot->curcmd->error = MMC_ERR_TIMEOUT; 1167 sdhci_req_done(slot); 1168 } else { 1169 slot_printf(slot, " Spurious timeout - no active command\n"); 1170 } 1171 } 1172 1173 static void 1174 sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) 1175 { 1176 uint16_t mode; 1177 1178 if (data == NULL) 1179 return; 1180 1181 mode = SDHCI_TRNS_BLK_CNT_EN; 1182 if (data->len > 512) 1183 mode |= SDHCI_TRNS_MULTI; 1184 if (data->flags & MMC_DATA_READ) 1185 mode |= SDHCI_TRNS_READ; 1186 #ifdef MMCCAM 1187 struct ccb_mmcio *mmcio; 1188 mmcio = &slot->ccb->mmcio; 1189 if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION 1190 && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1191 mode |= SDHCI_TRNS_ACMD12; 1192 #else 1193 if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) 1194 mode |= SDHCI_TRNS_ACMD12; 1195 #endif 1196 if (slot->flags & SDHCI_USE_DMA) 1197 mode |= SDHCI_TRNS_DMA; 1198 1199 WR2(slot, SDHCI_TRANSFER_MODE, mode); 1200 } 1201 1202 static void 1203 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 1204 { 1205 int flags, timeout; 1206 uint32_t mask; 1207 1208 slot->curcmd = cmd; 1209 slot->cmd_done = 0; 1210 1211 cmd->error = MMC_ERR_NONE; 1212 1213 /* This flags combination is not supported by controller. */ 1214 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1215 slot_printf(slot, "Unsupported response type!\n"); 1216 cmd->error = MMC_ERR_FAILED; 1217 sdhci_req_done(slot); 1218 return; 1219 } 1220 1221 /* 1222 * Do not issue command if there is no card, clock or power. 1223 * Controller will not detect timeout without clock active. 1224 */ 1225 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || 1226 slot->power == 0 || 1227 slot->clock == 0) { 1228 slot_printf(slot, 1229 "Cannot issue a command (power=%d clock=%d)", 1230 slot->power, slot->clock); 1231 cmd->error = MMC_ERR_FAILED; 1232 sdhci_req_done(slot); 1233 return; 1234 } 1235 /* Always wait for free CMD bus. */ 1236 mask = SDHCI_CMD_INHIBIT; 1237 /* Wait for free DAT if we have data or busy signal. */ 1238 if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) 1239 mask |= SDHCI_DAT_INHIBIT; 1240 /* We shouldn't wait for DAT for stop commands. */ 1241 #ifdef MMCCAM 1242 struct ccb_mmcio *mmcio = &slot->ccb->mmcio; 1243 if (cmd == &mmcio->stop) 1244 mask &= ~SDHCI_DAT_INHIBIT; 1245 #else 1246 if (cmd == slot->req->stop) 1247 mask &= ~SDHCI_DAT_INHIBIT; 1248 #endif 1249 /* 1250 * Wait for bus no more then 250 ms. Typically there will be no wait 1251 * here at all, but when writing a crash dump we may be bypassing the 1252 * host platform's interrupt handler, and in some cases that handler 1253 * may be working around hardware quirks such as not respecting r1b 1254 * busy indications. In those cases, this wait-loop serves the purpose 1255 * of waiting for the prior command and data transfers to be done, and 1256 * SD cards are allowed to take up to 250ms for write and erase ops. 1257 * (It's usually more like 20-30ms in the real world.) 1258 */ 1259 timeout = 250; 1260 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { 1261 if (timeout == 0) { 1262 slot_printf(slot, "Controller never released " 1263 "inhibit bit(s).\n"); 1264 sdhci_dumpregs(slot); 1265 cmd->error = MMC_ERR_FAILED; 1266 sdhci_req_done(slot); 1267 return; 1268 } 1269 timeout--; 1270 DELAY(1000); 1271 } 1272 1273 /* Prepare command flags. */ 1274 if (!(cmd->flags & MMC_RSP_PRESENT)) 1275 flags = SDHCI_CMD_RESP_NONE; 1276 else if (cmd->flags & MMC_RSP_136) 1277 flags = SDHCI_CMD_RESP_LONG; 1278 else if (cmd->flags & MMC_RSP_BUSY) 1279 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1280 else 1281 flags = SDHCI_CMD_RESP_SHORT; 1282 if (cmd->flags & MMC_RSP_CRC) 1283 flags |= SDHCI_CMD_CRC; 1284 if (cmd->flags & MMC_RSP_OPCODE) 1285 flags |= SDHCI_CMD_INDEX; 1286 if (cmd->data != NULL) 1287 flags |= SDHCI_CMD_DATA; 1288 if (cmd->opcode == MMC_STOP_TRANSMISSION) 1289 flags |= SDHCI_CMD_TYPE_ABORT; 1290 /* Prepare data. */ 1291 sdhci_start_data(slot, cmd->data); 1292 /* 1293 * Interrupt aggregation: To reduce total number of interrupts 1294 * group response interrupt with data interrupt when possible. 1295 * If there going to be data interrupt, mask response one. 1296 */ 1297 if (slot->data_done == 0) { 1298 WR4(slot, SDHCI_SIGNAL_ENABLE, 1299 slot->intmask &= ~SDHCI_INT_RESPONSE); 1300 } 1301 /* Set command argument. */ 1302 WR4(slot, SDHCI_ARGUMENT, cmd->arg); 1303 /* Set data transfer mode. */ 1304 sdhci_set_transfer_mode(slot, cmd->data); 1305 if (sdhci_debug > 1) 1306 slot_printf(slot, "Starting command!\n"); 1307 /* Start command. */ 1308 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 1309 /* Start timeout callout. */ 1310 callout_reset(&slot->timeout_callout, slot->timeout * hz, 1311 sdhci_timeout, slot); 1312 } 1313 1314 static void 1315 sdhci_finish_command(struct sdhci_slot *slot) 1316 { 1317 int i; 1318 uint32_t val; 1319 uint8_t extra; 1320 1321 if (sdhci_debug > 1) 1322 slot_printf(slot, "%s: called, err %d flags %d\n", 1323 __func__, slot->curcmd->error, slot->curcmd->flags); 1324 slot->cmd_done = 1; 1325 /* 1326 * Interrupt aggregation: Restore command interrupt. 1327 * Main restore point for the case when command interrupt 1328 * happened first. 1329 */ 1330 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 1331 /* In case of error - reset host and return. */ 1332 if (slot->curcmd->error) { 1333 sdhci_reset(slot, SDHCI_RESET_CMD); 1334 sdhci_reset(slot, SDHCI_RESET_DATA); 1335 sdhci_start(slot); 1336 return; 1337 } 1338 /* If command has response - fetch it. */ 1339 if (slot->curcmd->flags & MMC_RSP_PRESENT) { 1340 if (slot->curcmd->flags & MMC_RSP_136) { 1341 /* CRC is stripped so we need one byte shift. */ 1342 extra = 0; 1343 for (i = 0; i < 4; i++) { 1344 val = RD4(slot, SDHCI_RESPONSE + i * 4); 1345 if (slot->quirks & 1346 SDHCI_QUIRK_DONT_SHIFT_RESPONSE) 1347 slot->curcmd->resp[3 - i] = val; 1348 else { 1349 slot->curcmd->resp[3 - i] = 1350 (val << 8) | extra; 1351 extra = val >> 24; 1352 } 1353 } 1354 } else 1355 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 1356 } 1357 if (sdhci_debug > 1) 1358 printf("Resp: %02x %02x %02x %02x\n", 1359 slot->curcmd->resp[0], slot->curcmd->resp[1], 1360 slot->curcmd->resp[2], slot->curcmd->resp[3]); 1361 1362 /* If data ready - finish. */ 1363 if (slot->data_done) 1364 sdhci_start(slot); 1365 } 1366 1367 static void 1368 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 1369 { 1370 uint32_t target_timeout, current_timeout; 1371 uint8_t div; 1372 1373 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1374 slot->data_done = 1; 1375 return; 1376 } 1377 1378 slot->data_done = 0; 1379 1380 /* Calculate and set data timeout.*/ 1381 /* XXX: We should have this from mmc layer, now assume 1 sec. */ 1382 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { 1383 div = 0xE; 1384 } else { 1385 target_timeout = 1000000; 1386 div = 0; 1387 current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 1388 while (current_timeout < target_timeout && div < 0xE) { 1389 ++div; 1390 current_timeout <<= 1; 1391 } 1392 /* Compensate for an off-by-one error in the CaFe chip.*/ 1393 if (div < 0xE && 1394 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { 1395 ++div; 1396 } 1397 } 1398 WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 1399 1400 if (data == NULL) 1401 return; 1402 1403 /* Use DMA if possible. */ 1404 if ((slot->opt & SDHCI_HAVE_DMA)) 1405 slot->flags |= SDHCI_USE_DMA; 1406 /* If data is small, broken DMA may return zeroes instead of data, */ 1407 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 1408 (data->len <= 512)) 1409 slot->flags &= ~SDHCI_USE_DMA; 1410 /* Some controllers require even block sizes. */ 1411 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 1412 ((data->len) & 0x3)) 1413 slot->flags &= ~SDHCI_USE_DMA; 1414 /* Load DMA buffer. */ 1415 if (slot->flags & SDHCI_USE_DMA) { 1416 if (data->flags & MMC_DATA_READ) 1417 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1418 BUS_DMASYNC_PREREAD); 1419 else { 1420 memcpy(slot->dmamem, data->data, 1421 (data->len < DMA_BLOCK_SIZE) ? 1422 data->len : DMA_BLOCK_SIZE); 1423 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1424 BUS_DMASYNC_PREWRITE); 1425 } 1426 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1427 /* Interrupt aggregation: Mask border interrupt 1428 * for the last page and unmask else. */ 1429 if (data->len == DMA_BLOCK_SIZE) 1430 slot->intmask &= ~SDHCI_INT_DMA_END; 1431 else 1432 slot->intmask |= SDHCI_INT_DMA_END; 1433 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1434 } 1435 /* Current data offset for both PIO and DMA. */ 1436 slot->offset = 0; 1437 /* Set block size and request IRQ on 4K border. */ 1438 WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, 1439 (data->len < 512) ? data->len : 512)); 1440 /* Set block count. */ 1441 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 1442 1443 if (sdhci_debug > 1) 1444 slot_printf(slot, "Block size: %02x, count %lu\n", (unsigned int) 1445 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512), 1446 (unsigned long)(data->len + 511) / 512); 1447 } 1448 1449 void 1450 sdhci_finish_data(struct sdhci_slot *slot) 1451 { 1452 struct mmc_data *data = slot->curcmd->data; 1453 size_t left; 1454 1455 /* Interrupt aggregation: Restore command interrupt. 1456 * Auxiliary restore point for the case when data interrupt 1457 * happened first. */ 1458 if (!slot->cmd_done) { 1459 WR4(slot, SDHCI_SIGNAL_ENABLE, 1460 slot->intmask |= SDHCI_INT_RESPONSE); 1461 } 1462 /* Unload rest of data from DMA buffer. */ 1463 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && 1464 slot->curcmd->data != NULL) { 1465 if (data->flags & MMC_DATA_READ) { 1466 left = data->len - slot->offset; 1467 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1468 BUS_DMASYNC_POSTREAD); 1469 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1470 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1471 } else 1472 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1473 BUS_DMASYNC_POSTWRITE); 1474 } 1475 slot->data_done = 1; 1476 /* If there was error - reset the host. */ 1477 if (slot->curcmd->error) { 1478 sdhci_reset(slot, SDHCI_RESET_CMD); 1479 sdhci_reset(slot, SDHCI_RESET_DATA); 1480 sdhci_start(slot); 1481 return; 1482 } 1483 /* If we already have command response - finish. */ 1484 if (slot->cmd_done) 1485 sdhci_start(slot); 1486 } 1487 1488 #ifdef MMCCAM 1489 static void 1490 sdhci_start(struct sdhci_slot *slot) 1491 { 1492 union ccb *ccb; 1493 1494 ccb = slot->ccb; 1495 if (ccb == NULL) 1496 return; 1497 1498 struct ccb_mmcio *mmcio; 1499 mmcio = &ccb->mmcio; 1500 1501 if (!(slot->flags & CMD_STARTED)) { 1502 slot->flags |= CMD_STARTED; 1503 sdhci_start_command(slot, &mmcio->cmd); 1504 return; 1505 } 1506 1507 /* 1508 * Old stack doesn't use this! 1509 * Enabling this code causes significant performance degradation 1510 * and IRQ storms on BBB, Wandboard behaves fine. 1511 * Not using this code does no harm... 1512 if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { 1513 slot->flags |= STOP_STARTED; 1514 sdhci_start_command(slot, &mmcio->stop); 1515 return; 1516 } 1517 */ 1518 if (sdhci_debug > 1) 1519 slot_printf(slot, "result: %d\n", mmcio->cmd.error); 1520 if (mmcio->cmd.error == 0 && 1521 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 1522 sdhci_reset(slot, SDHCI_RESET_CMD); 1523 sdhci_reset(slot, SDHCI_RESET_DATA); 1524 } 1525 1526 sdhci_req_done(slot); 1527 } 1528 #else 1529 static void 1530 sdhci_start(struct sdhci_slot *slot) 1531 { 1532 struct mmc_request *req; 1533 1534 req = slot->req; 1535 if (req == NULL) 1536 return; 1537 1538 if (!(slot->flags & CMD_STARTED)) { 1539 slot->flags |= CMD_STARTED; 1540 sdhci_start_command(slot, req->cmd); 1541 return; 1542 } 1543 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && 1544 !(slot->flags & STOP_STARTED) && req->stop) { 1545 slot->flags |= STOP_STARTED; 1546 sdhci_start_command(slot, req->stop); 1547 return; 1548 } 1549 if (sdhci_debug > 1) 1550 slot_printf(slot, "result: %d\n", req->cmd->error); 1551 if (!req->cmd->error && 1552 ((slot->curcmd == req->stop && 1553 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || 1554 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1555 sdhci_reset(slot, SDHCI_RESET_CMD); 1556 sdhci_reset(slot, SDHCI_RESET_DATA); 1557 } 1558 1559 sdhci_req_done(slot); 1560 } 1561 #endif 1562 1563 int 1564 sdhci_generic_request(device_t brdev __unused, device_t reqdev, 1565 struct mmc_request *req) 1566 { 1567 struct sdhci_slot *slot = device_get_ivars(reqdev); 1568 1569 SDHCI_LOCK(slot); 1570 if (slot->req != NULL) { 1571 SDHCI_UNLOCK(slot); 1572 return (EBUSY); 1573 } 1574 if (sdhci_debug > 1) { 1575 slot_printf(slot, 1576 "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1577 req->cmd->opcode, req->cmd->arg, req->cmd->flags, 1578 (req->cmd->data)?(u_int)req->cmd->data->len:0, 1579 (req->cmd->data)?req->cmd->data->flags:0); 1580 } 1581 slot->req = req; 1582 slot->flags = 0; 1583 sdhci_start(slot); 1584 SDHCI_UNLOCK(slot); 1585 if (dumping) { 1586 while (slot->req != NULL) { 1587 sdhci_generic_intr(slot); 1588 DELAY(10); 1589 } 1590 } 1591 return (0); 1592 } 1593 1594 int 1595 sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) 1596 { 1597 struct sdhci_slot *slot = device_get_ivars(reqdev); 1598 uint32_t val; 1599 1600 SDHCI_LOCK(slot); 1601 val = RD4(slot, SDHCI_PRESENT_STATE); 1602 SDHCI_UNLOCK(slot); 1603 return (!(val & SDHCI_WRITE_PROTECT)); 1604 } 1605 1606 int 1607 sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) 1608 { 1609 struct sdhci_slot *slot = device_get_ivars(reqdev); 1610 int err = 0; 1611 1612 SDHCI_LOCK(slot); 1613 while (slot->bus_busy) 1614 msleep(slot, &slot->mtx, 0, "sdhciah", 0); 1615 slot->bus_busy++; 1616 /* Activate led. */ 1617 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 1618 SDHCI_UNLOCK(slot); 1619 return (err); 1620 } 1621 1622 int 1623 sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) 1624 { 1625 struct sdhci_slot *slot = device_get_ivars(reqdev); 1626 1627 SDHCI_LOCK(slot); 1628 /* Deactivate led. */ 1629 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 1630 slot->bus_busy--; 1631 SDHCI_UNLOCK(slot); 1632 wakeup(slot); 1633 return (0); 1634 } 1635 1636 static void 1637 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1638 { 1639 1640 if (!slot->curcmd) { 1641 slot_printf(slot, "Got command interrupt 0x%08x, but " 1642 "there is no active command.\n", intmask); 1643 sdhci_dumpregs(slot); 1644 return; 1645 } 1646 if (intmask & SDHCI_INT_TIMEOUT) 1647 slot->curcmd->error = MMC_ERR_TIMEOUT; 1648 else if (intmask & SDHCI_INT_CRC) 1649 slot->curcmd->error = MMC_ERR_BADCRC; 1650 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1651 slot->curcmd->error = MMC_ERR_FIFO; 1652 1653 sdhci_finish_command(slot); 1654 } 1655 1656 static void 1657 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1658 { 1659 struct mmc_data *data; 1660 1661 if (!slot->curcmd) { 1662 slot_printf(slot, "Got data interrupt 0x%08x, but " 1663 "there is no active command.\n", intmask); 1664 sdhci_dumpregs(slot); 1665 return; 1666 } 1667 if (slot->curcmd->data == NULL && 1668 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1669 slot_printf(slot, "Got data interrupt 0x%08x, but " 1670 "there is no active data operation.\n", 1671 intmask); 1672 sdhci_dumpregs(slot); 1673 return; 1674 } 1675 if (intmask & SDHCI_INT_DATA_TIMEOUT) 1676 slot->curcmd->error = MMC_ERR_TIMEOUT; 1677 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1678 slot->curcmd->error = MMC_ERR_BADCRC; 1679 if (slot->curcmd->data == NULL && 1680 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1681 SDHCI_INT_DMA_END))) { 1682 slot_printf(slot, "Got data interrupt 0x%08x, but " 1683 "there is busy-only command.\n", intmask); 1684 sdhci_dumpregs(slot); 1685 slot->curcmd->error = MMC_ERR_INVALID; 1686 } 1687 if (slot->curcmd->error) { 1688 /* No need to continue after any error. */ 1689 goto done; 1690 } 1691 1692 /* Handle PIO interrupt. */ 1693 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { 1694 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && 1695 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { 1696 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, 1697 &intmask); 1698 slot->flags |= PLATFORM_DATA_STARTED; 1699 } else 1700 sdhci_transfer_pio(slot); 1701 } 1702 /* Handle DMA border. */ 1703 if (intmask & SDHCI_INT_DMA_END) { 1704 data = slot->curcmd->data; 1705 size_t left; 1706 1707 /* Unload DMA buffer ... */ 1708 left = data->len - slot->offset; 1709 if (data->flags & MMC_DATA_READ) { 1710 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1711 BUS_DMASYNC_POSTREAD); 1712 memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1713 (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); 1714 } else { 1715 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1716 BUS_DMASYNC_POSTWRITE); 1717 } 1718 /* ... and reload it again. */ 1719 slot->offset += DMA_BLOCK_SIZE; 1720 left = data->len - slot->offset; 1721 if (data->flags & MMC_DATA_READ) { 1722 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1723 BUS_DMASYNC_PREREAD); 1724 } else { 1725 memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1726 (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); 1727 bus_dmamap_sync(slot->dmatag, slot->dmamap, 1728 BUS_DMASYNC_PREWRITE); 1729 } 1730 /* Interrupt aggregation: Mask border interrupt 1731 * for the last page. */ 1732 if (left == DMA_BLOCK_SIZE) { 1733 slot->intmask &= ~SDHCI_INT_DMA_END; 1734 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1735 } 1736 /* Restart DMA. */ 1737 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1738 } 1739 /* We have got all data. */ 1740 if (intmask & SDHCI_INT_DATA_END) { 1741 if (slot->flags & PLATFORM_DATA_STARTED) { 1742 slot->flags &= ~PLATFORM_DATA_STARTED; 1743 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1744 } else 1745 sdhci_finish_data(slot); 1746 } 1747 done: 1748 if (slot->curcmd != NULL && slot->curcmd->error != 0) { 1749 if (slot->flags & PLATFORM_DATA_STARTED) { 1750 slot->flags &= ~PLATFORM_DATA_STARTED; 1751 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); 1752 } else 1753 sdhci_finish_data(slot); 1754 } 1755 } 1756 1757 static void 1758 sdhci_acmd_irq(struct sdhci_slot *slot) 1759 { 1760 uint16_t err; 1761 1762 err = RD4(slot, SDHCI_ACMD12_ERR); 1763 if (!slot->curcmd) { 1764 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1765 "there is no active command.\n", err); 1766 sdhci_dumpregs(slot); 1767 return; 1768 } 1769 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1770 sdhci_reset(slot, SDHCI_RESET_CMD); 1771 } 1772 1773 void 1774 sdhci_generic_intr(struct sdhci_slot *slot) 1775 { 1776 uint32_t intmask, present; 1777 1778 SDHCI_LOCK(slot); 1779 /* Read slot interrupt status. */ 1780 intmask = RD4(slot, SDHCI_INT_STATUS); 1781 if (intmask == 0 || intmask == 0xffffffff) { 1782 SDHCI_UNLOCK(slot); 1783 return; 1784 } 1785 if (sdhci_debug > 2) 1786 slot_printf(slot, "Interrupt %#x\n", intmask); 1787 1788 /* Handle card presence interrupts. */ 1789 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1790 present = (intmask & SDHCI_INT_CARD_INSERT) != 0; 1791 slot->intmask &= 1792 ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1793 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : 1794 SDHCI_INT_CARD_INSERT; 1795 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1796 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1797 WR4(slot, SDHCI_INT_STATUS, intmask & 1798 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1799 sdhci_handle_card_present_locked(slot, present); 1800 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1801 } 1802 /* Handle command interrupts. */ 1803 if (intmask & SDHCI_INT_CMD_MASK) { 1804 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1805 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1806 } 1807 /* Handle data interrupts. */ 1808 if (intmask & SDHCI_INT_DATA_MASK) { 1809 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1810 /* Don't call data_irq in case of errored command. */ 1811 if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) 1812 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1813 } 1814 /* Handle AutoCMD12 error interrupt. */ 1815 if (intmask & SDHCI_INT_ACMD12ERR) { 1816 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1817 sdhci_acmd_irq(slot); 1818 } 1819 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1820 intmask &= ~SDHCI_INT_ACMD12ERR; 1821 intmask &= ~SDHCI_INT_ERROR; 1822 /* Handle bus power interrupt. */ 1823 if (intmask & SDHCI_INT_BUS_POWER) { 1824 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1825 slot_printf(slot, 1826 "Card is consuming too much power!\n"); 1827 intmask &= ~SDHCI_INT_BUS_POWER; 1828 } 1829 /* Handle card interrupt. */ 1830 if (intmask & SDHCI_INT_CARD_INT) { 1831 1832 } 1833 /* The rest is unknown. */ 1834 if (intmask) { 1835 WR4(slot, SDHCI_INT_STATUS, intmask); 1836 slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1837 intmask); 1838 sdhci_dumpregs(slot); 1839 } 1840 1841 SDHCI_UNLOCK(slot); 1842 } 1843 1844 int 1845 sdhci_generic_read_ivar(device_t bus, device_t child, int which, 1846 uintptr_t *result) 1847 { 1848 struct sdhci_slot *slot = device_get_ivars(child); 1849 1850 switch (which) { 1851 default: 1852 return (EINVAL); 1853 case MMCBR_IVAR_BUS_MODE: 1854 *result = slot->host.ios.bus_mode; 1855 break; 1856 case MMCBR_IVAR_BUS_WIDTH: 1857 *result = slot->host.ios.bus_width; 1858 break; 1859 case MMCBR_IVAR_CHIP_SELECT: 1860 *result = slot->host.ios.chip_select; 1861 break; 1862 case MMCBR_IVAR_CLOCK: 1863 *result = slot->host.ios.clock; 1864 break; 1865 case MMCBR_IVAR_F_MIN: 1866 *result = slot->host.f_min; 1867 break; 1868 case MMCBR_IVAR_F_MAX: 1869 *result = slot->host.f_max; 1870 break; 1871 case MMCBR_IVAR_HOST_OCR: 1872 *result = slot->host.host_ocr; 1873 break; 1874 case MMCBR_IVAR_MODE: 1875 *result = slot->host.mode; 1876 break; 1877 case MMCBR_IVAR_OCR: 1878 *result = slot->host.ocr; 1879 break; 1880 case MMCBR_IVAR_POWER_MODE: 1881 *result = slot->host.ios.power_mode; 1882 break; 1883 case MMCBR_IVAR_VDD: 1884 *result = slot->host.ios.vdd; 1885 break; 1886 case MMCBR_IVAR_VCCQ: 1887 *result = slot->host.ios.vccq; 1888 break; 1889 case MMCBR_IVAR_CAPS: 1890 *result = slot->host.caps; 1891 break; 1892 case MMCBR_IVAR_TIMING: 1893 *result = slot->host.ios.timing; 1894 break; 1895 case MMCBR_IVAR_MAX_DATA: 1896 *result = 65535; 1897 break; 1898 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: 1899 /* 1900 * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. 1901 */ 1902 *result = 1000000; 1903 break; 1904 } 1905 return (0); 1906 } 1907 1908 int 1909 sdhci_generic_write_ivar(device_t bus, device_t child, int which, 1910 uintptr_t value) 1911 { 1912 struct sdhci_slot *slot = device_get_ivars(child); 1913 uint32_t clock, max_clock; 1914 int i; 1915 1916 slot_printf(slot, "sdhci_generic_write_ivar, var=%d\n", which); 1917 switch (which) { 1918 default: 1919 return (EINVAL); 1920 case MMCBR_IVAR_BUS_MODE: 1921 slot->host.ios.bus_mode = value; 1922 break; 1923 case MMCBR_IVAR_BUS_WIDTH: 1924 slot->host.ios.bus_width = value; 1925 break; 1926 case MMCBR_IVAR_CHIP_SELECT: 1927 slot->host.ios.chip_select = value; 1928 break; 1929 case MMCBR_IVAR_CLOCK: 1930 if (value > 0) { 1931 max_clock = slot->max_clk; 1932 clock = max_clock; 1933 1934 if (slot->version < SDHCI_SPEC_300) { 1935 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 1936 i <<= 1) { 1937 if (clock <= value) 1938 break; 1939 clock >>= 1; 1940 } 1941 } else { 1942 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 1943 i += 2) { 1944 if (clock <= value) 1945 break; 1946 clock = max_clock / (i + 2); 1947 } 1948 } 1949 1950 slot->host.ios.clock = clock; 1951 } else 1952 slot->host.ios.clock = 0; 1953 break; 1954 case MMCBR_IVAR_MODE: 1955 slot->host.mode = value; 1956 break; 1957 case MMCBR_IVAR_OCR: 1958 slot->host.ocr = value; 1959 break; 1960 case MMCBR_IVAR_POWER_MODE: 1961 slot->host.ios.power_mode = value; 1962 break; 1963 case MMCBR_IVAR_VDD: 1964 slot->host.ios.vdd = value; 1965 break; 1966 case MMCBR_IVAR_VCCQ: 1967 slot->host.ios.vccq = value; 1968 break; 1969 case MMCBR_IVAR_TIMING: 1970 slot->host.ios.timing = value; 1971 break; 1972 case MMCBR_IVAR_CAPS: 1973 case MMCBR_IVAR_HOST_OCR: 1974 case MMCBR_IVAR_F_MIN: 1975 case MMCBR_IVAR_F_MAX: 1976 case MMCBR_IVAR_MAX_DATA: 1977 return (EINVAL); 1978 } 1979 return (0); 1980 } 1981 1982 /* CAM-related functions */ 1983 #include <cam/cam.h> 1984 #include <cam/cam_ccb.h> 1985 #include <cam/cam_debug.h> 1986 #include <cam/cam_sim.h> 1987 #include <cam/cam_xpt_sim.h> 1988 1989 void 1990 sdhci_cam_start_slot(struct sdhci_slot *slot) 1991 { 1992 if ((slot->devq = cam_simq_alloc(1)) == NULL) { 1993 goto fail; 1994 } 1995 1996 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); 1997 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, 1998 "sdhci_slot", slot, device_get_unit(slot->bus), 1999 &slot->sim_mtx, 1, 1, slot->devq); 2000 2001 if (slot->sim == NULL) { 2002 cam_simq_free(slot->devq); 2003 slot_printf(slot, "cannot allocate CAM SIM\n"); 2004 goto fail; 2005 } 2006 2007 mtx_lock(&slot->sim_mtx); 2008 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { 2009 slot_printf(slot, 2010 "cannot register SCSI pass-through bus\n"); 2011 cam_sim_free(slot->sim, FALSE); 2012 cam_simq_free(slot->devq); 2013 mtx_unlock(&slot->sim_mtx); 2014 goto fail; 2015 } 2016 2017 mtx_unlock(&slot->sim_mtx); 2018 /* End CAM-specific init */ 2019 slot->card_present = 0; 2020 sdhci_card_task(slot, 0); 2021 return; 2022 2023 fail: 2024 if (slot->sim != NULL) { 2025 mtx_lock(&slot->sim_mtx); 2026 xpt_bus_deregister(cam_sim_path(slot->sim)); 2027 cam_sim_free(slot->sim, FALSE); 2028 mtx_unlock(&slot->sim_mtx); 2029 } 2030 2031 if (slot->devq != NULL) 2032 cam_simq_free(slot->devq); 2033 } 2034 2035 static void 2036 sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) 2037 { 2038 struct sdhci_slot *slot; 2039 2040 slot = cam_sim_softc(sim); 2041 2042 sdhci_cam_request(slot, ccb); 2043 } 2044 2045 void 2046 sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) 2047 { 2048 struct sdhci_slot *slot; 2049 2050 slot = cam_sim_softc(sim); 2051 if (slot == NULL) { 2052 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2053 xpt_done(ccb); 2054 return; 2055 } 2056 2057 mtx_assert(&slot->sim_mtx, MA_OWNED); 2058 2059 switch (ccb->ccb_h.func_code) { 2060 case XPT_PATH_INQ: 2061 { 2062 struct ccb_pathinq *cpi; 2063 2064 cpi = &ccb->cpi; 2065 cpi->version_num = 1; 2066 cpi->hba_inquiry = 0; 2067 cpi->target_sprt = 0; 2068 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2069 cpi->hba_eng_cnt = 0; 2070 cpi->max_target = 0; 2071 cpi->max_lun = 0; 2072 cpi->initiator_id = 1; 2073 cpi->maxio = MAXPHYS; 2074 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2075 strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); 2076 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2077 cpi->unit_number = cam_sim_unit(sim); 2078 cpi->bus_id = cam_sim_bus(sim); 2079 cpi->base_transfer_speed = 100; /* XXX WTF? */ 2080 cpi->protocol = PROTO_MMCSD; 2081 cpi->protocol_version = SCSI_REV_0; 2082 cpi->transport = XPORT_MMCSD; 2083 cpi->transport_version = 0; 2084 2085 cpi->ccb_h.status = CAM_REQ_CMP; 2086 break; 2087 } 2088 case XPT_GET_TRAN_SETTINGS: 2089 { 2090 struct ccb_trans_settings *cts = &ccb->cts; 2091 2092 if (sdhci_debug > 1) 2093 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); 2094 2095 cts->protocol = PROTO_MMCSD; 2096 cts->protocol_version = 1; 2097 cts->transport = XPORT_MMCSD; 2098 cts->transport_version = 1; 2099 cts->xport_specific.valid = 0; 2100 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; 2101 cts->proto_specific.mmc.host_f_min = slot->host.f_min; 2102 cts->proto_specific.mmc.host_f_max = slot->host.f_max; 2103 cts->proto_specific.mmc.host_caps = slot->host.caps; 2104 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); 2105 ccb->ccb_h.status = CAM_REQ_CMP; 2106 break; 2107 } 2108 case XPT_SET_TRAN_SETTINGS: 2109 { 2110 if (sdhci_debug > 1) 2111 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); 2112 sdhci_cam_settran_settings(slot, ccb); 2113 ccb->ccb_h.status = CAM_REQ_CMP; 2114 break; 2115 } 2116 case XPT_RESET_BUS: 2117 if (sdhci_debug > 1) 2118 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); 2119 ccb->ccb_h.status = CAM_REQ_CMP; 2120 break; 2121 case XPT_MMC_IO: 2122 /* 2123 * Here is the HW-dependent part of 2124 * sending the command to the underlying h/w 2125 * At some point in the future an interrupt comes. 2126 * Then the request will be marked as completed. 2127 */ 2128 if (sdhci_debug > 1) 2129 slot_printf(slot, "Got XPT_MMC_IO\n"); 2130 ccb->ccb_h.status = CAM_REQ_INPROG; 2131 2132 sdhci_cam_handle_mmcio(sim, ccb); 2133 return; 2134 /* NOTREACHED */ 2135 break; 2136 default: 2137 ccb->ccb_h.status = CAM_REQ_INVALID; 2138 break; 2139 } 2140 xpt_done(ccb); 2141 return; 2142 } 2143 2144 void 2145 sdhci_cam_poll(struct cam_sim *sim) 2146 { 2147 return; 2148 } 2149 2150 int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) { 2151 int max_clock, clock, i; 2152 2153 if (proposed_clock == 0) 2154 return 0; 2155 max_clock = slot->max_clk; 2156 clock = max_clock; 2157 2158 if (slot->version < SDHCI_SPEC_300) { 2159 for (i = 0; i < SDHCI_200_MAX_DIVIDER; 2160 i <<= 1) { 2161 if (clock <= proposed_clock) 2162 break; 2163 clock >>= 1; 2164 } 2165 } else { 2166 for (i = 0; i < SDHCI_300_MAX_DIVIDER; 2167 i += 2) { 2168 if (clock <= proposed_clock) 2169 break; 2170 clock = max_clock / (i + 2); 2171 } 2172 } 2173 return clock; 2174 } 2175 2176 int 2177 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) 2178 { 2179 struct mmc_ios *ios; 2180 struct mmc_ios *new_ios; 2181 struct ccb_trans_settings_mmc *cts; 2182 2183 ios = &slot->host.ios; 2184 2185 cts = &ccb->cts.proto_specific.mmc; 2186 new_ios = &cts->ios; 2187 2188 /* Update only requested fields */ 2189 if (cts->ios_valid & MMC_CLK) { 2190 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); 2191 slot_printf(slot, "Clock => %d\n", ios->clock); 2192 } 2193 if (cts->ios_valid & MMC_VDD) { 2194 ios->vdd = new_ios->vdd; 2195 slot_printf(slot, "VDD => %d\n", ios->vdd); 2196 } 2197 if (cts->ios_valid & MMC_CS) { 2198 ios->chip_select = new_ios->chip_select; 2199 slot_printf(slot, "CS => %d\n", ios->chip_select); 2200 } 2201 if (cts->ios_valid & MMC_BW) { 2202 ios->bus_width = new_ios->bus_width; 2203 slot_printf(slot, "Bus width => %d\n", ios->bus_width); 2204 } 2205 if (cts->ios_valid & MMC_PM) { 2206 ios->power_mode = new_ios->power_mode; 2207 slot_printf(slot, "Power mode => %d\n", ios->power_mode); 2208 } 2209 if (cts->ios_valid & MMC_BT) { 2210 ios->timing = new_ios->timing; 2211 slot_printf(slot, "Timing => %d\n", ios->timing); 2212 } 2213 if (cts->ios_valid & MMC_BM) { 2214 ios->bus_mode = new_ios->bus_mode; 2215 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); 2216 } 2217 2218 /* XXX Provide a way to call a chip-specific IOS update, required for TI */ 2219 return (sdhci_cam_update_ios(slot)); 2220 } 2221 2222 int 2223 sdhci_cam_update_ios(struct sdhci_slot *slot) 2224 { 2225 struct mmc_ios *ios = &slot->host.ios; 2226 2227 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", 2228 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); 2229 SDHCI_LOCK(slot); 2230 /* Do full reset on bus power down to clear from any state. */ 2231 if (ios->power_mode == power_off) { 2232 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 2233 sdhci_init(slot); 2234 } 2235 /* Configure the bus. */ 2236 sdhci_set_clock(slot, ios->clock); 2237 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); 2238 if (ios->bus_width == bus_width_8) { 2239 slot->hostctrl |= SDHCI_CTRL_8BITBUS; 2240 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2241 } else if (ios->bus_width == bus_width_4) { 2242 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2243 slot->hostctrl |= SDHCI_CTRL_4BITBUS; 2244 } else if (ios->bus_width == bus_width_1) { 2245 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; 2246 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 2247 } else { 2248 panic("Invalid bus width: %d", ios->bus_width); 2249 } 2250 if (ios->timing == bus_timing_hs && 2251 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) 2252 slot->hostctrl |= SDHCI_CTRL_HISPD; 2253 else 2254 slot->hostctrl &= ~SDHCI_CTRL_HISPD; 2255 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 2256 /* Some controllers like reset after bus changes. */ 2257 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 2258 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2259 2260 SDHCI_UNLOCK(slot); 2261 return (0); 2262 } 2263 2264 int 2265 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) 2266 { 2267 struct ccb_mmcio *mmcio; 2268 2269 mmcio = &ccb->mmcio; 2270 2271 SDHCI_LOCK(slot); 2272 /* if (slot->req != NULL) { 2273 SDHCI_UNLOCK(slot); 2274 return (EBUSY); 2275 } 2276 */ 2277 if (sdhci_debug > 1) { 2278 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 2279 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 2280 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 2281 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 2282 } 2283 if (mmcio->cmd.data != NULL) { 2284 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 2285 panic("data->len = %d, data->flags = %d -- something is b0rked", 2286 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 2287 } 2288 slot->ccb = ccb; 2289 slot->flags = 0; 2290 sdhci_start(slot); 2291 SDHCI_UNLOCK(slot); 2292 if (dumping) { 2293 while (slot->ccb != NULL) { 2294 sdhci_generic_intr(slot); 2295 DELAY(10); 2296 } 2297 } 2298 return (0); 2299 } 2300 2301 MODULE_VERSION(sdhci, 1); 2302