1831f5dcfSAlexander Motin /*- 2831f5dcfSAlexander Motin * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3831f5dcfSAlexander Motin * All rights reserved. 4831f5dcfSAlexander Motin * 5831f5dcfSAlexander Motin * Redistribution and use in source and binary forms, with or without 6831f5dcfSAlexander Motin * modification, are permitted provided that the following conditions 7831f5dcfSAlexander Motin * are met: 8831f5dcfSAlexander Motin * 1. Redistributions of source code must retain the above copyright 9831f5dcfSAlexander Motin * notice, this list of conditions and the following disclaimer. 10831f5dcfSAlexander Motin * 2. Redistributions in binary form must reproduce the above copyright 11831f5dcfSAlexander Motin * notice, this list of conditions and the following disclaimer in the 12831f5dcfSAlexander Motin * documentation and/or other materials provided with the distribution. 13831f5dcfSAlexander Motin * 14831f5dcfSAlexander Motin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15831f5dcfSAlexander Motin * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16831f5dcfSAlexander Motin * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17831f5dcfSAlexander Motin * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18831f5dcfSAlexander Motin * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19831f5dcfSAlexander Motin * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20831f5dcfSAlexander Motin * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21831f5dcfSAlexander Motin * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22831f5dcfSAlexander Motin * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23831f5dcfSAlexander Motin * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24831f5dcfSAlexander Motin */ 25831f5dcfSAlexander Motin 26831f5dcfSAlexander Motin #include <sys/cdefs.h> 27831f5dcfSAlexander Motin __FBSDID("$FreeBSD$"); 28831f5dcfSAlexander Motin 29831f5dcfSAlexander Motin #include <sys/param.h> 30831f5dcfSAlexander Motin #include <sys/systm.h> 31831f5dcfSAlexander Motin #include <sys/bus.h> 32831f5dcfSAlexander Motin #include <sys/conf.h> 33831f5dcfSAlexander Motin #include <sys/kernel.h> 34831f5dcfSAlexander Motin #include <sys/lock.h> 35831f5dcfSAlexander Motin #include <sys/module.h> 36831f5dcfSAlexander Motin #include <sys/mutex.h> 37831f5dcfSAlexander Motin #include <sys/resource.h> 38831f5dcfSAlexander Motin #include <sys/rman.h> 395b69a497SAlexander Motin #include <sys/sysctl.h> 40831f5dcfSAlexander Motin #include <sys/taskqueue.h> 41831f5dcfSAlexander Motin 42831f5dcfSAlexander Motin #include <machine/bus.h> 43831f5dcfSAlexander Motin #include <machine/resource.h> 44831f5dcfSAlexander Motin #include <machine/stdarg.h> 45831f5dcfSAlexander Motin 46831f5dcfSAlexander Motin #include <dev/mmc/bridge.h> 47831f5dcfSAlexander Motin #include <dev/mmc/mmcreg.h> 48831f5dcfSAlexander Motin #include <dev/mmc/mmcbrvar.h> 49831f5dcfSAlexander Motin 50831f5dcfSAlexander Motin #include "mmcbr_if.h" 51831f5dcfSAlexander Motin #include "sdhci.h" 52*d6b3aaf8SOleksandr Tymoshenko #include "sdhci_if.h" 53831f5dcfSAlexander Motin 54831f5dcfSAlexander Motin struct sdhci_softc; 55831f5dcfSAlexander Motin 56831f5dcfSAlexander Motin struct sdhci_softc { 57831f5dcfSAlexander Motin device_t dev; /* Controller device */ 58831f5dcfSAlexander Motin struct resource *irq_res; /* IRQ resource */ 59831f5dcfSAlexander Motin int irq_rid; 60831f5dcfSAlexander Motin void *intrhand; /* Interrupt handle */ 61831f5dcfSAlexander Motin 62831f5dcfSAlexander Motin int num_slots; /* Number of slots on this controller */ 63831f5dcfSAlexander Motin struct sdhci_slot slots[6]; 64831f5dcfSAlexander Motin }; 65831f5dcfSAlexander Motin 666472ac3dSEd Schouten static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); 675b69a497SAlexander Motin 68*d6b3aaf8SOleksandr Tymoshenko int sdhci_debug = 0; 695b69a497SAlexander Motin TUNABLE_INT("hw.sdhci.debug", &sdhci_debug); 705b69a497SAlexander Motin SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level"); 715b69a497SAlexander Motin 72*d6b3aaf8SOleksandr Tymoshenko #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) 73*d6b3aaf8SOleksandr Tymoshenko #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) 74*d6b3aaf8SOleksandr Tymoshenko #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) 75*d6b3aaf8SOleksandr Tymoshenko #define RD_MULTI_4(slot, off, ptr, count) \ 76*d6b3aaf8SOleksandr Tymoshenko SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 77831f5dcfSAlexander Motin 78*d6b3aaf8SOleksandr Tymoshenko #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) 79*d6b3aaf8SOleksandr Tymoshenko #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) 80*d6b3aaf8SOleksandr Tymoshenko #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) 81*d6b3aaf8SOleksandr Tymoshenko #define WR_MULTI_4(slot, off, ptr, count) \ 82*d6b3aaf8SOleksandr Tymoshenko SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) 83831f5dcfSAlexander Motin 84831f5dcfSAlexander Motin static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); 85831f5dcfSAlexander Motin static void sdhci_start(struct sdhci_slot *slot); 86831f5dcfSAlexander Motin static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); 87831f5dcfSAlexander Motin 88831f5dcfSAlexander Motin static void sdhci_card_task(void *, int); 89831f5dcfSAlexander Motin 90831f5dcfSAlexander Motin /* helper routines */ 91831f5dcfSAlexander Motin #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) 92831f5dcfSAlexander Motin #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) 93831f5dcfSAlexander Motin #define SDHCI_LOCK_INIT(_slot) \ 94831f5dcfSAlexander Motin mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) 95831f5dcfSAlexander Motin #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); 96831f5dcfSAlexander Motin #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); 97831f5dcfSAlexander Motin #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); 98831f5dcfSAlexander Motin 99831f5dcfSAlexander Motin static void 100831f5dcfSAlexander Motin sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 101831f5dcfSAlexander Motin { 102831f5dcfSAlexander Motin if (error != 0) { 103831f5dcfSAlexander Motin printf("getaddr: error %d\n", error); 104831f5dcfSAlexander Motin return; 105831f5dcfSAlexander Motin } 106831f5dcfSAlexander Motin *(bus_addr_t *)arg = segs[0].ds_addr; 107831f5dcfSAlexander Motin } 108831f5dcfSAlexander Motin 109*d6b3aaf8SOleksandr Tymoshenko static int 110*d6b3aaf8SOleksandr Tymoshenko slot_printf(struct sdhci_slot *slot, const char * fmt, ...) 111*d6b3aaf8SOleksandr Tymoshenko { 112*d6b3aaf8SOleksandr Tymoshenko va_list ap; 113*d6b3aaf8SOleksandr Tymoshenko int retval; 114*d6b3aaf8SOleksandr Tymoshenko 115*d6b3aaf8SOleksandr Tymoshenko retval = printf("%s-slot%d: ", 116*d6b3aaf8SOleksandr Tymoshenko device_get_nameunit(slot->bus), slot->num); 117*d6b3aaf8SOleksandr Tymoshenko 118*d6b3aaf8SOleksandr Tymoshenko va_start(ap, fmt); 119*d6b3aaf8SOleksandr Tymoshenko retval += vprintf(fmt, ap); 120*d6b3aaf8SOleksandr Tymoshenko va_end(ap); 121*d6b3aaf8SOleksandr Tymoshenko return (retval); 122*d6b3aaf8SOleksandr Tymoshenko } 123*d6b3aaf8SOleksandr Tymoshenko 124831f5dcfSAlexander Motin static void 125831f5dcfSAlexander Motin sdhci_dumpregs(struct sdhci_slot *slot) 126831f5dcfSAlexander Motin { 127831f5dcfSAlexander Motin slot_printf(slot, 128831f5dcfSAlexander Motin "============== REGISTER DUMP ==============\n"); 129831f5dcfSAlexander Motin 130831f5dcfSAlexander Motin slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", 131831f5dcfSAlexander Motin RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 132831f5dcfSAlexander Motin slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", 133831f5dcfSAlexander Motin RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); 134831f5dcfSAlexander Motin slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", 135831f5dcfSAlexander Motin RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 136831f5dcfSAlexander Motin slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", 137831f5dcfSAlexander Motin RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 138831f5dcfSAlexander Motin slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", 139831f5dcfSAlexander Motin RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); 140831f5dcfSAlexander Motin slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", 141831f5dcfSAlexander Motin RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); 142831f5dcfSAlexander Motin slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", 143831f5dcfSAlexander Motin RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 144831f5dcfSAlexander Motin slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", 145831f5dcfSAlexander Motin RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 146831f5dcfSAlexander Motin slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n", 147831f5dcfSAlexander Motin RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS)); 148831f5dcfSAlexander Motin slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n", 149831f5dcfSAlexander Motin RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 150831f5dcfSAlexander Motin 151831f5dcfSAlexander Motin slot_printf(slot, 152831f5dcfSAlexander Motin "===========================================\n"); 153831f5dcfSAlexander Motin } 154831f5dcfSAlexander Motin 155831f5dcfSAlexander Motin static void 156831f5dcfSAlexander Motin sdhci_reset(struct sdhci_slot *slot, uint8_t mask) 157831f5dcfSAlexander Motin { 158831f5dcfSAlexander Motin int timeout; 159831f5dcfSAlexander Motin uint8_t res; 160831f5dcfSAlexander Motin 161*d6b3aaf8SOleksandr Tymoshenko if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 162831f5dcfSAlexander Motin if (!(RD4(slot, SDHCI_PRESENT_STATE) & 163831f5dcfSAlexander Motin SDHCI_CARD_PRESENT)) 164831f5dcfSAlexander Motin return; 165831f5dcfSAlexander Motin } 166831f5dcfSAlexander Motin 167831f5dcfSAlexander Motin /* Some controllers need this kick or reset won't work. */ 168831f5dcfSAlexander Motin if ((mask & SDHCI_RESET_ALL) == 0 && 169*d6b3aaf8SOleksandr Tymoshenko (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { 170831f5dcfSAlexander Motin uint32_t clock; 171831f5dcfSAlexander Motin 172831f5dcfSAlexander Motin /* This is to force an update */ 173831f5dcfSAlexander Motin clock = slot->clock; 174831f5dcfSAlexander Motin slot->clock = 0; 175831f5dcfSAlexander Motin sdhci_set_clock(slot, clock); 176831f5dcfSAlexander Motin } 177831f5dcfSAlexander Motin 178831f5dcfSAlexander Motin WR1(slot, SDHCI_SOFTWARE_RESET, mask); 179831f5dcfSAlexander Motin 180d8208d9eSAlexander Motin if (mask & SDHCI_RESET_ALL) { 181831f5dcfSAlexander Motin slot->clock = 0; 182d8208d9eSAlexander Motin slot->power = 0; 183d8208d9eSAlexander Motin } 184831f5dcfSAlexander Motin 185831f5dcfSAlexander Motin /* Wait max 100 ms */ 186831f5dcfSAlexander Motin timeout = 100; 187831f5dcfSAlexander Motin /* Controller clears the bits when it's done */ 188831f5dcfSAlexander Motin while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) { 189831f5dcfSAlexander Motin if (timeout == 0) { 190831f5dcfSAlexander Motin slot_printf(slot, 191831f5dcfSAlexander Motin "Reset 0x%x never completed - 0x%x.\n", 192831f5dcfSAlexander Motin (int)mask, (int)res); 193831f5dcfSAlexander Motin sdhci_dumpregs(slot); 194831f5dcfSAlexander Motin return; 195831f5dcfSAlexander Motin } 196831f5dcfSAlexander Motin timeout--; 197831f5dcfSAlexander Motin DELAY(1000); 198831f5dcfSAlexander Motin } 199831f5dcfSAlexander Motin } 200831f5dcfSAlexander Motin 201831f5dcfSAlexander Motin static void 202831f5dcfSAlexander Motin sdhci_init(struct sdhci_slot *slot) 203831f5dcfSAlexander Motin { 204831f5dcfSAlexander Motin 205831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_ALL); 206831f5dcfSAlexander Motin 207831f5dcfSAlexander Motin /* Enable interrupts. */ 208831f5dcfSAlexander Motin slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 209831f5dcfSAlexander Motin SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 210831f5dcfSAlexander Motin SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 211831f5dcfSAlexander Motin SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | 212831f5dcfSAlexander Motin SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 213831f5dcfSAlexander Motin SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | 214831f5dcfSAlexander Motin SDHCI_INT_ACMD12ERR; 215831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 216831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 217831f5dcfSAlexander Motin } 218831f5dcfSAlexander Motin 219831f5dcfSAlexander Motin static void 220831f5dcfSAlexander Motin sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) 221831f5dcfSAlexander Motin { 222831f5dcfSAlexander Motin uint32_t res; 223831f5dcfSAlexander Motin uint16_t clk; 224831f5dcfSAlexander Motin int timeout; 225831f5dcfSAlexander Motin 226831f5dcfSAlexander Motin if (clock == slot->clock) 227831f5dcfSAlexander Motin return; 228831f5dcfSAlexander Motin slot->clock = clock; 229831f5dcfSAlexander Motin 230831f5dcfSAlexander Motin /* Turn off the clock. */ 231831f5dcfSAlexander Motin WR2(slot, SDHCI_CLOCK_CONTROL, 0); 232831f5dcfSAlexander Motin /* If no clock requested - left it so. */ 233831f5dcfSAlexander Motin if (clock == 0) 234831f5dcfSAlexander Motin return; 235831f5dcfSAlexander Motin /* Looking for highest freq <= clock. */ 236831f5dcfSAlexander Motin res = slot->max_clk; 237831f5dcfSAlexander Motin for (clk = 1; clk < 256; clk <<= 1) { 238831f5dcfSAlexander Motin if (res <= clock) 239831f5dcfSAlexander Motin break; 240831f5dcfSAlexander Motin res >>= 1; 241831f5dcfSAlexander Motin } 242831f5dcfSAlexander Motin /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ 243831f5dcfSAlexander Motin clk >>= 1; 244831f5dcfSAlexander Motin /* Now we have got divider, set it. */ 245831f5dcfSAlexander Motin clk <<= SDHCI_DIVIDER_SHIFT; 246831f5dcfSAlexander Motin WR2(slot, SDHCI_CLOCK_CONTROL, clk); 247831f5dcfSAlexander Motin /* Enable clock. */ 248831f5dcfSAlexander Motin clk |= SDHCI_CLOCK_INT_EN; 249831f5dcfSAlexander Motin WR2(slot, SDHCI_CLOCK_CONTROL, clk); 250831f5dcfSAlexander Motin /* Wait up to 10 ms until it stabilize. */ 251831f5dcfSAlexander Motin timeout = 10; 252831f5dcfSAlexander Motin while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) 253831f5dcfSAlexander Motin & SDHCI_CLOCK_INT_STABLE)) { 254831f5dcfSAlexander Motin if (timeout == 0) { 255831f5dcfSAlexander Motin slot_printf(slot, 256831f5dcfSAlexander Motin "Internal clock never stabilised.\n"); 257831f5dcfSAlexander Motin sdhci_dumpregs(slot); 258831f5dcfSAlexander Motin return; 259831f5dcfSAlexander Motin } 260831f5dcfSAlexander Motin timeout--; 261831f5dcfSAlexander Motin DELAY(1000); 262831f5dcfSAlexander Motin } 263831f5dcfSAlexander Motin /* Pass clock signal to the bus. */ 264831f5dcfSAlexander Motin clk |= SDHCI_CLOCK_CARD_EN; 265831f5dcfSAlexander Motin WR2(slot, SDHCI_CLOCK_CONTROL, clk); 266831f5dcfSAlexander Motin } 267831f5dcfSAlexander Motin 268831f5dcfSAlexander Motin static void 269831f5dcfSAlexander Motin sdhci_set_power(struct sdhci_slot *slot, u_char power) 270831f5dcfSAlexander Motin { 271831f5dcfSAlexander Motin uint8_t pwr; 272831f5dcfSAlexander Motin 273831f5dcfSAlexander Motin if (slot->power == power) 274831f5dcfSAlexander Motin return; 275*d6b3aaf8SOleksandr Tymoshenko 276831f5dcfSAlexander Motin slot->power = power; 277831f5dcfSAlexander Motin 278831f5dcfSAlexander Motin /* Turn off the power. */ 279831f5dcfSAlexander Motin pwr = 0; 280831f5dcfSAlexander Motin WR1(slot, SDHCI_POWER_CONTROL, pwr); 281831f5dcfSAlexander Motin /* If power down requested - left it so. */ 282831f5dcfSAlexander Motin if (power == 0) 283831f5dcfSAlexander Motin return; 284831f5dcfSAlexander Motin /* Set voltage. */ 285831f5dcfSAlexander Motin switch (1 << power) { 286831f5dcfSAlexander Motin case MMC_OCR_LOW_VOLTAGE: 287831f5dcfSAlexander Motin pwr |= SDHCI_POWER_180; 288831f5dcfSAlexander Motin break; 289831f5dcfSAlexander Motin case MMC_OCR_290_300: 290831f5dcfSAlexander Motin case MMC_OCR_300_310: 291831f5dcfSAlexander Motin pwr |= SDHCI_POWER_300; 292831f5dcfSAlexander Motin break; 293831f5dcfSAlexander Motin case MMC_OCR_320_330: 294831f5dcfSAlexander Motin case MMC_OCR_330_340: 295831f5dcfSAlexander Motin pwr |= SDHCI_POWER_330; 296831f5dcfSAlexander Motin break; 297831f5dcfSAlexander Motin } 298831f5dcfSAlexander Motin WR1(slot, SDHCI_POWER_CONTROL, pwr); 299831f5dcfSAlexander Motin /* Turn on the power. */ 300831f5dcfSAlexander Motin pwr |= SDHCI_POWER_ON; 301831f5dcfSAlexander Motin WR1(slot, SDHCI_POWER_CONTROL, pwr); 302831f5dcfSAlexander Motin } 303831f5dcfSAlexander Motin 304831f5dcfSAlexander Motin static void 305831f5dcfSAlexander Motin sdhci_read_block_pio(struct sdhci_slot *slot) 306831f5dcfSAlexander Motin { 307831f5dcfSAlexander Motin uint32_t data; 308831f5dcfSAlexander Motin char *buffer; 309831f5dcfSAlexander Motin size_t left; 310831f5dcfSAlexander Motin 311831f5dcfSAlexander Motin buffer = slot->curcmd->data->data; 312831f5dcfSAlexander Motin buffer += slot->offset; 313831f5dcfSAlexander Motin /* Transfer one block at a time. */ 314831f5dcfSAlexander Motin left = min(512, slot->curcmd->data->len - slot->offset); 315831f5dcfSAlexander Motin slot->offset += left; 316831f5dcfSAlexander Motin 317831f5dcfSAlexander Motin /* If we are too fast, broken controllers return zeroes. */ 318*d6b3aaf8SOleksandr Tymoshenko if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) 319831f5dcfSAlexander Motin DELAY(10); 320831f5dcfSAlexander Motin /* Handle unalligned and alligned buffer cases. */ 321831f5dcfSAlexander Motin if ((intptr_t)buffer & 3) { 322831f5dcfSAlexander Motin while (left > 3) { 323831f5dcfSAlexander Motin data = RD4(slot, SDHCI_BUFFER); 324831f5dcfSAlexander Motin buffer[0] = data; 325831f5dcfSAlexander Motin buffer[1] = (data >> 8); 326831f5dcfSAlexander Motin buffer[2] = (data >> 16); 327831f5dcfSAlexander Motin buffer[3] = (data >> 24); 328831f5dcfSAlexander Motin buffer += 4; 329831f5dcfSAlexander Motin left -= 4; 330831f5dcfSAlexander Motin } 331831f5dcfSAlexander Motin } else { 332*d6b3aaf8SOleksandr Tymoshenko RD_MULTI_4(slot, SDHCI_BUFFER, 333831f5dcfSAlexander Motin (uint32_t *)buffer, left >> 2); 334831f5dcfSAlexander Motin left &= 3; 335831f5dcfSAlexander Motin } 336831f5dcfSAlexander Motin /* Handle uneven size case. */ 337831f5dcfSAlexander Motin if (left > 0) { 338831f5dcfSAlexander Motin data = RD4(slot, SDHCI_BUFFER); 339831f5dcfSAlexander Motin while (left > 0) { 340831f5dcfSAlexander Motin *(buffer++) = data; 341831f5dcfSAlexander Motin data >>= 8; 342831f5dcfSAlexander Motin left--; 343831f5dcfSAlexander Motin } 344831f5dcfSAlexander Motin } 345831f5dcfSAlexander Motin } 346831f5dcfSAlexander Motin 347831f5dcfSAlexander Motin static void 348831f5dcfSAlexander Motin sdhci_write_block_pio(struct sdhci_slot *slot) 349831f5dcfSAlexander Motin { 350831f5dcfSAlexander Motin uint32_t data = 0; 351831f5dcfSAlexander Motin char *buffer; 352831f5dcfSAlexander Motin size_t left; 353831f5dcfSAlexander Motin 354831f5dcfSAlexander Motin buffer = slot->curcmd->data->data; 355831f5dcfSAlexander Motin buffer += slot->offset; 356831f5dcfSAlexander Motin /* Transfer one block at a time. */ 357831f5dcfSAlexander Motin left = min(512, slot->curcmd->data->len - slot->offset); 358831f5dcfSAlexander Motin slot->offset += left; 359831f5dcfSAlexander Motin 360831f5dcfSAlexander Motin /* Handle unalligned and alligned buffer cases. */ 361831f5dcfSAlexander Motin if ((intptr_t)buffer & 3) { 362831f5dcfSAlexander Motin while (left > 3) { 363831f5dcfSAlexander Motin data = buffer[0] + 364831f5dcfSAlexander Motin (buffer[1] << 8) + 365831f5dcfSAlexander Motin (buffer[2] << 16) + 366831f5dcfSAlexander Motin (buffer[3] << 24); 367831f5dcfSAlexander Motin left -= 4; 368831f5dcfSAlexander Motin buffer += 4; 369831f5dcfSAlexander Motin WR4(slot, SDHCI_BUFFER, data); 370831f5dcfSAlexander Motin } 371831f5dcfSAlexander Motin } else { 372*d6b3aaf8SOleksandr Tymoshenko WR_MULTI_4(slot, SDHCI_BUFFER, 373831f5dcfSAlexander Motin (uint32_t *)buffer, left >> 2); 374831f5dcfSAlexander Motin left &= 3; 375831f5dcfSAlexander Motin } 376831f5dcfSAlexander Motin /* Handle uneven size case. */ 377831f5dcfSAlexander Motin if (left > 0) { 378831f5dcfSAlexander Motin while (left > 0) { 379831f5dcfSAlexander Motin data <<= 8; 380831f5dcfSAlexander Motin data += *(buffer++); 381831f5dcfSAlexander Motin left--; 382831f5dcfSAlexander Motin } 383831f5dcfSAlexander Motin WR4(slot, SDHCI_BUFFER, data); 384831f5dcfSAlexander Motin } 385831f5dcfSAlexander Motin } 386831f5dcfSAlexander Motin 387831f5dcfSAlexander Motin static void 388831f5dcfSAlexander Motin sdhci_transfer_pio(struct sdhci_slot *slot) 389831f5dcfSAlexander Motin { 390831f5dcfSAlexander Motin 391831f5dcfSAlexander Motin /* Read as many blocks as possible. */ 392831f5dcfSAlexander Motin if (slot->curcmd->data->flags & MMC_DATA_READ) { 393831f5dcfSAlexander Motin while (RD4(slot, SDHCI_PRESENT_STATE) & 394831f5dcfSAlexander Motin SDHCI_DATA_AVAILABLE) { 395831f5dcfSAlexander Motin sdhci_read_block_pio(slot); 396831f5dcfSAlexander Motin if (slot->offset >= slot->curcmd->data->len) 397831f5dcfSAlexander Motin break; 398831f5dcfSAlexander Motin } 399831f5dcfSAlexander Motin } else { 400831f5dcfSAlexander Motin while (RD4(slot, SDHCI_PRESENT_STATE) & 401831f5dcfSAlexander Motin SDHCI_SPACE_AVAILABLE) { 402831f5dcfSAlexander Motin sdhci_write_block_pio(slot); 403831f5dcfSAlexander Motin if (slot->offset >= slot->curcmd->data->len) 404831f5dcfSAlexander Motin break; 405831f5dcfSAlexander Motin } 406831f5dcfSAlexander Motin } 407831f5dcfSAlexander Motin } 408831f5dcfSAlexander Motin 409831f5dcfSAlexander Motin static void 410831f5dcfSAlexander Motin sdhci_card_delay(void *arg) 411831f5dcfSAlexander Motin { 412831f5dcfSAlexander Motin struct sdhci_slot *slot = arg; 413831f5dcfSAlexander Motin 414831f5dcfSAlexander Motin taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); 415831f5dcfSAlexander Motin } 416831f5dcfSAlexander Motin 417831f5dcfSAlexander Motin static void 418831f5dcfSAlexander Motin sdhci_card_task(void *arg, int pending) 419831f5dcfSAlexander Motin { 420831f5dcfSAlexander Motin struct sdhci_slot *slot = arg; 421831f5dcfSAlexander Motin 422831f5dcfSAlexander Motin SDHCI_LOCK(slot); 423831f5dcfSAlexander Motin if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) { 424831f5dcfSAlexander Motin if (slot->dev == NULL) { 425831f5dcfSAlexander Motin /* If card is present - attach mmc bus. */ 426*d6b3aaf8SOleksandr Tymoshenko slot->dev = device_add_child(slot->bus, "mmc", -1); 427831f5dcfSAlexander Motin device_set_ivars(slot->dev, slot); 428831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 429831f5dcfSAlexander Motin device_probe_and_attach(slot->dev); 430831f5dcfSAlexander Motin } else 431831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 432831f5dcfSAlexander Motin } else { 433831f5dcfSAlexander Motin if (slot->dev != NULL) { 434831f5dcfSAlexander Motin /* If no card present - detach mmc bus. */ 435831f5dcfSAlexander Motin device_t d = slot->dev; 436831f5dcfSAlexander Motin slot->dev = NULL; 437831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 438*d6b3aaf8SOleksandr Tymoshenko device_delete_child(slot->bus, d); 439831f5dcfSAlexander Motin } else 440831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 441831f5dcfSAlexander Motin } 442831f5dcfSAlexander Motin } 443831f5dcfSAlexander Motin 444*d6b3aaf8SOleksandr Tymoshenko int 445*d6b3aaf8SOleksandr Tymoshenko sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) 446831f5dcfSAlexander Motin { 447831f5dcfSAlexander Motin uint32_t caps; 448*d6b3aaf8SOleksandr Tymoshenko int err; 449831f5dcfSAlexander Motin 450831f5dcfSAlexander Motin SDHCI_LOCK_INIT(slot); 451*d6b3aaf8SOleksandr Tymoshenko slot->num = num; 452*d6b3aaf8SOleksandr Tymoshenko slot->bus = dev; 453*d6b3aaf8SOleksandr Tymoshenko 454831f5dcfSAlexander Motin /* Allocate DMA tag. */ 455831f5dcfSAlexander Motin err = bus_dma_tag_create(bus_get_dma_tag(dev), 456831f5dcfSAlexander Motin DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 457831f5dcfSAlexander Motin BUS_SPACE_MAXADDR, NULL, NULL, 458831f5dcfSAlexander Motin DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, 459831f5dcfSAlexander Motin BUS_DMA_ALLOCNOW, NULL, NULL, 460831f5dcfSAlexander Motin &slot->dmatag); 461831f5dcfSAlexander Motin if (err != 0) { 462831f5dcfSAlexander Motin device_printf(dev, "Can't create DMA tag\n"); 463831f5dcfSAlexander Motin SDHCI_LOCK_DESTROY(slot); 464*d6b3aaf8SOleksandr Tymoshenko return (err); 465831f5dcfSAlexander Motin } 466831f5dcfSAlexander Motin /* Allocate DMA memory. */ 467831f5dcfSAlexander Motin err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, 468831f5dcfSAlexander Motin BUS_DMA_NOWAIT, &slot->dmamap); 469831f5dcfSAlexander Motin if (err != 0) { 470831f5dcfSAlexander Motin device_printf(dev, "Can't alloc DMA memory\n"); 471831f5dcfSAlexander Motin SDHCI_LOCK_DESTROY(slot); 472*d6b3aaf8SOleksandr Tymoshenko return (err); 473831f5dcfSAlexander Motin } 474831f5dcfSAlexander Motin /* Map the memory. */ 475831f5dcfSAlexander Motin err = bus_dmamap_load(slot->dmatag, slot->dmamap, 476831f5dcfSAlexander Motin (void *)slot->dmamem, DMA_BLOCK_SIZE, 477831f5dcfSAlexander Motin sdhci_getaddr, &slot->paddr, 0); 478831f5dcfSAlexander Motin if (err != 0 || slot->paddr == 0) { 479831f5dcfSAlexander Motin device_printf(dev, "Can't load DMA memory\n"); 480831f5dcfSAlexander Motin SDHCI_LOCK_DESTROY(slot); 481*d6b3aaf8SOleksandr Tymoshenko if(err) 482*d6b3aaf8SOleksandr Tymoshenko return (err); 483*d6b3aaf8SOleksandr Tymoshenko else 484*d6b3aaf8SOleksandr Tymoshenko return (EFAULT); 485831f5dcfSAlexander Motin } 486*d6b3aaf8SOleksandr Tymoshenko 487831f5dcfSAlexander Motin /* Initialize slot. */ 488831f5dcfSAlexander Motin sdhci_init(slot); 489*d6b3aaf8SOleksandr Tymoshenko slot->version = (RD2(slot, SDHCI_HOST_VERSION) 490*d6b3aaf8SOleksandr Tymoshenko >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; 491831f5dcfSAlexander Motin caps = RD4(slot, SDHCI_CAPABILITIES); 492831f5dcfSAlexander Motin /* Calculate base clock frequency. */ 493831f5dcfSAlexander Motin slot->max_clk = 494831f5dcfSAlexander Motin (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; 495831f5dcfSAlexander Motin if (slot->max_clk == 0) { 496*d6b3aaf8SOleksandr Tymoshenko slot->max_clk = 50; 497831f5dcfSAlexander Motin device_printf(dev, "Hardware doesn't specify base clock " 498831f5dcfSAlexander Motin "frequency.\n"); 499831f5dcfSAlexander Motin } 500831f5dcfSAlexander Motin slot->max_clk *= 1000000; 501831f5dcfSAlexander Motin /* Calculate timeout clock frequency. */ 502831f5dcfSAlexander Motin slot->timeout_clk = 503831f5dcfSAlexander Motin (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 504831f5dcfSAlexander Motin if (slot->timeout_clk == 0) { 505831f5dcfSAlexander Motin device_printf(dev, "Hardware doesn't specify timeout clock " 506831f5dcfSAlexander Motin "frequency.\n"); 507831f5dcfSAlexander Motin } 508831f5dcfSAlexander Motin if (caps & SDHCI_TIMEOUT_CLK_UNIT) 509831f5dcfSAlexander Motin slot->timeout_clk *= 1000; 510831f5dcfSAlexander Motin 511831f5dcfSAlexander Motin slot->host.f_min = slot->max_clk / 256; 512831f5dcfSAlexander Motin slot->host.f_max = slot->max_clk; 513831f5dcfSAlexander Motin slot->host.host_ocr = 0; 514831f5dcfSAlexander Motin if (caps & SDHCI_CAN_VDD_330) 515831f5dcfSAlexander Motin slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; 516831f5dcfSAlexander Motin if (caps & SDHCI_CAN_VDD_300) 517831f5dcfSAlexander Motin slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; 518831f5dcfSAlexander Motin if (caps & SDHCI_CAN_VDD_180) 519831f5dcfSAlexander Motin slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; 520831f5dcfSAlexander Motin if (slot->host.host_ocr == 0) { 521831f5dcfSAlexander Motin device_printf(dev, "Hardware doesn't report any " 522831f5dcfSAlexander Motin "support voltages.\n"); 523831f5dcfSAlexander Motin } 524831f5dcfSAlexander Motin slot->host.caps = MMC_CAP_4_BIT_DATA; 525831f5dcfSAlexander Motin if (caps & SDHCI_CAN_DO_HISPD) 526831f5dcfSAlexander Motin slot->host.caps |= MMC_CAP_HSPEED; 527831f5dcfSAlexander Motin /* Decide if we have usable DMA. */ 528831f5dcfSAlexander Motin if (caps & SDHCI_CAN_DO_DMA) 529831f5dcfSAlexander Motin slot->opt |= SDHCI_HAVE_DMA; 530*d6b3aaf8SOleksandr Tymoshenko 531*d6b3aaf8SOleksandr Tymoshenko if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) 532831f5dcfSAlexander Motin slot->opt &= ~SDHCI_HAVE_DMA; 533*d6b3aaf8SOleksandr Tymoshenko if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) 534831f5dcfSAlexander Motin slot->opt |= SDHCI_HAVE_DMA; 535831f5dcfSAlexander Motin 5365b69a497SAlexander Motin if (bootverbose || sdhci_debug) { 537831f5dcfSAlexander Motin slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n", 538831f5dcfSAlexander Motin slot->max_clk / 1000000, 539831f5dcfSAlexander Motin (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", 540831f5dcfSAlexander Motin (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", 541831f5dcfSAlexander Motin (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", 542831f5dcfSAlexander Motin (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "", 543831f5dcfSAlexander Motin (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO"); 544831f5dcfSAlexander Motin sdhci_dumpregs(slot); 545831f5dcfSAlexander Motin } 546831f5dcfSAlexander Motin 547831f5dcfSAlexander Motin TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); 548831f5dcfSAlexander Motin callout_init(&slot->card_callout, 1); 549831f5dcfSAlexander Motin return (0); 550831f5dcfSAlexander Motin } 551831f5dcfSAlexander Motin 552*d6b3aaf8SOleksandr Tymoshenko void 553*d6b3aaf8SOleksandr Tymoshenko sdhci_start_slot(struct sdhci_slot *slot) 554831f5dcfSAlexander Motin { 555*d6b3aaf8SOleksandr Tymoshenko sdhci_card_task(slot, 0); 556*d6b3aaf8SOleksandr Tymoshenko } 557831f5dcfSAlexander Motin 558*d6b3aaf8SOleksandr Tymoshenko int 559*d6b3aaf8SOleksandr Tymoshenko sdhci_cleanup_slot(struct sdhci_slot *slot) 560*d6b3aaf8SOleksandr Tymoshenko { 561831f5dcfSAlexander Motin device_t d; 562831f5dcfSAlexander Motin 563831f5dcfSAlexander Motin callout_drain(&slot->card_callout); 564831f5dcfSAlexander Motin taskqueue_drain(taskqueue_swi_giant, &slot->card_task); 565831f5dcfSAlexander Motin 566831f5dcfSAlexander Motin SDHCI_LOCK(slot); 567831f5dcfSAlexander Motin d = slot->dev; 568831f5dcfSAlexander Motin slot->dev = NULL; 569831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 570831f5dcfSAlexander Motin if (d != NULL) 571*d6b3aaf8SOleksandr Tymoshenko device_delete_child(slot->bus, d); 572831f5dcfSAlexander Motin 573831f5dcfSAlexander Motin SDHCI_LOCK(slot); 574831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_ALL); 575831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 576831f5dcfSAlexander Motin bus_dmamap_unload(slot->dmatag, slot->dmamap); 577831f5dcfSAlexander Motin bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); 578831f5dcfSAlexander Motin bus_dma_tag_destroy(slot->dmatag); 579*d6b3aaf8SOleksandr Tymoshenko 580831f5dcfSAlexander Motin SDHCI_LOCK_DESTROY(slot); 581*d6b3aaf8SOleksandr Tymoshenko 582831f5dcfSAlexander Motin return (0); 583831f5dcfSAlexander Motin } 584831f5dcfSAlexander Motin 585*d6b3aaf8SOleksandr Tymoshenko int 586*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_suspend(struct sdhci_slot *slot) 58792bf0e27SAlexander Motin { 588*d6b3aaf8SOleksandr Tymoshenko sdhci_reset(slot, SDHCI_RESET_ALL); 58992bf0e27SAlexander Motin 59092bf0e27SAlexander Motin return (0); 59192bf0e27SAlexander Motin } 59292bf0e27SAlexander Motin 593*d6b3aaf8SOleksandr Tymoshenko int 594*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_resume(struct sdhci_slot *slot) 59592bf0e27SAlexander Motin { 596*d6b3aaf8SOleksandr Tymoshenko sdhci_init(slot); 59792bf0e27SAlexander Motin 598*d6b3aaf8SOleksandr Tymoshenko return (0); 59992bf0e27SAlexander Motin } 60092bf0e27SAlexander Motin 601*d6b3aaf8SOleksandr Tymoshenko int 602*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_update_ios(device_t brdev, device_t reqdev) 603831f5dcfSAlexander Motin { 604831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(reqdev); 605831f5dcfSAlexander Motin struct mmc_ios *ios = &slot->host.ios; 606831f5dcfSAlexander Motin 607831f5dcfSAlexander Motin SDHCI_LOCK(slot); 608831f5dcfSAlexander Motin /* Do full reset on bus power down to clear from any state. */ 609831f5dcfSAlexander Motin if (ios->power_mode == power_off) { 610831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 611831f5dcfSAlexander Motin sdhci_init(slot); 612831f5dcfSAlexander Motin } 613831f5dcfSAlexander Motin /* Configure the bus. */ 614831f5dcfSAlexander Motin sdhci_set_clock(slot, ios->clock); 615831f5dcfSAlexander Motin sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd); 616831f5dcfSAlexander Motin if (ios->bus_width == bus_width_4) 617831f5dcfSAlexander Motin slot->hostctrl |= SDHCI_CTRL_4BITBUS; 618831f5dcfSAlexander Motin else 619831f5dcfSAlexander Motin slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; 620831f5dcfSAlexander Motin if (ios->timing == bus_timing_hs) 621831f5dcfSAlexander Motin slot->hostctrl |= SDHCI_CTRL_HISPD; 622831f5dcfSAlexander Motin else 623831f5dcfSAlexander Motin slot->hostctrl &= ~SDHCI_CTRL_HISPD; 624831f5dcfSAlexander Motin WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); 625831f5dcfSAlexander Motin /* Some controllers like reset after bus changes. */ 626*d6b3aaf8SOleksandr Tymoshenko if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) 627831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 628831f5dcfSAlexander Motin 629831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 630831f5dcfSAlexander Motin return (0); 631831f5dcfSAlexander Motin } 632831f5dcfSAlexander Motin 633831f5dcfSAlexander Motin static void 634831f5dcfSAlexander Motin sdhci_set_transfer_mode(struct sdhci_slot *slot, 635831f5dcfSAlexander Motin struct mmc_data *data) 636831f5dcfSAlexander Motin { 637831f5dcfSAlexander Motin uint16_t mode; 638831f5dcfSAlexander Motin 639831f5dcfSAlexander Motin if (data == NULL) 640831f5dcfSAlexander Motin return; 641831f5dcfSAlexander Motin 642831f5dcfSAlexander Motin mode = SDHCI_TRNS_BLK_CNT_EN; 643831f5dcfSAlexander Motin if (data->len > 512) 644831f5dcfSAlexander Motin mode |= SDHCI_TRNS_MULTI; 645831f5dcfSAlexander Motin if (data->flags & MMC_DATA_READ) 646831f5dcfSAlexander Motin mode |= SDHCI_TRNS_READ; 647831f5dcfSAlexander Motin if (slot->req->stop) 648831f5dcfSAlexander Motin mode |= SDHCI_TRNS_ACMD12; 649831f5dcfSAlexander Motin if (slot->flags & SDHCI_USE_DMA) 650831f5dcfSAlexander Motin mode |= SDHCI_TRNS_DMA; 651831f5dcfSAlexander Motin 652831f5dcfSAlexander Motin WR2(slot, SDHCI_TRANSFER_MODE, mode); 653831f5dcfSAlexander Motin } 654831f5dcfSAlexander Motin 655831f5dcfSAlexander Motin static void 656831f5dcfSAlexander Motin sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) 657831f5dcfSAlexander Motin { 658831f5dcfSAlexander Motin struct mmc_request *req = slot->req; 659831f5dcfSAlexander Motin int flags, timeout; 660831f5dcfSAlexander Motin uint32_t mask, state; 661831f5dcfSAlexander Motin 662831f5dcfSAlexander Motin slot->curcmd = cmd; 663831f5dcfSAlexander Motin slot->cmd_done = 0; 664831f5dcfSAlexander Motin 665831f5dcfSAlexander Motin cmd->error = MMC_ERR_NONE; 666831f5dcfSAlexander Motin 667831f5dcfSAlexander Motin /* This flags combination is not supported by controller. */ 668831f5dcfSAlexander Motin if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 669831f5dcfSAlexander Motin slot_printf(slot, "Unsupported response type!\n"); 670831f5dcfSAlexander Motin cmd->error = MMC_ERR_FAILED; 671831f5dcfSAlexander Motin slot->req = NULL; 672831f5dcfSAlexander Motin slot->curcmd = NULL; 673831f5dcfSAlexander Motin req->done(req); 674831f5dcfSAlexander Motin return; 675831f5dcfSAlexander Motin } 676831f5dcfSAlexander Motin 677831f5dcfSAlexander Motin /* Read controller present state. */ 678831f5dcfSAlexander Motin state = RD4(slot, SDHCI_PRESENT_STATE); 679d8208d9eSAlexander Motin /* Do not issue command if there is no card, clock or power. 680d8208d9eSAlexander Motin * Controller will not detect timeout without clock active. */ 681d8208d9eSAlexander Motin if ((state & SDHCI_CARD_PRESENT) == 0 || 682d8208d9eSAlexander Motin slot->power == 0 || 683d8208d9eSAlexander Motin slot->clock == 0) { 684831f5dcfSAlexander Motin cmd->error = MMC_ERR_FAILED; 685831f5dcfSAlexander Motin slot->req = NULL; 686831f5dcfSAlexander Motin slot->curcmd = NULL; 687831f5dcfSAlexander Motin req->done(req); 688831f5dcfSAlexander Motin return; 689831f5dcfSAlexander Motin } 690831f5dcfSAlexander Motin /* Always wait for free CMD bus. */ 691831f5dcfSAlexander Motin mask = SDHCI_CMD_INHIBIT; 692831f5dcfSAlexander Motin /* Wait for free DAT if we have data or busy signal. */ 693831f5dcfSAlexander Motin if (cmd->data || (cmd->flags & MMC_RSP_BUSY)) 694831f5dcfSAlexander Motin mask |= SDHCI_DAT_INHIBIT; 695831f5dcfSAlexander Motin /* We shouldn't wait for DAT for stop commands. */ 696831f5dcfSAlexander Motin if (cmd == slot->req->stop) 697831f5dcfSAlexander Motin mask &= ~SDHCI_DAT_INHIBIT; 698831f5dcfSAlexander Motin /* Wait for bus no more then 10 ms. */ 699831f5dcfSAlexander Motin timeout = 10; 700831f5dcfSAlexander Motin while (state & mask) { 701831f5dcfSAlexander Motin if (timeout == 0) { 702831f5dcfSAlexander Motin slot_printf(slot, "Controller never released " 703831f5dcfSAlexander Motin "inhibit bit(s).\n"); 704831f5dcfSAlexander Motin sdhci_dumpregs(slot); 705831f5dcfSAlexander Motin cmd->error = MMC_ERR_FAILED; 706831f5dcfSAlexander Motin slot->req = NULL; 707831f5dcfSAlexander Motin slot->curcmd = NULL; 708831f5dcfSAlexander Motin req->done(req); 709831f5dcfSAlexander Motin return; 710831f5dcfSAlexander Motin } 711831f5dcfSAlexander Motin timeout--; 712831f5dcfSAlexander Motin DELAY(1000); 713831f5dcfSAlexander Motin state = RD4(slot, SDHCI_PRESENT_STATE); 714831f5dcfSAlexander Motin } 715831f5dcfSAlexander Motin 716831f5dcfSAlexander Motin /* Prepare command flags. */ 717831f5dcfSAlexander Motin if (!(cmd->flags & MMC_RSP_PRESENT)) 718831f5dcfSAlexander Motin flags = SDHCI_CMD_RESP_NONE; 719831f5dcfSAlexander Motin else if (cmd->flags & MMC_RSP_136) 720831f5dcfSAlexander Motin flags = SDHCI_CMD_RESP_LONG; 721831f5dcfSAlexander Motin else if (cmd->flags & MMC_RSP_BUSY) 722831f5dcfSAlexander Motin flags = SDHCI_CMD_RESP_SHORT_BUSY; 723831f5dcfSAlexander Motin else 724831f5dcfSAlexander Motin flags = SDHCI_CMD_RESP_SHORT; 725831f5dcfSAlexander Motin if (cmd->flags & MMC_RSP_CRC) 726831f5dcfSAlexander Motin flags |= SDHCI_CMD_CRC; 727831f5dcfSAlexander Motin if (cmd->flags & MMC_RSP_OPCODE) 728831f5dcfSAlexander Motin flags |= SDHCI_CMD_INDEX; 729831f5dcfSAlexander Motin if (cmd->data) 730831f5dcfSAlexander Motin flags |= SDHCI_CMD_DATA; 731831f5dcfSAlexander Motin if (cmd->opcode == MMC_STOP_TRANSMISSION) 732831f5dcfSAlexander Motin flags |= SDHCI_CMD_TYPE_ABORT; 733831f5dcfSAlexander Motin /* Prepare data. */ 734831f5dcfSAlexander Motin sdhci_start_data(slot, cmd->data); 735831f5dcfSAlexander Motin /* 736831f5dcfSAlexander Motin * Interrupt aggregation: To reduce total number of interrupts 737831f5dcfSAlexander Motin * group response interrupt with data interrupt when possible. 738831f5dcfSAlexander Motin * If there going to be data interrupt, mask response one. 739831f5dcfSAlexander Motin */ 740831f5dcfSAlexander Motin if (slot->data_done == 0) { 741831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, 742831f5dcfSAlexander Motin slot->intmask &= ~SDHCI_INT_RESPONSE); 743831f5dcfSAlexander Motin } 744831f5dcfSAlexander Motin /* Set command argument. */ 745831f5dcfSAlexander Motin WR4(slot, SDHCI_ARGUMENT, cmd->arg); 746831f5dcfSAlexander Motin /* Set data transfer mode. */ 747831f5dcfSAlexander Motin sdhci_set_transfer_mode(slot, cmd->data); 748831f5dcfSAlexander Motin /* Start command. */ 749*d6b3aaf8SOleksandr Tymoshenko WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); 750831f5dcfSAlexander Motin } 751831f5dcfSAlexander Motin 752831f5dcfSAlexander Motin static void 753831f5dcfSAlexander Motin sdhci_finish_command(struct sdhci_slot *slot) 754831f5dcfSAlexander Motin { 755831f5dcfSAlexander Motin int i; 756831f5dcfSAlexander Motin 757831f5dcfSAlexander Motin slot->cmd_done = 1; 758831f5dcfSAlexander Motin /* Interrupt aggregation: Restore command interrupt. 759831f5dcfSAlexander Motin * Main restore point for the case when command interrupt 760831f5dcfSAlexander Motin * happened first. */ 761831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); 762831f5dcfSAlexander Motin /* In case of error - reset host and return. */ 763831f5dcfSAlexander Motin if (slot->curcmd->error) { 764831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_CMD); 765831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_DATA); 766831f5dcfSAlexander Motin sdhci_start(slot); 767831f5dcfSAlexander Motin return; 768831f5dcfSAlexander Motin } 769831f5dcfSAlexander Motin /* If command has response - fetch it. */ 770831f5dcfSAlexander Motin if (slot->curcmd->flags & MMC_RSP_PRESENT) { 771831f5dcfSAlexander Motin if (slot->curcmd->flags & MMC_RSP_136) { 772831f5dcfSAlexander Motin /* CRC is stripped so we need one byte shift. */ 773831f5dcfSAlexander Motin uint8_t extra = 0; 774831f5dcfSAlexander Motin for (i = 0; i < 4; i++) { 775831f5dcfSAlexander Motin uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4); 776831f5dcfSAlexander Motin slot->curcmd->resp[3 - i] = (val << 8) + extra; 777831f5dcfSAlexander Motin extra = val >> 24; 778831f5dcfSAlexander Motin } 779831f5dcfSAlexander Motin } else 780831f5dcfSAlexander Motin slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); 781831f5dcfSAlexander Motin } 782831f5dcfSAlexander Motin /* If data ready - finish. */ 783831f5dcfSAlexander Motin if (slot->data_done) 784831f5dcfSAlexander Motin sdhci_start(slot); 785831f5dcfSAlexander Motin } 786831f5dcfSAlexander Motin 787831f5dcfSAlexander Motin static void 788831f5dcfSAlexander Motin sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) 789831f5dcfSAlexander Motin { 790831f5dcfSAlexander Motin uint32_t target_timeout, current_timeout; 791831f5dcfSAlexander Motin uint8_t div; 792831f5dcfSAlexander Motin 793831f5dcfSAlexander Motin if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 794831f5dcfSAlexander Motin slot->data_done = 1; 795831f5dcfSAlexander Motin return; 796831f5dcfSAlexander Motin } 797831f5dcfSAlexander Motin 798831f5dcfSAlexander Motin slot->data_done = 0; 799831f5dcfSAlexander Motin 800831f5dcfSAlexander Motin /* Calculate and set data timeout.*/ 801831f5dcfSAlexander Motin /* XXX: We should have this from mmc layer, now assume 1 sec. */ 802831f5dcfSAlexander Motin target_timeout = 1000000; 803831f5dcfSAlexander Motin div = 0; 804831f5dcfSAlexander Motin current_timeout = (1 << 13) * 1000 / slot->timeout_clk; 805831f5dcfSAlexander Motin while (current_timeout < target_timeout) { 806831f5dcfSAlexander Motin div++; 807831f5dcfSAlexander Motin current_timeout <<= 1; 808831f5dcfSAlexander Motin if (div >= 0xF) 809831f5dcfSAlexander Motin break; 810831f5dcfSAlexander Motin } 811831f5dcfSAlexander Motin /* Compensate for an off-by-one error in the CaFe chip.*/ 812*d6b3aaf8SOleksandr Tymoshenko if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL) 813831f5dcfSAlexander Motin div++; 814831f5dcfSAlexander Motin if (div >= 0xF) { 815831f5dcfSAlexander Motin slot_printf(slot, "Timeout too large!\n"); 816831f5dcfSAlexander Motin div = 0xE; 817831f5dcfSAlexander Motin } 818831f5dcfSAlexander Motin WR1(slot, SDHCI_TIMEOUT_CONTROL, div); 819831f5dcfSAlexander Motin 820831f5dcfSAlexander Motin if (data == NULL) 821831f5dcfSAlexander Motin return; 822831f5dcfSAlexander Motin 823831f5dcfSAlexander Motin /* Use DMA if possible. */ 824831f5dcfSAlexander Motin if ((slot->opt & SDHCI_HAVE_DMA)) 825831f5dcfSAlexander Motin slot->flags |= SDHCI_USE_DMA; 826831f5dcfSAlexander Motin /* If data is small, broken DMA may return zeroes instead of data, */ 827*d6b3aaf8SOleksandr Tymoshenko if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && 828831f5dcfSAlexander Motin (data->len <= 512)) 829831f5dcfSAlexander Motin slot->flags &= ~SDHCI_USE_DMA; 830831f5dcfSAlexander Motin /* Some controllers require even block sizes. */ 831*d6b3aaf8SOleksandr Tymoshenko if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && 832831f5dcfSAlexander Motin ((data->len) & 0x3)) 833831f5dcfSAlexander Motin slot->flags &= ~SDHCI_USE_DMA; 834831f5dcfSAlexander Motin /* Load DMA buffer. */ 835831f5dcfSAlexander Motin if (slot->flags & SDHCI_USE_DMA) { 836831f5dcfSAlexander Motin if (data->flags & MMC_DATA_READ) 837831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); 838831f5dcfSAlexander Motin else { 839831f5dcfSAlexander Motin memcpy(slot->dmamem, data->data, 840831f5dcfSAlexander Motin (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE); 841831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); 842831f5dcfSAlexander Motin } 843831f5dcfSAlexander Motin WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 844831f5dcfSAlexander Motin /* Interrupt aggregation: Mask border interrupt 845831f5dcfSAlexander Motin * for the last page and unmask else. */ 846831f5dcfSAlexander Motin if (data->len == DMA_BLOCK_SIZE) 847831f5dcfSAlexander Motin slot->intmask &= ~SDHCI_INT_DMA_END; 848831f5dcfSAlexander Motin else 849831f5dcfSAlexander Motin slot->intmask |= SDHCI_INT_DMA_END; 850831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 851831f5dcfSAlexander Motin } 852831f5dcfSAlexander Motin /* Current data offset for both PIO and DMA. */ 853831f5dcfSAlexander Motin slot->offset = 0; 854831f5dcfSAlexander Motin /* Set block size and request IRQ on 4K border. */ 855831f5dcfSAlexander Motin WR2(slot, SDHCI_BLOCK_SIZE, 856831f5dcfSAlexander Motin SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512)); 857831f5dcfSAlexander Motin /* Set block count. */ 858831f5dcfSAlexander Motin WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); 859831f5dcfSAlexander Motin } 860831f5dcfSAlexander Motin 861831f5dcfSAlexander Motin static void 862831f5dcfSAlexander Motin sdhci_finish_data(struct sdhci_slot *slot) 863831f5dcfSAlexander Motin { 864831f5dcfSAlexander Motin struct mmc_data *data = slot->curcmd->data; 865831f5dcfSAlexander Motin 866831f5dcfSAlexander Motin slot->data_done = 1; 867831f5dcfSAlexander Motin /* Interrupt aggregation: Restore command interrupt. 868831f5dcfSAlexander Motin * Auxillary restore point for the case when data interrupt 869831f5dcfSAlexander Motin * happened first. */ 870831f5dcfSAlexander Motin if (!slot->cmd_done) { 871831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, 872831f5dcfSAlexander Motin slot->intmask |= SDHCI_INT_RESPONSE); 873831f5dcfSAlexander Motin } 874831f5dcfSAlexander Motin /* Unload rest of data from DMA buffer. */ 875831f5dcfSAlexander Motin if (slot->flags & SDHCI_USE_DMA) { 876831f5dcfSAlexander Motin if (data->flags & MMC_DATA_READ) { 877831f5dcfSAlexander Motin size_t left = data->len - slot->offset; 878831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); 879831f5dcfSAlexander Motin memcpy((u_char*)data->data + slot->offset, slot->dmamem, 880831f5dcfSAlexander Motin (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 881831f5dcfSAlexander Motin } else 882831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 883831f5dcfSAlexander Motin } 884831f5dcfSAlexander Motin /* If there was error - reset the host. */ 885831f5dcfSAlexander Motin if (slot->curcmd->error) { 886831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_CMD); 887831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_DATA); 888831f5dcfSAlexander Motin sdhci_start(slot); 889831f5dcfSAlexander Motin return; 890831f5dcfSAlexander Motin } 891831f5dcfSAlexander Motin /* If we already have command response - finish. */ 892831f5dcfSAlexander Motin if (slot->cmd_done) 893831f5dcfSAlexander Motin sdhci_start(slot); 894831f5dcfSAlexander Motin } 895831f5dcfSAlexander Motin 896831f5dcfSAlexander Motin static void 897831f5dcfSAlexander Motin sdhci_start(struct sdhci_slot *slot) 898831f5dcfSAlexander Motin { 899831f5dcfSAlexander Motin struct mmc_request *req; 900831f5dcfSAlexander Motin 901831f5dcfSAlexander Motin req = slot->req; 902831f5dcfSAlexander Motin if (req == NULL) 903831f5dcfSAlexander Motin return; 904831f5dcfSAlexander Motin 905831f5dcfSAlexander Motin if (!(slot->flags & CMD_STARTED)) { 906831f5dcfSAlexander Motin slot->flags |= CMD_STARTED; 907831f5dcfSAlexander Motin sdhci_start_command(slot, req->cmd); 908831f5dcfSAlexander Motin return; 909831f5dcfSAlexander Motin } 910831f5dcfSAlexander Motin /* We don't need this until using Auto-CMD12 feature 911831f5dcfSAlexander Motin if (!(slot->flags & STOP_STARTED) && req->stop) { 912831f5dcfSAlexander Motin slot->flags |= STOP_STARTED; 913831f5dcfSAlexander Motin sdhci_start_command(slot, req->stop); 914831f5dcfSAlexander Motin return; 915831f5dcfSAlexander Motin } 916831f5dcfSAlexander Motin */ 9175b69a497SAlexander Motin if (sdhci_debug > 1) 9185b69a497SAlexander Motin slot_printf(slot, "result: %d\n", req->cmd->error); 9195b69a497SAlexander Motin if (!req->cmd->error && 920*d6b3aaf8SOleksandr Tymoshenko (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { 921831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_CMD); 922831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_DATA); 923831f5dcfSAlexander Motin } 924831f5dcfSAlexander Motin 925831f5dcfSAlexander Motin /* We must be done -- bad idea to do this while locked? */ 926831f5dcfSAlexander Motin slot->req = NULL; 927831f5dcfSAlexander Motin slot->curcmd = NULL; 928831f5dcfSAlexander Motin req->done(req); 929831f5dcfSAlexander Motin } 930831f5dcfSAlexander Motin 931*d6b3aaf8SOleksandr Tymoshenko int 932*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req) 933831f5dcfSAlexander Motin { 934831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(reqdev); 935831f5dcfSAlexander Motin 936831f5dcfSAlexander Motin SDHCI_LOCK(slot); 937831f5dcfSAlexander Motin if (slot->req != NULL) { 938831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 939831f5dcfSAlexander Motin return (EBUSY); 940831f5dcfSAlexander Motin } 9415b69a497SAlexander Motin if (sdhci_debug > 1) { 9425b69a497SAlexander Motin slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 943831f5dcfSAlexander Motin req->cmd->opcode, req->cmd->arg, req->cmd->flags, 9445b69a497SAlexander Motin (req->cmd->data)?(u_int)req->cmd->data->len:0, 9455b69a497SAlexander Motin (req->cmd->data)?req->cmd->data->flags:0); 9465b69a497SAlexander Motin } 947831f5dcfSAlexander Motin slot->req = req; 948831f5dcfSAlexander Motin slot->flags = 0; 949831f5dcfSAlexander Motin sdhci_start(slot); 950831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 951bea2dca2SAlexander Motin if (dumping) { 952bea2dca2SAlexander Motin while (slot->req != NULL) { 953*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_intr(slot); 954bea2dca2SAlexander Motin DELAY(10); 955bea2dca2SAlexander Motin } 956bea2dca2SAlexander Motin } 957831f5dcfSAlexander Motin return (0); 958831f5dcfSAlexander Motin } 959831f5dcfSAlexander Motin 960*d6b3aaf8SOleksandr Tymoshenko int 961*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_get_ro(device_t brdev, device_t reqdev) 962831f5dcfSAlexander Motin { 963831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(reqdev); 964831f5dcfSAlexander Motin uint32_t val; 965831f5dcfSAlexander Motin 966831f5dcfSAlexander Motin SDHCI_LOCK(slot); 967831f5dcfSAlexander Motin val = RD4(slot, SDHCI_PRESENT_STATE); 968831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 969831f5dcfSAlexander Motin return (!(val & SDHCI_WRITE_PROTECT)); 970831f5dcfSAlexander Motin } 971831f5dcfSAlexander Motin 972*d6b3aaf8SOleksandr Tymoshenko int 973*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_acquire_host(device_t brdev, device_t reqdev) 974831f5dcfSAlexander Motin { 975831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(reqdev); 976831f5dcfSAlexander Motin int err = 0; 977831f5dcfSAlexander Motin 978831f5dcfSAlexander Motin SDHCI_LOCK(slot); 979831f5dcfSAlexander Motin while (slot->bus_busy) 980d493985aSAlexander Motin msleep(slot, &slot->mtx, 0, "sdhciah", 0); 981831f5dcfSAlexander Motin slot->bus_busy++; 982831f5dcfSAlexander Motin /* Activate led. */ 983831f5dcfSAlexander Motin WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); 984831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 985831f5dcfSAlexander Motin return (err); 986831f5dcfSAlexander Motin } 987831f5dcfSAlexander Motin 988*d6b3aaf8SOleksandr Tymoshenko int 989*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_release_host(device_t brdev, device_t reqdev) 990831f5dcfSAlexander Motin { 991831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(reqdev); 992831f5dcfSAlexander Motin 993831f5dcfSAlexander Motin SDHCI_LOCK(slot); 994831f5dcfSAlexander Motin /* Deactivate led. */ 995831f5dcfSAlexander Motin WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); 996831f5dcfSAlexander Motin slot->bus_busy--; 997831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 998d493985aSAlexander Motin wakeup(slot); 999831f5dcfSAlexander Motin return (0); 1000831f5dcfSAlexander Motin } 1001831f5dcfSAlexander Motin 1002831f5dcfSAlexander Motin static void 1003831f5dcfSAlexander Motin sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) 1004831f5dcfSAlexander Motin { 1005831f5dcfSAlexander Motin 1006831f5dcfSAlexander Motin if (!slot->curcmd) { 1007831f5dcfSAlexander Motin slot_printf(slot, "Got command interrupt 0x%08x, but " 1008831f5dcfSAlexander Motin "there is no active command.\n", intmask); 1009831f5dcfSAlexander Motin sdhci_dumpregs(slot); 1010831f5dcfSAlexander Motin return; 1011831f5dcfSAlexander Motin } 1012831f5dcfSAlexander Motin if (intmask & SDHCI_INT_TIMEOUT) 1013831f5dcfSAlexander Motin slot->curcmd->error = MMC_ERR_TIMEOUT; 1014831f5dcfSAlexander Motin else if (intmask & SDHCI_INT_CRC) 1015831f5dcfSAlexander Motin slot->curcmd->error = MMC_ERR_BADCRC; 1016831f5dcfSAlexander Motin else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) 1017831f5dcfSAlexander Motin slot->curcmd->error = MMC_ERR_FIFO; 1018831f5dcfSAlexander Motin 1019831f5dcfSAlexander Motin sdhci_finish_command(slot); 1020831f5dcfSAlexander Motin } 1021831f5dcfSAlexander Motin 1022831f5dcfSAlexander Motin static void 1023831f5dcfSAlexander Motin sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) 1024831f5dcfSAlexander Motin { 1025831f5dcfSAlexander Motin 1026831f5dcfSAlexander Motin if (!slot->curcmd) { 1027831f5dcfSAlexander Motin slot_printf(slot, "Got data interrupt 0x%08x, but " 1028831f5dcfSAlexander Motin "there is no active command.\n", intmask); 1029831f5dcfSAlexander Motin sdhci_dumpregs(slot); 1030831f5dcfSAlexander Motin return; 1031831f5dcfSAlexander Motin } 1032831f5dcfSAlexander Motin if (slot->curcmd->data == NULL && 1033831f5dcfSAlexander Motin (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { 1034831f5dcfSAlexander Motin slot_printf(slot, "Got data interrupt 0x%08x, but " 1035831f5dcfSAlexander Motin "there is no active data operation.\n", 1036831f5dcfSAlexander Motin intmask); 1037831f5dcfSAlexander Motin sdhci_dumpregs(slot); 1038831f5dcfSAlexander Motin return; 1039831f5dcfSAlexander Motin } 1040831f5dcfSAlexander Motin if (intmask & SDHCI_INT_DATA_TIMEOUT) 1041831f5dcfSAlexander Motin slot->curcmd->error = MMC_ERR_TIMEOUT; 1042831f5dcfSAlexander Motin else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) 1043831f5dcfSAlexander Motin slot->curcmd->error = MMC_ERR_BADCRC; 1044831f5dcfSAlexander Motin if (slot->curcmd->data == NULL && 1045831f5dcfSAlexander Motin (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | 1046831f5dcfSAlexander Motin SDHCI_INT_DMA_END))) { 1047831f5dcfSAlexander Motin slot_printf(slot, "Got data interrupt 0x%08x, but " 1048831f5dcfSAlexander Motin "there is busy-only command.\n", intmask); 1049831f5dcfSAlexander Motin sdhci_dumpregs(slot); 1050831f5dcfSAlexander Motin slot->curcmd->error = MMC_ERR_INVALID; 1051831f5dcfSAlexander Motin } 1052831f5dcfSAlexander Motin if (slot->curcmd->error) { 1053831f5dcfSAlexander Motin /* No need to continue after any error. */ 1054831f5dcfSAlexander Motin sdhci_finish_data(slot); 1055831f5dcfSAlexander Motin return; 1056831f5dcfSAlexander Motin } 1057831f5dcfSAlexander Motin 1058831f5dcfSAlexander Motin /* Handle PIO interrupt. */ 1059831f5dcfSAlexander Motin if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 1060831f5dcfSAlexander Motin sdhci_transfer_pio(slot); 1061831f5dcfSAlexander Motin /* Handle DMA border. */ 1062831f5dcfSAlexander Motin if (intmask & SDHCI_INT_DMA_END) { 1063831f5dcfSAlexander Motin struct mmc_data *data = slot->curcmd->data; 1064831f5dcfSAlexander Motin size_t left; 1065831f5dcfSAlexander Motin 1066831f5dcfSAlexander Motin /* Unload DMA buffer... */ 1067831f5dcfSAlexander Motin left = data->len - slot->offset; 1068831f5dcfSAlexander Motin if (data->flags & MMC_DATA_READ) { 1069831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, 1070831f5dcfSAlexander Motin BUS_DMASYNC_POSTREAD); 1071831f5dcfSAlexander Motin memcpy((u_char*)data->data + slot->offset, slot->dmamem, 1072831f5dcfSAlexander Motin (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1073831f5dcfSAlexander Motin } else { 1074831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, 1075831f5dcfSAlexander Motin BUS_DMASYNC_POSTWRITE); 1076831f5dcfSAlexander Motin } 1077831f5dcfSAlexander Motin /* ... and reload it again. */ 1078831f5dcfSAlexander Motin slot->offset += DMA_BLOCK_SIZE; 1079831f5dcfSAlexander Motin left = data->len - slot->offset; 1080831f5dcfSAlexander Motin if (data->flags & MMC_DATA_READ) { 1081831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, 1082831f5dcfSAlexander Motin BUS_DMASYNC_PREREAD); 1083831f5dcfSAlexander Motin } else { 1084831f5dcfSAlexander Motin memcpy(slot->dmamem, (u_char*)data->data + slot->offset, 1085831f5dcfSAlexander Motin (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE); 1086831f5dcfSAlexander Motin bus_dmamap_sync(slot->dmatag, slot->dmamap, 1087831f5dcfSAlexander Motin BUS_DMASYNC_PREWRITE); 1088831f5dcfSAlexander Motin } 1089831f5dcfSAlexander Motin /* Interrupt aggregation: Mask border interrupt 1090831f5dcfSAlexander Motin * for the last page. */ 1091831f5dcfSAlexander Motin if (left == DMA_BLOCK_SIZE) { 1092831f5dcfSAlexander Motin slot->intmask &= ~SDHCI_INT_DMA_END; 1093831f5dcfSAlexander Motin WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1094831f5dcfSAlexander Motin } 1095831f5dcfSAlexander Motin /* Restart DMA. */ 1096831f5dcfSAlexander Motin WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); 1097831f5dcfSAlexander Motin } 1098831f5dcfSAlexander Motin /* We have got all data. */ 1099831f5dcfSAlexander Motin if (intmask & SDHCI_INT_DATA_END) 1100831f5dcfSAlexander Motin sdhci_finish_data(slot); 1101831f5dcfSAlexander Motin } 1102831f5dcfSAlexander Motin 1103831f5dcfSAlexander Motin static void 1104831f5dcfSAlexander Motin sdhci_acmd_irq(struct sdhci_slot *slot) 1105831f5dcfSAlexander Motin { 1106831f5dcfSAlexander Motin uint16_t err; 1107831f5dcfSAlexander Motin 1108831f5dcfSAlexander Motin err = RD4(slot, SDHCI_ACMD12_ERR); 1109831f5dcfSAlexander Motin if (!slot->curcmd) { 1110831f5dcfSAlexander Motin slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " 1111831f5dcfSAlexander Motin "there is no active command.\n", err); 1112831f5dcfSAlexander Motin sdhci_dumpregs(slot); 1113831f5dcfSAlexander Motin return; 1114831f5dcfSAlexander Motin } 1115831f5dcfSAlexander Motin slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); 1116831f5dcfSAlexander Motin sdhci_reset(slot, SDHCI_RESET_CMD); 1117831f5dcfSAlexander Motin } 1118831f5dcfSAlexander Motin 1119*d6b3aaf8SOleksandr Tymoshenko void 1120*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_intr(struct sdhci_slot *slot) 1121831f5dcfSAlexander Motin { 1122831f5dcfSAlexander Motin uint32_t intmask; 1123831f5dcfSAlexander Motin 1124831f5dcfSAlexander Motin SDHCI_LOCK(slot); 1125831f5dcfSAlexander Motin /* Read slot interrupt status. */ 1126831f5dcfSAlexander Motin intmask = RD4(slot, SDHCI_INT_STATUS); 1127831f5dcfSAlexander Motin if (intmask == 0 || intmask == 0xffffffff) { 1128831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 1129*d6b3aaf8SOleksandr Tymoshenko return; 1130831f5dcfSAlexander Motin } 11315b69a497SAlexander Motin if (sdhci_debug > 2) 11325b69a497SAlexander Motin slot_printf(slot, "Interrupt %#x\n", intmask); 11335b69a497SAlexander Motin 1134831f5dcfSAlexander Motin /* Handle card presence interrupts. */ 1135831f5dcfSAlexander Motin if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 1136831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_STATUS, intmask & 1137831f5dcfSAlexander Motin (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); 1138831f5dcfSAlexander Motin 1139831f5dcfSAlexander Motin if (intmask & SDHCI_INT_CARD_REMOVE) { 11405b69a497SAlexander Motin if (bootverbose || sdhci_debug) 1141831f5dcfSAlexander Motin slot_printf(slot, "Card removed\n"); 1142831f5dcfSAlexander Motin callout_stop(&slot->card_callout); 1143831f5dcfSAlexander Motin taskqueue_enqueue(taskqueue_swi_giant, 1144831f5dcfSAlexander Motin &slot->card_task); 1145831f5dcfSAlexander Motin } 1146831f5dcfSAlexander Motin if (intmask & SDHCI_INT_CARD_INSERT) { 11475b69a497SAlexander Motin if (bootverbose || sdhci_debug) 1148831f5dcfSAlexander Motin slot_printf(slot, "Card inserted\n"); 1149831f5dcfSAlexander Motin callout_reset(&slot->card_callout, hz / 2, 1150831f5dcfSAlexander Motin sdhci_card_delay, slot); 1151831f5dcfSAlexander Motin } 1152831f5dcfSAlexander Motin intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 1153831f5dcfSAlexander Motin } 1154831f5dcfSAlexander Motin /* Handle command interrupts. */ 1155831f5dcfSAlexander Motin if (intmask & SDHCI_INT_CMD_MASK) { 1156831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); 1157831f5dcfSAlexander Motin sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); 1158831f5dcfSAlexander Motin } 1159831f5dcfSAlexander Motin /* Handle data interrupts. */ 1160831f5dcfSAlexander Motin if (intmask & SDHCI_INT_DATA_MASK) { 1161831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); 1162831f5dcfSAlexander Motin sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); 1163831f5dcfSAlexander Motin } 1164831f5dcfSAlexander Motin /* Handle AutoCMD12 error interrupt. */ 1165831f5dcfSAlexander Motin if (intmask & SDHCI_INT_ACMD12ERR) { 1166831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); 1167831f5dcfSAlexander Motin sdhci_acmd_irq(slot); 1168831f5dcfSAlexander Motin } 1169831f5dcfSAlexander Motin intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 1170831f5dcfSAlexander Motin intmask &= ~SDHCI_INT_ACMD12ERR; 1171831f5dcfSAlexander Motin intmask &= ~SDHCI_INT_ERROR; 1172831f5dcfSAlexander Motin /* Handle bus power interrupt. */ 1173831f5dcfSAlexander Motin if (intmask & SDHCI_INT_BUS_POWER) { 1174831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); 1175831f5dcfSAlexander Motin slot_printf(slot, 1176831f5dcfSAlexander Motin "Card is consuming too much power!\n"); 1177831f5dcfSAlexander Motin intmask &= ~SDHCI_INT_BUS_POWER; 1178831f5dcfSAlexander Motin } 1179831f5dcfSAlexander Motin /* The rest is unknown. */ 1180831f5dcfSAlexander Motin if (intmask) { 1181831f5dcfSAlexander Motin WR4(slot, SDHCI_INT_STATUS, intmask); 1182831f5dcfSAlexander Motin slot_printf(slot, "Unexpected interrupt 0x%08x.\n", 1183831f5dcfSAlexander Motin intmask); 1184831f5dcfSAlexander Motin sdhci_dumpregs(slot); 1185831f5dcfSAlexander Motin } 1186831f5dcfSAlexander Motin 1187831f5dcfSAlexander Motin SDHCI_UNLOCK(slot); 1188831f5dcfSAlexander Motin } 1189831f5dcfSAlexander Motin 1190*d6b3aaf8SOleksandr Tymoshenko int 1191*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 1192831f5dcfSAlexander Motin { 1193831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(child); 1194831f5dcfSAlexander Motin 1195831f5dcfSAlexander Motin switch (which) { 1196831f5dcfSAlexander Motin default: 1197831f5dcfSAlexander Motin return (EINVAL); 1198831f5dcfSAlexander Motin case MMCBR_IVAR_BUS_MODE: 1199bcd91d25SJayachandran C. *result = slot->host.ios.bus_mode; 1200831f5dcfSAlexander Motin break; 1201831f5dcfSAlexander Motin case MMCBR_IVAR_BUS_WIDTH: 1202bcd91d25SJayachandran C. *result = slot->host.ios.bus_width; 1203831f5dcfSAlexander Motin break; 1204831f5dcfSAlexander Motin case MMCBR_IVAR_CHIP_SELECT: 1205bcd91d25SJayachandran C. *result = slot->host.ios.chip_select; 1206831f5dcfSAlexander Motin break; 1207831f5dcfSAlexander Motin case MMCBR_IVAR_CLOCK: 1208bcd91d25SJayachandran C. *result = slot->host.ios.clock; 1209831f5dcfSAlexander Motin break; 1210831f5dcfSAlexander Motin case MMCBR_IVAR_F_MIN: 1211bcd91d25SJayachandran C. *result = slot->host.f_min; 1212831f5dcfSAlexander Motin break; 1213831f5dcfSAlexander Motin case MMCBR_IVAR_F_MAX: 1214bcd91d25SJayachandran C. *result = slot->host.f_max; 1215831f5dcfSAlexander Motin break; 1216831f5dcfSAlexander Motin case MMCBR_IVAR_HOST_OCR: 1217bcd91d25SJayachandran C. *result = slot->host.host_ocr; 1218831f5dcfSAlexander Motin break; 1219831f5dcfSAlexander Motin case MMCBR_IVAR_MODE: 1220bcd91d25SJayachandran C. *result = slot->host.mode; 1221831f5dcfSAlexander Motin break; 1222831f5dcfSAlexander Motin case MMCBR_IVAR_OCR: 1223bcd91d25SJayachandran C. *result = slot->host.ocr; 1224831f5dcfSAlexander Motin break; 1225831f5dcfSAlexander Motin case MMCBR_IVAR_POWER_MODE: 1226bcd91d25SJayachandran C. *result = slot->host.ios.power_mode; 1227831f5dcfSAlexander Motin break; 1228831f5dcfSAlexander Motin case MMCBR_IVAR_VDD: 1229bcd91d25SJayachandran C. *result = slot->host.ios.vdd; 1230831f5dcfSAlexander Motin break; 1231831f5dcfSAlexander Motin case MMCBR_IVAR_CAPS: 1232bcd91d25SJayachandran C. *result = slot->host.caps; 1233831f5dcfSAlexander Motin break; 1234831f5dcfSAlexander Motin case MMCBR_IVAR_TIMING: 1235bcd91d25SJayachandran C. *result = slot->host.ios.timing; 1236831f5dcfSAlexander Motin break; 12373a4a2557SAlexander Motin case MMCBR_IVAR_MAX_DATA: 1238bcd91d25SJayachandran C. *result = 65535; 12393a4a2557SAlexander Motin break; 1240831f5dcfSAlexander Motin } 1241831f5dcfSAlexander Motin return (0); 1242831f5dcfSAlexander Motin } 1243831f5dcfSAlexander Motin 1244*d6b3aaf8SOleksandr Tymoshenko int 1245*d6b3aaf8SOleksandr Tymoshenko sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 1246831f5dcfSAlexander Motin { 1247831f5dcfSAlexander Motin struct sdhci_slot *slot = device_get_ivars(child); 1248831f5dcfSAlexander Motin 1249831f5dcfSAlexander Motin switch (which) { 1250831f5dcfSAlexander Motin default: 1251831f5dcfSAlexander Motin return (EINVAL); 1252831f5dcfSAlexander Motin case MMCBR_IVAR_BUS_MODE: 1253831f5dcfSAlexander Motin slot->host.ios.bus_mode = value; 1254831f5dcfSAlexander Motin break; 1255831f5dcfSAlexander Motin case MMCBR_IVAR_BUS_WIDTH: 1256831f5dcfSAlexander Motin slot->host.ios.bus_width = value; 1257831f5dcfSAlexander Motin break; 1258831f5dcfSAlexander Motin case MMCBR_IVAR_CHIP_SELECT: 1259831f5dcfSAlexander Motin slot->host.ios.chip_select = value; 1260831f5dcfSAlexander Motin break; 1261831f5dcfSAlexander Motin case MMCBR_IVAR_CLOCK: 1262831f5dcfSAlexander Motin if (value > 0) { 1263831f5dcfSAlexander Motin uint32_t clock = slot->max_clk; 1264831f5dcfSAlexander Motin int i; 1265831f5dcfSAlexander Motin 1266831f5dcfSAlexander Motin for (i = 0; i < 8; i++) { 1267831f5dcfSAlexander Motin if (clock <= value) 1268831f5dcfSAlexander Motin break; 1269831f5dcfSAlexander Motin clock >>= 1; 1270831f5dcfSAlexander Motin } 1271831f5dcfSAlexander Motin slot->host.ios.clock = clock; 1272831f5dcfSAlexander Motin } else 1273831f5dcfSAlexander Motin slot->host.ios.clock = 0; 1274831f5dcfSAlexander Motin break; 1275831f5dcfSAlexander Motin case MMCBR_IVAR_MODE: 1276831f5dcfSAlexander Motin slot->host.mode = value; 1277831f5dcfSAlexander Motin break; 1278831f5dcfSAlexander Motin case MMCBR_IVAR_OCR: 1279831f5dcfSAlexander Motin slot->host.ocr = value; 1280831f5dcfSAlexander Motin break; 1281831f5dcfSAlexander Motin case MMCBR_IVAR_POWER_MODE: 1282831f5dcfSAlexander Motin slot->host.ios.power_mode = value; 1283831f5dcfSAlexander Motin break; 1284831f5dcfSAlexander Motin case MMCBR_IVAR_VDD: 1285831f5dcfSAlexander Motin slot->host.ios.vdd = value; 1286831f5dcfSAlexander Motin break; 1287831f5dcfSAlexander Motin case MMCBR_IVAR_TIMING: 1288831f5dcfSAlexander Motin slot->host.ios.timing = value; 1289831f5dcfSAlexander Motin break; 1290831f5dcfSAlexander Motin case MMCBR_IVAR_CAPS: 1291831f5dcfSAlexander Motin case MMCBR_IVAR_HOST_OCR: 1292831f5dcfSAlexander Motin case MMCBR_IVAR_F_MIN: 1293831f5dcfSAlexander Motin case MMCBR_IVAR_F_MAX: 12943a4a2557SAlexander Motin case MMCBR_IVAR_MAX_DATA: 1295831f5dcfSAlexander Motin return (EINVAL); 1296831f5dcfSAlexander Motin } 1297831f5dcfSAlexander Motin return (0); 1298831f5dcfSAlexander Motin } 1299831f5dcfSAlexander Motin 1300*d6b3aaf8SOleksandr Tymoshenko MODULE_VERSION(sdhci, 1); 1301