1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36 #include "opt_mmccam.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/bus.h> 42 #include <sys/callout.h> 43 #include <sys/kernel.h> 44 #include <sys/libkern.h> 45 #include <sys/lock.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/mutex.h> 49 #include <sys/resource.h> 50 #include <sys/rman.h> 51 #include <sys/sysctl.h> 52 #include <sys/taskqueue.h> 53 #include <sys/time.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 #ifdef __arm__ 58 #include <machine/intr.h> 59 60 #include <arm/freescale/imx/imx_ccmvar.h> 61 #endif 62 63 #ifdef __powerpc__ 64 #include <powerpc/mpc85xx/mpc85xx.h> 65 #endif 66 67 #include <dev/gpio/gpiobusvar.h> 68 69 #include <dev/ofw/ofw_bus.h> 70 #include <dev/ofw/ofw_bus_subr.h> 71 72 #include <dev/mmc/bridge.h> 73 74 #include <dev/sdhci/sdhci.h> 75 #include <dev/sdhci/sdhci_fdt_gpio.h> 76 77 #include "mmcbr_if.h" 78 #include "sdhci_if.h" 79 80 struct fsl_sdhci_softc { 81 device_t dev; 82 struct resource * mem_res; 83 struct resource * irq_res; 84 void * intr_cookie; 85 struct sdhci_slot slot; 86 struct callout r1bfix_callout; 87 sbintime_t r1bfix_timeout_at; 88 struct sdhci_fdt_gpio * gpio; 89 uint32_t baseclk_hz; 90 uint32_t cmd_and_mode; 91 uint32_t r1bfix_intmask; 92 uint16_t sdclockreg_freq_bits; 93 uint8_t r1bfix_type; 94 uint8_t hwtype; 95 bool slot_init_done; 96 }; 97 98 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 99 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 100 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 101 102 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 103 #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */ 104 #define HWTYPE_USDHC 2 /* fsl6. */ 105 106 /* 107 * Freescale-specific registers, or in some cases the layout of bits within the 108 * sdhci-defined register is different on Freescale. These names all begin with 109 * SDHC_ (not SDHCI_). 110 */ 111 112 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 113 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 114 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 115 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 116 #define SDHC_VEND_IPGEN (1 << 11) 117 #define SDHC_VEND_HCKEN (1 << 12) 118 #define SDHC_VEND_PEREN (1 << 13) 119 120 #define SDHC_PRES_STATE 0x24 121 #define SDHC_PRES_CIHB (1 << 0) 122 #define SDHC_PRES_CDIHB (1 << 1) 123 #define SDHC_PRES_DLA (1 << 2) 124 #define SDHC_PRES_SDSTB (1 << 3) 125 #define SDHC_PRES_IPGOFF (1 << 4) 126 #define SDHC_PRES_HCKOFF (1 << 5) 127 #define SDHC_PRES_PEROFF (1 << 6) 128 #define SDHC_PRES_SDOFF (1 << 7) 129 #define SDHC_PRES_WTA (1 << 8) 130 #define SDHC_PRES_RTA (1 << 9) 131 #define SDHC_PRES_BWEN (1 << 10) 132 #define SDHC_PRES_BREN (1 << 11) 133 #define SDHC_PRES_RTR (1 << 12) 134 #define SDHC_PRES_CINST (1 << 16) 135 #define SDHC_PRES_CDPL (1 << 18) 136 #define SDHC_PRES_WPSPL (1 << 19) 137 #define SDHC_PRES_CLSL (1 << 23) 138 #define SDHC_PRES_DLSL_SHIFT 24 139 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 140 141 #define SDHC_PROT_CTRL 0x28 142 #define SDHC_PROT_LED (1 << 0) 143 #define SDHC_PROT_WIDTH_1BIT (0 << 1) 144 #define SDHC_PROT_WIDTH_4BIT (1 << 1) 145 #define SDHC_PROT_WIDTH_8BIT (2 << 1) 146 #define SDHC_PROT_WIDTH_MASK (3 << 1) 147 #define SDHC_PROT_D3CD (1 << 3) 148 #define SDHC_PROT_EMODE_BIG (0 << 4) 149 #define SDHC_PROT_EMODE_HALF (1 << 4) 150 #define SDHC_PROT_EMODE_LITTLE (2 << 4) 151 #define SDHC_PROT_EMODE_MASK (3 << 4) 152 #define SDHC_PROT_SDMA (0 << 8) 153 #define SDHC_PROT_ADMA1 (1 << 8) 154 #define SDHC_PROT_ADMA2 (2 << 8) 155 #define SDHC_PROT_ADMA264 (3 << 8) 156 #define SDHC_PROT_DMA_MASK (3 << 8) 157 #define SDHC_PROT_CDTL (1 << 6) 158 #define SDHC_PROT_CDSS (1 << 7) 159 160 #define SDHC_SYS_CTRL 0x2c 161 162 /* 163 * The clock enable bits exist in different registers for ESDHC vs USDHC, but 164 * they are the same bits in both cases. The divisor values go into the 165 * standard sdhci clock register, but in different bit positions and meanings 166 than the sdhci spec values. 167 */ 168 #define SDHC_CLK_IPGEN (1 << 0) 169 #define SDHC_CLK_HCKEN (1 << 1) 170 #define SDHC_CLK_PEREN (1 << 2) 171 #define SDHC_CLK_SDCLKEN (1 << 3) 172 #define SDHC_CLK_ENABLE_MASK 0x0000000f 173 #define SDHC_CLK_DIVISOR_MASK 0x000000f0 174 #define SDHC_CLK_DIVISOR_SHIFT 4 175 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00 176 #define SDHC_CLK_PRESCALE_SHIFT 8 177 178 static struct ofw_compat_data compat_data[] = { 179 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 180 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 181 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 182 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 183 {"fsl,esdhc", HWTYPE_ESDHC}, 184 {NULL, HWTYPE_NONE}, 185 }; 186 187 static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc); 188 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val); 189 static void fsl_sdhci_r1bfix_func(void *arg); 190 191 static inline uint32_t 192 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) 193 { 194 195 return (bus_read_4(sc->mem_res, off)); 196 } 197 198 static inline void 199 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) 200 { 201 202 bus_write_4(sc->mem_res, off, val); 203 } 204 205 static uint8_t 206 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 207 { 208 struct fsl_sdhci_softc *sc = device_get_softc(dev); 209 uint32_t val32, wrk32; 210 211 /* 212 * Most of the things in the standard host control register are in the 213 * hardware's wider protocol control register, but some of the bits are 214 * moved around. 215 */ 216 if (off == SDHCI_HOST_CONTROL) { 217 wrk32 = RD4(sc, SDHC_PROT_CTRL); 218 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 219 SDHCI_CTRL_FORCE_CARD); 220 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 221 case SDHC_PROT_WIDTH_1BIT: 222 /* Value is already 0. */ 223 break; 224 case SDHC_PROT_WIDTH_4BIT: 225 val32 |= SDHCI_CTRL_4BITBUS; 226 break; 227 case SDHC_PROT_WIDTH_8BIT: 228 val32 |= SDHCI_CTRL_8BITBUS; 229 break; 230 } 231 switch (wrk32 & SDHC_PROT_DMA_MASK) { 232 case SDHC_PROT_SDMA: 233 /* Value is already 0. */ 234 break; 235 case SDHC_PROT_ADMA1: 236 /* This value is deprecated, should never appear. */ 237 break; 238 case SDHC_PROT_ADMA2: 239 val32 |= SDHCI_CTRL_ADMA2; 240 break; 241 case SDHC_PROT_ADMA264: 242 val32 |= SDHCI_CTRL_ADMA264; 243 break; 244 } 245 return val32; 246 } 247 248 /* 249 * XXX can't find the bus power on/off knob. For now we have to say the 250 * power is always on and always set to the same voltage. 251 */ 252 if (off == SDHCI_POWER_CONTROL) { 253 return (SDHCI_POWER_ON | SDHCI_POWER_300); 254 } 255 256 257 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 258 } 259 260 static uint16_t 261 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 262 { 263 struct fsl_sdhci_softc *sc = device_get_softc(dev); 264 uint32_t val32; 265 266 if (sc->hwtype == HWTYPE_USDHC) { 267 /* 268 * The USDHC hardware has nothing in the version register, but 269 * it's v3 compatible with all our translation code. 270 */ 271 if (off == SDHCI_HOST_VERSION) { 272 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 273 } 274 /* 275 * The USDHC hardware moved the transfer mode bits to the mixed 276 * control register, fetch them from there. 277 */ 278 if (off == SDHCI_TRANSFER_MODE) 279 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 280 281 } else if (sc->hwtype == HWTYPE_ESDHC) { 282 283 /* 284 * The ESDHC hardware has the typical 32-bit combined "command 285 * and mode" register that we have to cache so that command 286 * isn't written until after mode. On a read, just retrieve the 287 * cached values last written. 288 */ 289 if (off == SDHCI_TRANSFER_MODE) { 290 return (sc->cmd_and_mode & 0x0000ffff); 291 } else if (off == SDHCI_COMMAND_FLAGS) { 292 return (sc->cmd_and_mode >> 16); 293 } 294 } 295 296 /* 297 * This hardware only manages one slot. Synthesize a slot interrupt 298 * status register... if there are any enabled interrupts active they 299 * must be coming from our one and only slot. 300 */ 301 if (off == SDHCI_SLOT_INT_STATUS) { 302 val32 = RD4(sc, SDHCI_INT_STATUS); 303 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 304 return (val32 ? 1 : 0); 305 } 306 307 /* 308 * Clock bits are scattered into various registers which differ by 309 * hardware type, complex enough to have their own function. 310 */ 311 if (off == SDHCI_CLOCK_CONTROL) { 312 return (fsl_sdhc_get_clock(sc)); 313 } 314 315 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 316 } 317 318 static uint32_t 319 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 320 { 321 struct fsl_sdhci_softc *sc = device_get_softc(dev); 322 uint32_t val32, wrk32; 323 324 val32 = RD4(sc, off); 325 326 /* 327 * The hardware leaves the base clock frequency out of the capabilities 328 * register, but we filled it in by setting slot->max_clk at attach time 329 * rather than here, because we can't represent frequencies above 63MHz 330 * in an sdhci 2.0 capabliities register. The timeout clock is the same 331 * as the active output sdclock; we indicate that with a quirk setting 332 * so don't populate the timeout frequency bits. 333 * 334 * XXX Turn off (for now) features the hardware can do but this driver 335 * doesn't yet handle (1.8v, suspend/resume, etc). 336 */ 337 if (off == SDHCI_CAPABILITIES) { 338 val32 &= ~SDHCI_CAN_VDD_180; 339 val32 &= ~SDHCI_CAN_DO_SUSPEND; 340 val32 |= SDHCI_CAN_DO_8BITBUS; 341 return (val32); 342 } 343 344 /* 345 * The hardware moves bits around in the present state register to make 346 * room for all 8 data line state bits. To translate, mask out all the 347 * bits which are not in the same position in both registers (this also 348 * masks out some Freescale-specific bits in locations defined as 349 * reserved by sdhci), then shift the data line and retune request bits 350 * down to their standard locations. 351 */ 352 if (off == SDHCI_PRESENT_STATE) { 353 wrk32 = val32; 354 val32 &= 0x000F0F07; 355 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 356 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 357 return (val32); 358 } 359 360 /* 361 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a 362 * command with an R1B response, mix it into the hardware status. 363 */ 364 if (off == SDHCI_INT_STATUS) { 365 return (val32 | sc->r1bfix_intmask); 366 } 367 368 return val32; 369 } 370 371 static void 372 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 373 uint32_t *data, bus_size_t count) 374 { 375 struct fsl_sdhci_softc *sc = device_get_softc(dev); 376 377 bus_read_multi_4(sc->mem_res, off, data, count); 378 } 379 380 static void 381 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 382 { 383 struct fsl_sdhci_softc *sc = device_get_softc(dev); 384 uint32_t val32; 385 386 /* 387 * Most of the things in the standard host control register are in the 388 * hardware's wider protocol control register, but some of the bits are 389 * moved around. 390 */ 391 if (off == SDHCI_HOST_CONTROL) { 392 val32 = RD4(sc, SDHC_PROT_CTRL); 393 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 394 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 395 val32 |= (val & SDHCI_CTRL_LED); 396 if (val & SDHCI_CTRL_8BITBUS) 397 val32 |= SDHC_PROT_WIDTH_8BIT; 398 else 399 val32 |= (val & SDHCI_CTRL_4BITBUS); 400 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 401 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 402 WR4(sc, SDHC_PROT_CTRL, val32); 403 return; 404 } 405 406 /* XXX I can't find the bus power on/off knob; do nothing. */ 407 if (off == SDHCI_POWER_CONTROL) { 408 return; 409 } 410 #ifdef __powerpc__ 411 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */ 412 if (off == SDHCI_SOFTWARE_RESET) 413 return; 414 #endif 415 416 val32 = RD4(sc, off & ~3); 417 val32 &= ~(0xff << (off & 3) * 8); 418 val32 |= (val << (off & 3) * 8); 419 420 WR4(sc, off & ~3, val32); 421 } 422 423 static void 424 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 425 { 426 struct fsl_sdhci_softc *sc = device_get_softc(dev); 427 uint32_t val32; 428 429 /* 430 * The clock control stuff is complex enough to have its own function 431 * that can handle the ESDHC versus USDHC differences. 432 */ 433 if (off == SDHCI_CLOCK_CONTROL) { 434 fsl_sdhc_set_clock(sc, val); 435 return; 436 } 437 438 /* 439 * Figure out whether we need to check the DAT0 line for busy status at 440 * interrupt time. The controller should be doing this, but for some 441 * reason it doesn't. There are two cases: 442 * - R1B response with no data transfer should generate a DATA_END (aka 443 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 444 * there's no data transfer there's no DATA_END interrupt. This is 445 * documented; they seem to think it's a feature. 446 * - R1B response after Auto-CMD12 appears to not work, even though 447 * there's a control bit for it (bit 3) in the vendor register. 448 * When we're starting a command that needs a manual DAT0 line check at 449 * interrupt time, we leave ourselves a note in r1bfix_type so that we 450 * can do the extra work in fsl_sdhci_intr(). 451 */ 452 if (off == SDHCI_COMMAND_FLAGS) { 453 if (val & SDHCI_CMD_DATA) { 454 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 455 val32 = RD4(sc, USDHC_MIX_CONTROL); 456 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 457 sc->r1bfix_type = R1BFIX_AC12; 458 } else { 459 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 460 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 461 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 462 sc->r1bfix_type = R1BFIX_NODATA; 463 } 464 } 465 } 466 467 /* 468 * The USDHC hardware moved the transfer mode bits to mixed control; we 469 * just write them there and we're done. The ESDHC hardware has the 470 * typical combined cmd-and-mode register that allows only 32-bit 471 * access, so when writing the mode bits just save them, then later when 472 * writing the command bits, add in the saved mode bits. 473 */ 474 if (sc->hwtype == HWTYPE_USDHC) { 475 if (off == SDHCI_TRANSFER_MODE) { 476 val32 = RD4(sc, USDHC_MIX_CONTROL); 477 val32 &= ~0x3f; 478 val32 |= val & 0x37; 479 // XXX acmd23 not supported here (or by sdhci driver) 480 WR4(sc, USDHC_MIX_CONTROL, val32); 481 return; 482 } 483 } else if (sc->hwtype == HWTYPE_ESDHC) { 484 if (off == SDHCI_TRANSFER_MODE) { 485 sc->cmd_and_mode = 486 (sc->cmd_and_mode & 0xffff0000) | val; 487 return; 488 } else if (off == SDHCI_COMMAND_FLAGS) { 489 sc->cmd_and_mode = 490 (sc->cmd_and_mode & 0xffff) | (val << 16); 491 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 492 return; 493 } 494 } 495 496 val32 = RD4(sc, off & ~3); 497 val32 &= ~(0xffff << (off & 3) * 8); 498 val32 |= ((val & 0xffff) << (off & 3) * 8); 499 WR4(sc, off & ~3, val32); 500 } 501 502 static void 503 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 504 { 505 struct fsl_sdhci_softc *sc = device_get_softc(dev); 506 507 /* Clear synthesized interrupts, then pass the value to the hardware. */ 508 if (off == SDHCI_INT_STATUS) { 509 sc->r1bfix_intmask &= ~val; 510 } 511 512 WR4(sc, off, val); 513 } 514 515 static void 516 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 517 uint32_t *data, bus_size_t count) 518 { 519 struct fsl_sdhci_softc *sc = device_get_softc(dev); 520 521 bus_write_multi_4(sc->mem_res, off, data, count); 522 } 523 524 static uint16_t 525 fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc) 526 { 527 uint16_t val; 528 529 /* 530 * Whenever the sdhci driver writes the clock register we save a 531 * snapshot of just the frequency bits, so that we can play them back 532 * here on a register read without recalculating the frequency from the 533 * prescalar and divisor bits in the real register. We'll start with 534 * those bits, and mix in the clock status and enable bits that come 535 * from different places depending on which hardware we've got. 536 */ 537 val = sc->sdclockreg_freq_bits; 538 539 /* 540 * The internal clock is always enabled (actually, the hardware manages 541 * it). Whether the internal clock is stable yet after a frequency 542 * change comes from the present-state register on both hardware types. 543 */ 544 val |= SDHCI_CLOCK_INT_EN; 545 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) 546 val |= SDHCI_CLOCK_INT_STABLE; 547 548 /* 549 * On i.MX ESDHC hardware the card bus clock enable is in the usual 550 * sdhci register but it's a different bit, so transcribe it (note the 551 * difference between standard SDHCI_ and Freescale SDHC_ prefixes 552 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but 553 * no force-off for the card bus clock (the hardware runs the clock when 554 * transfers are active no matter what), so we always say the clock is 555 * on. 556 * XXX Maybe we should say it's in whatever state the sdhci driver last 557 * set it to. 558 */ 559 if (sc->hwtype == HWTYPE_ESDHC) { 560 #ifdef __arm__ 561 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) 562 #endif 563 val |= SDHCI_CLOCK_CARD_EN; 564 } else { 565 val |= SDHCI_CLOCK_CARD_EN; 566 } 567 568 return (val); 569 } 570 571 static void 572 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val) 573 { 574 uint32_t divisor, freq, prescale, val32; 575 576 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 577 578 /* 579 * Save the frequency-setting bits in SDHCI format so that we can play 580 * them back in get_clock without complex decoding of hardware regs, 581 * then deal with the freqency part of the value based on hardware type. 582 */ 583 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; 584 if (sc->hwtype == HWTYPE_ESDHC) { 585 /* 586 * The i.MX5 ESDHC hardware requires the driver to manually 587 * start and stop the sd bus clock. If the enable bit is not 588 * set, turn off the clock in hardware and we're done, otherwise 589 * decode the requested frequency. ESDHC hardware is sdhci 2.0; 590 * the sdhci driver will use the original 8-bit divisor field 591 * and the "base / 2^N" divisor scheme. 592 */ 593 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 594 #ifdef __arm__ 595 /* On QorIQ, this is a reserved bit. */ 596 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); 597 #endif 598 return; 599 600 } 601 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 602 freq = sc->baseclk_hz >> ffs(divisor); 603 } else { 604 /* 605 * The USDHC hardware provides only "force always on" control 606 * over the sd bus clock, but no way to turn it off. (If a cmd 607 * or data transfer is in progress the clock is on, otherwise it 608 * is off.) If the clock is being disabled, we can just return 609 * now, otherwise we decode the requested frequency. USDHC 610 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit 611 * divisor using the "base / 2*N" divisor scheme. 612 */ 613 if ((val & SDHCI_CLOCK_CARD_EN) == 0) 614 return; 615 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 616 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 617 SDHCI_DIVIDER_MASK_LEN; 618 if (divisor == 0) 619 freq = sc->baseclk_hz; 620 else 621 freq = sc->baseclk_hz / (2 * divisor); 622 } 623 624 /* 625 * Get a prescaler and final divisor to achieve the desired frequency. 626 */ 627 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) 628 prescale <<= 1; 629 630 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) 631 ++divisor; 632 633 #ifdef DEBUG 634 device_printf(sc->dev, 635 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", 636 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, 637 prescale, divisor); 638 #endif 639 640 /* 641 * Adjust to zero-based values, and store them to the hardware. 642 */ 643 prescale >>= 1; 644 divisor -= 1; 645 646 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); 647 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 648 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 649 val32 |= SDHC_CLK_IPGEN; 650 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 651 } 652 653 static boolean_t 654 fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc) 655 { 656 uint32_t inhibit; 657 658 mtx_assert(&sc->slot.mtx, MA_OWNED); 659 660 /* 661 * Check the DAT0 line status using both the DLA (data line active) and 662 * CDIHB (data inhibit) bits in the present state register. In theory 663 * just DLA should do the trick, but in practice it takes both. If the 664 * DAT0 line is still being held and we're not yet beyond the timeout 665 * point, just schedule another callout to check again later. 666 */ 667 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 668 669 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 670 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 671 fsl_sdhci_r1bfix_func, sc, 0); 672 return (false); 673 } 674 675 /* 676 * If we reach this point with the inhibit bits still set, we've got a 677 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 678 * line has been released, and we synthesize a DATA_END, and if the type 679 * of fix needed was on a command-without-data we also now add in the 680 * original INT_RESPONSE that we suppressed earlier. 681 */ 682 if (inhibit) 683 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 684 else { 685 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 686 if (sc->r1bfix_type == R1BFIX_NODATA) 687 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 688 } 689 690 sc->r1bfix_type = R1BFIX_NONE; 691 return (true); 692 } 693 694 static void 695 fsl_sdhci_r1bfix_func(void * arg) 696 { 697 struct fsl_sdhci_softc *sc = arg; 698 boolean_t r1bwait_done; 699 700 mtx_lock(&sc->slot.mtx); 701 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc); 702 mtx_unlock(&sc->slot.mtx); 703 if (r1bwait_done) 704 sdhci_generic_intr(&sc->slot); 705 } 706 707 static void 708 fsl_sdhci_intr(void *arg) 709 { 710 struct fsl_sdhci_softc *sc = arg; 711 uint32_t intmask; 712 713 mtx_lock(&sc->slot.mtx); 714 715 /* 716 * Manually check the DAT0 line for R1B response types that the 717 * controller fails to handle properly. The controller asserts the done 718 * interrupt while the card is still asserting busy with the DAT0 line. 719 * 720 * We check DAT0 immediately because most of the time, especially on a 721 * read, the card will actually be done by time we get here. If it's 722 * not, then the wait_done routine will schedule a callout to re-check 723 * periodically until it is done. In that case we clear the interrupt 724 * out of the hardware now so that we can present it later when the DAT0 725 * line is released. 726 * 727 * If we need to wait for the DAT0 line to be released, we set up a 728 * timeout point 250ms in the future. This number comes from the SD 729 * spec, which allows a command to take that long. In the real world, 730 * cards tend to take 10-20ms for a long-running command such as a write 731 * or erase that spans two pages. 732 */ 733 switch (sc->r1bfix_type) { 734 case R1BFIX_NODATA: 735 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE; 736 break; 737 case R1BFIX_AC12: 738 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END; 739 break; 740 default: 741 intmask = 0; 742 break; 743 } 744 if (intmask) { 745 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 746 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) { 747 WR4(sc, SDHCI_INT_STATUS, intmask); 748 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, 749 BUS_SPACE_BARRIER_WRITE); 750 } 751 } 752 753 mtx_unlock(&sc->slot.mtx); 754 sdhci_generic_intr(&sc->slot); 755 } 756 757 static int 758 fsl_sdhci_get_ro(device_t bus, device_t child) 759 { 760 struct fsl_sdhci_softc *sc = device_get_softc(bus); 761 762 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 763 } 764 765 static bool 766 fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 767 { 768 struct fsl_sdhci_softc *sc = device_get_softc(dev); 769 770 return (sdhci_fdt_gpio_get_present(sc->gpio)); 771 } 772 773 #ifdef __powerpc__ 774 static uint32_t 775 fsl_sdhci_get_platform_clock(device_t dev) 776 { 777 phandle_t node; 778 uint32_t clock; 779 780 node = ofw_bus_get_node(dev); 781 782 /* Get sdhci node properties */ 783 if((OF_getprop(node, "clock-frequency", (void *)&clock, 784 sizeof(clock)) <= 0) || (clock == 0)) { 785 786 clock = mpc85xx_get_system_clock(); 787 788 if (clock == 0) { 789 device_printf(dev,"Cannot acquire correct sdhci " 790 "frequency from DTS.\n"); 791 792 return (0); 793 } 794 } 795 796 if (bootverbose) 797 device_printf(dev, "Acquired clock: %d from DTS\n", clock); 798 799 return (clock); 800 } 801 #endif 802 803 804 static int 805 fsl_sdhci_detach(device_t dev) 806 { 807 struct fsl_sdhci_softc *sc = device_get_softc(dev); 808 809 if (sc->gpio != NULL) 810 sdhci_fdt_gpio_teardown(sc->gpio); 811 812 callout_drain(&sc->r1bfix_callout); 813 814 if (sc->slot_init_done) 815 sdhci_cleanup_slot(&sc->slot); 816 817 if (sc->intr_cookie != NULL) 818 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 819 if (sc->irq_res != NULL) 820 bus_release_resource(dev, SYS_RES_IRQ, 821 rman_get_rid(sc->irq_res), sc->irq_res); 822 823 if (sc->mem_res != NULL) { 824 bus_release_resource(dev, SYS_RES_MEMORY, 825 rman_get_rid(sc->mem_res), sc->mem_res); 826 } 827 828 return (0); 829 } 830 831 static int 832 fsl_sdhci_attach(device_t dev) 833 { 834 struct fsl_sdhci_softc *sc = device_get_softc(dev); 835 int rid, err; 836 #ifdef __powerpc__ 837 phandle_t node; 838 uint32_t protctl; 839 #endif 840 841 sc->dev = dev; 842 843 callout_init(&sc->r1bfix_callout, 1); 844 845 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 846 if (sc->hwtype == HWTYPE_NONE) 847 panic("Impossible: not compatible in fsl_sdhci_attach()"); 848 849 rid = 0; 850 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 851 RF_ACTIVE); 852 if (!sc->mem_res) { 853 device_printf(dev, "cannot allocate memory window\n"); 854 err = ENXIO; 855 goto fail; 856 } 857 858 rid = 0; 859 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 860 RF_ACTIVE); 861 if (!sc->irq_res) { 862 device_printf(dev, "cannot allocate interrupt\n"); 863 err = ENXIO; 864 goto fail; 865 } 866 867 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 868 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { 869 device_printf(dev, "cannot setup interrupt handler\n"); 870 err = ENXIO; 871 goto fail; 872 } 873 874 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 875 876 /* 877 * DMA is not really broken, I just haven't implemented it yet. 878 */ 879 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 880 881 /* 882 * Set the buffer watermark level to 128 words (512 bytes) for both read 883 * and write. The hardware has a restriction that when the read or 884 * write ready status is asserted, that means you can read exactly the 885 * number of words set in the watermark register before you have to 886 * re-check the status and potentially wait for more data. The main 887 * sdhci driver provides no hook for doing status checking on less than 888 * a full block boundary, so we set the watermark level to be a full 889 * block. Reads and writes where the block size is less than the 890 * watermark size will work correctly too, no need to change the 891 * watermark for different size blocks. However, 128 is the maximum 892 * allowed for the watermark, so PIO is limitted to 512 byte blocks 893 * (which works fine for SD cards, may be a problem for SDIO some day). 894 * 895 * XXX need named constants for this stuff. 896 */ 897 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */ 898 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) 899 WR4(sc, SDHC_WTMK_LVL, 0x10801080); 900 else 901 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 902 903 /* 904 * We read in native byte order in the main driver, but the register 905 * defaults to little endian. 906 */ 907 #ifdef __powerpc__ 908 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); 909 #else 910 sc->baseclk_hz = imx_ccm_sdhci_hz(); 911 #endif 912 sc->slot.max_clk = sc->baseclk_hz; 913 914 /* 915 * Set up any gpio pin handling described in the FDT data. This cannot 916 * fail; see comments in sdhci_fdt_gpio.h for details. 917 */ 918 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 919 920 #ifdef __powerpc__ 921 node = ofw_bus_get_node(dev); 922 /* Default to big-endian on powerpc */ 923 protctl = RD4(sc, SDHC_PROT_CTRL); 924 protctl &= ~SDHC_PROT_EMODE_MASK; 925 if (OF_hasprop(node, "little-endian")) 926 protctl |= SDHC_PROT_EMODE_LITTLE; 927 else 928 protctl |= SDHC_PROT_EMODE_BIG; 929 WR4(sc, SDHC_PROT_CTRL, protctl); 930 #endif 931 932 sdhci_init_slot(dev, &sc->slot, 0); 933 sc->slot_init_done = true; 934 935 bus_generic_probe(dev); 936 bus_generic_attach(dev); 937 938 sdhci_start_slot(&sc->slot); 939 940 return (0); 941 942 fail: 943 fsl_sdhci_detach(dev); 944 return (err); 945 } 946 947 static int 948 fsl_sdhci_probe(device_t dev) 949 { 950 951 if (!ofw_bus_status_okay(dev)) 952 return (ENXIO); 953 954 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 955 case HWTYPE_ESDHC: 956 device_set_desc(dev, "Freescale eSDHC controller"); 957 return (BUS_PROBE_DEFAULT); 958 case HWTYPE_USDHC: 959 device_set_desc(dev, "Freescale uSDHC controller"); 960 return (BUS_PROBE_DEFAULT); 961 default: 962 break; 963 } 964 return (ENXIO); 965 } 966 967 static device_method_t fsl_sdhci_methods[] = { 968 /* Device interface */ 969 DEVMETHOD(device_probe, fsl_sdhci_probe), 970 DEVMETHOD(device_attach, fsl_sdhci_attach), 971 DEVMETHOD(device_detach, fsl_sdhci_detach), 972 973 /* Bus interface */ 974 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 975 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 976 977 /* MMC bridge interface */ 978 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 979 DEVMETHOD(mmcbr_request, sdhci_generic_request), 980 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro), 981 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 982 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 983 984 /* SDHCI accessors */ 985 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1), 986 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2), 987 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4), 988 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4), 989 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1), 990 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2), 991 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4), 992 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4), 993 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present), 994 995 DEVMETHOD_END 996 }; 997 998 static devclass_t fsl_sdhci_devclass; 999 1000 static driver_t fsl_sdhci_driver = { 1001 "sdhci_fsl", 1002 fsl_sdhci_methods, 1003 sizeof(struct fsl_sdhci_softc), 1004 }; 1005 1006 DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass, 1007 NULL, NULL); 1008 SDHCI_DEPEND(sdhci_fsl); 1009 1010 #ifndef MMCCAM 1011 MMC_DECLARE_BRIDGE(sdhci_fsl); 1012 #endif 1013