1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/bus.h> 40 #include <sys/callout.h> 41 #include <sys/endian.h> 42 #include <sys/kernel.h> 43 #include <sys/libkern.h> 44 #include <sys/lock.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/mutex.h> 48 #include <sys/resource.h> 49 #include <sys/rman.h> 50 #include <sys/sysctl.h> 51 #include <sys/taskqueue.h> 52 #include <sys/time.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #ifdef __arm__ 57 #include <machine/intr.h> 58 59 #include <arm/freescale/imx/imx_ccmvar.h> 60 #endif 61 62 #include <dev/gpio/gpiobusvar.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 66 #include <dev/mmc/bridge.h> 67 #include <dev/mmc/mmcreg.h> 68 #include <dev/mmc/mmcbrvar.h> 69 70 #include <dev/sdhci/sdhci.h> 71 #include <dev/sdhci/sdhci_fdt_gpio.h> 72 #include "sdhci_if.h" 73 74 struct fsl_sdhci_softc { 75 device_t dev; 76 struct resource * mem_res; 77 struct resource * irq_res; 78 void * intr_cookie; 79 struct sdhci_slot slot; 80 struct callout r1bfix_callout; 81 sbintime_t r1bfix_timeout_at; 82 struct sdhci_fdt_gpio * gpio; 83 uint32_t baseclk_hz; 84 uint32_t cmd_and_mode; 85 uint32_t r1bfix_intmask; 86 uint16_t sdclockreg_freq_bits; 87 uint8_t r1bfix_type; 88 uint8_t hwtype; 89 }; 90 91 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 92 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 93 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 94 95 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 96 #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */ 97 #define HWTYPE_USDHC 2 /* fsl6. */ 98 99 /* 100 * Freescale-specific registers, or in some cases the layout of bits within the 101 * sdhci-defined register is different on Freescale. These names all begin with 102 * SDHC_ (not SDHCI_). 103 */ 104 105 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 106 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 107 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 108 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 109 #define SDHC_VEND_IPGEN (1 << 11) 110 #define SDHC_VEND_HCKEN (1 << 12) 111 #define SDHC_VEND_PEREN (1 << 13) 112 113 #define SDHC_PRES_STATE 0x24 114 #define SDHC_PRES_CIHB (1 << 0) 115 #define SDHC_PRES_CDIHB (1 << 1) 116 #define SDHC_PRES_DLA (1 << 2) 117 #define SDHC_PRES_SDSTB (1 << 3) 118 #define SDHC_PRES_IPGOFF (1 << 4) 119 #define SDHC_PRES_HCKOFF (1 << 5) 120 #define SDHC_PRES_PEROFF (1 << 6) 121 #define SDHC_PRES_SDOFF (1 << 7) 122 #define SDHC_PRES_WTA (1 << 8) 123 #define SDHC_PRES_RTA (1 << 9) 124 #define SDHC_PRES_BWEN (1 << 10) 125 #define SDHC_PRES_BREN (1 << 11) 126 #define SDHC_PRES_RTR (1 << 12) 127 #define SDHC_PRES_CINST (1 << 16) 128 #define SDHC_PRES_CDPL (1 << 18) 129 #define SDHC_PRES_WPSPL (1 << 19) 130 #define SDHC_PRES_CLSL (1 << 23) 131 #define SDHC_PRES_DLSL_SHIFT 24 132 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 133 134 #define SDHC_PROT_CTRL 0x28 135 #define SDHC_PROT_LED (1 << 0) 136 #define SDHC_PROT_WIDTH_1BIT (0 << 1) 137 #define SDHC_PROT_WIDTH_4BIT (1 << 1) 138 #define SDHC_PROT_WIDTH_8BIT (2 << 1) 139 #define SDHC_PROT_WIDTH_MASK (3 << 1) 140 #define SDHC_PROT_D3CD (1 << 3) 141 #define SDHC_PROT_EMODE_BIG (0 << 4) 142 #define SDHC_PROT_EMODE_HALF (1 << 4) 143 #define SDHC_PROT_EMODE_LITTLE (2 << 4) 144 #define SDHC_PROT_EMODE_MASK (3 << 4) 145 #define SDHC_PROT_SDMA (0 << 8) 146 #define SDHC_PROT_ADMA1 (1 << 8) 147 #define SDHC_PROT_ADMA2 (2 << 8) 148 #define SDHC_PROT_ADMA264 (3 << 8) 149 #define SDHC_PROT_DMA_MASK (3 << 8) 150 #define SDHC_PROT_CDTL (1 << 6) 151 #define SDHC_PROT_CDSS (1 << 7) 152 153 #define SDHC_SYS_CTRL 0x2c 154 155 /* 156 * The clock enable bits exist in different registers for ESDHC vs USDHC, but 157 * they are the same bits in both cases. The divisor values go into the 158 * standard sdhci clock register, but in different bit positions and meanings 159 than the sdhci spec values. 160 */ 161 #define SDHC_CLK_IPGEN (1 << 0) 162 #define SDHC_CLK_HCKEN (1 << 1) 163 #define SDHC_CLK_PEREN (1 << 2) 164 #define SDHC_CLK_SDCLKEN (1 << 3) 165 #define SDHC_CLK_ENABLE_MASK 0x0000000f 166 #define SDHC_CLK_DIVISOR_MASK 0x000000f0 167 #define SDHC_CLK_DIVISOR_SHIFT 4 168 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00 169 #define SDHC_CLK_PRESCALE_SHIFT 8 170 171 static struct ofw_compat_data compat_data[] = { 172 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 173 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 174 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 175 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 176 {"fsl,esdhc", HWTYPE_ESDHC}, 177 {NULL, HWTYPE_NONE}, 178 }; 179 180 static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc); 181 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val); 182 static void fsl_sdhci_r1bfix_func(void *arg); 183 184 static inline uint32_t 185 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) 186 { 187 188 return (bus_read_4(sc->mem_res, off)); 189 } 190 191 static inline void 192 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) 193 { 194 195 bus_write_4(sc->mem_res, off, val); 196 } 197 198 static uint8_t 199 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 200 { 201 struct fsl_sdhci_softc *sc = device_get_softc(dev); 202 uint32_t val32, wrk32; 203 204 /* 205 * Most of the things in the standard host control register are in the 206 * hardware's wider protocol control register, but some of the bits are 207 * moved around. 208 */ 209 if (off == SDHCI_HOST_CONTROL) { 210 wrk32 = RD4(sc, SDHC_PROT_CTRL); 211 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 212 SDHCI_CTRL_FORCE_CARD); 213 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 214 case SDHC_PROT_WIDTH_1BIT: 215 /* Value is already 0. */ 216 break; 217 case SDHC_PROT_WIDTH_4BIT: 218 val32 |= SDHCI_CTRL_4BITBUS; 219 break; 220 case SDHC_PROT_WIDTH_8BIT: 221 val32 |= SDHCI_CTRL_8BITBUS; 222 break; 223 } 224 switch (wrk32 & SDHC_PROT_DMA_MASK) { 225 case SDHC_PROT_SDMA: 226 /* Value is already 0. */ 227 break; 228 case SDHC_PROT_ADMA1: 229 /* This value is deprecated, should never appear. */ 230 break; 231 case SDHC_PROT_ADMA2: 232 val32 |= SDHCI_CTRL_ADMA2; 233 break; 234 case SDHC_PROT_ADMA264: 235 val32 |= SDHCI_CTRL_ADMA264; 236 break; 237 } 238 return val32; 239 } 240 241 /* 242 * XXX can't find the bus power on/off knob. For now we have to say the 243 * power is always on and always set to the same voltage. 244 */ 245 if (off == SDHCI_POWER_CONTROL) { 246 return (SDHCI_POWER_ON | SDHCI_POWER_300); 247 } 248 249 250 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 251 } 252 253 static uint16_t 254 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 255 { 256 struct fsl_sdhci_softc *sc = device_get_softc(dev); 257 uint32_t val32; 258 259 if (sc->hwtype == HWTYPE_USDHC) { 260 /* 261 * The USDHC hardware has nothing in the version register, but 262 * it's v3 compatible with all our translation code. 263 */ 264 if (off == SDHCI_HOST_VERSION) { 265 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 266 } 267 /* 268 * The USDHC hardware moved the transfer mode bits to the mixed 269 * control register, fetch them from there. 270 */ 271 if (off == SDHCI_TRANSFER_MODE) 272 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 273 274 } else if (sc->hwtype == HWTYPE_ESDHC) { 275 276 /* 277 * The ESDHC hardware has the typical 32-bit combined "command 278 * and mode" register that we have to cache so that command 279 * isn't written until after mode. On a read, just retrieve the 280 * cached values last written. 281 */ 282 if (off == SDHCI_TRANSFER_MODE) { 283 return (sc->cmd_and_mode & 0x0000ffff); 284 } else if (off == SDHCI_COMMAND_FLAGS) { 285 return (sc->cmd_and_mode >> 16); 286 } 287 } 288 289 /* 290 * This hardware only manages one slot. Synthesize a slot interrupt 291 * status register... if there are any enabled interrupts active they 292 * must be coming from our one and only slot. 293 */ 294 if (off == SDHCI_SLOT_INT_STATUS) { 295 val32 = RD4(sc, SDHCI_INT_STATUS); 296 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 297 return (val32 ? 1 : 0); 298 } 299 300 /* 301 * Clock bits are scattered into various registers which differ by 302 * hardware type, complex enough to have their own function. 303 */ 304 if (off == SDHCI_CLOCK_CONTROL) { 305 return (fsl_sdhc_get_clock(sc)); 306 } 307 308 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 309 } 310 311 static uint32_t 312 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 313 { 314 struct fsl_sdhci_softc *sc = device_get_softc(dev); 315 uint32_t val32, wrk32; 316 317 val32 = RD4(sc, off); 318 319 /* 320 * The hardware leaves the base clock frequency out of the capabilities 321 * register, but we filled it in by setting slot->max_clk at attach time 322 * rather than here, because we can't represent frequencies above 63MHz 323 * in an sdhci 2.0 capabliities register. The timeout clock is the same 324 * as the active output sdclock; we indicate that with a quirk setting 325 * so don't populate the timeout frequency bits. 326 * 327 * XXX Turn off (for now) features the hardware can do but this driver 328 * doesn't yet handle (1.8v, suspend/resume, etc). 329 */ 330 if (off == SDHCI_CAPABILITIES) { 331 val32 &= ~SDHCI_CAN_VDD_180; 332 val32 &= ~SDHCI_CAN_DO_SUSPEND; 333 val32 |= SDHCI_CAN_DO_8BITBUS; 334 return (val32); 335 } 336 337 /* 338 * The hardware moves bits around in the present state register to make 339 * room for all 8 data line state bits. To translate, mask out all the 340 * bits which are not in the same position in both registers (this also 341 * masks out some Freescale-specific bits in locations defined as 342 * reserved by sdhci), then shift the data line and retune request bits 343 * down to their standard locations. 344 */ 345 if (off == SDHCI_PRESENT_STATE) { 346 wrk32 = val32; 347 val32 &= 0x000F0F07; 348 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 349 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 350 return (val32); 351 } 352 353 /* 354 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a 355 * command with an R1B response, mix it into the hardware status. 356 */ 357 if (off == SDHCI_INT_STATUS) { 358 return (val32 | sc->r1bfix_intmask); 359 } 360 361 return val32; 362 } 363 364 static void 365 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 366 uint32_t *data, bus_size_t count) 367 { 368 struct fsl_sdhci_softc *sc = device_get_softc(dev); 369 370 bus_read_multi_4(sc->mem_res, off, data, count); 371 } 372 373 static void 374 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 375 { 376 struct fsl_sdhci_softc *sc = device_get_softc(dev); 377 uint32_t val32; 378 379 /* 380 * Most of the things in the standard host control register are in the 381 * hardware's wider protocol control register, but some of the bits are 382 * moved around. 383 */ 384 if (off == SDHCI_HOST_CONTROL) { 385 val32 = RD4(sc, SDHC_PROT_CTRL); 386 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 387 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 388 val32 |= (val & SDHCI_CTRL_LED); 389 if (val & SDHCI_CTRL_8BITBUS) 390 val32 |= SDHC_PROT_WIDTH_8BIT; 391 else 392 val32 |= (val & SDHCI_CTRL_4BITBUS); 393 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 394 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 395 WR4(sc, SDHC_PROT_CTRL, val32); 396 return; 397 } 398 399 /* XXX I can't find the bus power on/off knob; do nothing. */ 400 if (off == SDHCI_POWER_CONTROL) { 401 return; 402 } 403 #ifdef __powerpc__ 404 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */ 405 if (off == SDHCI_SOFTWARE_RESET) 406 return; 407 #endif 408 409 val32 = RD4(sc, off & ~3); 410 val32 &= ~(0xff << (off & 3) * 8); 411 val32 |= (val << (off & 3) * 8); 412 413 WR4(sc, off & ~3, val32); 414 } 415 416 static void 417 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 418 { 419 struct fsl_sdhci_softc *sc = device_get_softc(dev); 420 uint32_t val32; 421 422 /* 423 * The clock control stuff is complex enough to have its own function 424 * that can handle the ESDHC versus USDHC differences. 425 */ 426 if (off == SDHCI_CLOCK_CONTROL) { 427 fsl_sdhc_set_clock(sc, val); 428 return; 429 } 430 431 /* 432 * Figure out whether we need to check the DAT0 line for busy status at 433 * interrupt time. The controller should be doing this, but for some 434 * reason it doesn't. There are two cases: 435 * - R1B response with no data transfer should generate a DATA_END (aka 436 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 437 * there's no data transfer there's no DATA_END interrupt. This is 438 * documented; they seem to think it's a feature. 439 * - R1B response after Auto-CMD12 appears to not work, even though 440 * there's a control bit for it (bit 3) in the vendor register. 441 * When we're starting a command that needs a manual DAT0 line check at 442 * interrupt time, we leave ourselves a note in r1bfix_type so that we 443 * can do the extra work in fsl_sdhci_intr(). 444 */ 445 if (off == SDHCI_COMMAND_FLAGS) { 446 if (val & SDHCI_CMD_DATA) { 447 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 448 val32 = RD4(sc, USDHC_MIX_CONTROL); 449 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 450 sc->r1bfix_type = R1BFIX_AC12; 451 } else { 452 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 453 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 454 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 455 sc->r1bfix_type = R1BFIX_NODATA; 456 } 457 } 458 } 459 460 /* 461 * The USDHC hardware moved the transfer mode bits to mixed control; we 462 * just write them there and we're done. The ESDHC hardware has the 463 * typical combined cmd-and-mode register that allows only 32-bit 464 * access, so when writing the mode bits just save them, then later when 465 * writing the command bits, add in the saved mode bits. 466 */ 467 if (sc->hwtype == HWTYPE_USDHC) { 468 if (off == SDHCI_TRANSFER_MODE) { 469 val32 = RD4(sc, USDHC_MIX_CONTROL); 470 val32 &= ~0x3f; 471 val32 |= val & 0x37; 472 // XXX acmd23 not supported here (or by sdhci driver) 473 WR4(sc, USDHC_MIX_CONTROL, val32); 474 return; 475 } 476 } else if (sc->hwtype == HWTYPE_ESDHC) { 477 if (off == SDHCI_TRANSFER_MODE) { 478 sc->cmd_and_mode = 479 (sc->cmd_and_mode & 0xffff0000) | val; 480 return; 481 } else if (off == SDHCI_COMMAND_FLAGS) { 482 sc->cmd_and_mode = 483 (sc->cmd_and_mode & 0xffff) | (val << 16); 484 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 485 return; 486 } 487 } 488 489 val32 = RD4(sc, off & ~3); 490 val32 &= ~(0xffff << (off & 3) * 8); 491 val32 |= ((val & 0xffff) << (off & 3) * 8); 492 WR4(sc, off & ~3, val32); 493 } 494 495 static void 496 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 497 { 498 struct fsl_sdhci_softc *sc = device_get_softc(dev); 499 500 /* Clear synthesized interrupts, then pass the value to the hardware. */ 501 if (off == SDHCI_INT_STATUS) { 502 sc->r1bfix_intmask &= ~val; 503 } 504 505 WR4(sc, off, val); 506 } 507 508 static void 509 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 510 uint32_t *data, bus_size_t count) 511 { 512 struct fsl_sdhci_softc *sc = device_get_softc(dev); 513 514 bus_write_multi_4(sc->mem_res, off, data, count); 515 } 516 517 static uint16_t 518 fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc) 519 { 520 uint16_t val; 521 522 /* 523 * Whenever the sdhci driver writes the clock register we save a 524 * snapshot of just the frequency bits, so that we can play them back 525 * here on a register read without recalculating the frequency from the 526 * prescalar and divisor bits in the real register. We'll start with 527 * those bits, and mix in the clock status and enable bits that come 528 * from different places depending on which hardware we've got. 529 */ 530 val = sc->sdclockreg_freq_bits; 531 532 /* 533 * The internal clock is always enabled (actually, the hardware manages 534 * it). Whether the internal clock is stable yet after a frequency 535 * change comes from the present-state register on both hardware types. 536 */ 537 val |= SDHCI_CLOCK_INT_EN; 538 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) 539 val |= SDHCI_CLOCK_INT_STABLE; 540 541 /* 542 * On i.MX ESDHC hardware the card bus clock enable is in the usual 543 * sdhci register but it's a different bit, so transcribe it (note the 544 * difference between standard SDHCI_ and Freescale SDHC_ prefixes 545 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but 546 * no force-off for the card bus clock (the hardware runs the clock when 547 * transfers are active no matter what), so we always say the clock is 548 * on. 549 * XXX Maybe we should say it's in whatever state the sdhci driver last 550 * set it to. 551 */ 552 if (sc->hwtype == HWTYPE_ESDHC) { 553 #ifdef __arm__ 554 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) 555 #endif 556 val |= SDHCI_CLOCK_CARD_EN; 557 } else { 558 val |= SDHCI_CLOCK_CARD_EN; 559 } 560 561 return (val); 562 } 563 564 static void 565 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val) 566 { 567 uint32_t divisor, freq, prescale, val32; 568 569 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 570 571 /* 572 * Save the frequency-setting bits in SDHCI format so that we can play 573 * them back in get_clock without complex decoding of hardware regs, 574 * then deal with the freqency part of the value based on hardware type. 575 */ 576 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; 577 if (sc->hwtype == HWTYPE_ESDHC) { 578 /* 579 * The i.MX5 ESDHC hardware requires the driver to manually 580 * start and stop the sd bus clock. If the enable bit is not 581 * set, turn off the clock in hardware and we're done, otherwise 582 * decode the requested frequency. ESDHC hardware is sdhci 2.0; 583 * the sdhci driver will use the original 8-bit divisor field 584 * and the "base / 2^N" divisor scheme. 585 */ 586 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 587 #ifdef __arm__ 588 /* On QorIQ, this is a reserved bit. */ 589 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); 590 #endif 591 return; 592 593 } 594 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 595 freq = sc->baseclk_hz >> ffs(divisor); 596 } else { 597 /* 598 * The USDHC hardware provides only "force always on" control 599 * over the sd bus clock, but no way to turn it off. (If a cmd 600 * or data transfer is in progress the clock is on, otherwise it 601 * is off.) If the clock is being disabled, we can just return 602 * now, otherwise we decode the requested frequency. USDHC 603 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit 604 * divisor using the "base / 2*N" divisor scheme. 605 */ 606 if ((val & SDHCI_CLOCK_CARD_EN) == 0) 607 return; 608 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 609 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 610 SDHCI_DIVIDER_MASK_LEN; 611 if (divisor == 0) 612 freq = sc->baseclk_hz; 613 else 614 freq = sc->baseclk_hz / (2 * divisor); 615 } 616 617 /* 618 * Get a prescaler and final divisor to achieve the desired frequency. 619 */ 620 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) 621 prescale <<= 1; 622 623 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) 624 ++divisor; 625 626 #ifdef DEBUG 627 device_printf(sc->dev, 628 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", 629 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, 630 prescale, divisor); 631 #endif 632 633 /* 634 * Adjust to zero-based values, and store them to the hardware. 635 */ 636 prescale >>= 1; 637 divisor -= 1; 638 639 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); 640 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 641 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 642 val32 |= SDHC_CLK_IPGEN; 643 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 644 } 645 646 static boolean_t 647 fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc) 648 { 649 uint32_t inhibit; 650 651 mtx_assert(&sc->slot.mtx, MA_OWNED); 652 653 /* 654 * Check the DAT0 line status using both the DLA (data line active) and 655 * CDIHB (data inhibit) bits in the present state register. In theory 656 * just DLA should do the trick, but in practice it takes both. If the 657 * DAT0 line is still being held and we're not yet beyond the timeout 658 * point, just schedule another callout to check again later. 659 */ 660 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 661 662 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 663 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 664 fsl_sdhci_r1bfix_func, sc, 0); 665 return (false); 666 } 667 668 /* 669 * If we reach this point with the inhibit bits still set, we've got a 670 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 671 * line has been released, and we synthesize a DATA_END, and if the type 672 * of fix needed was on a command-without-data we also now add in the 673 * original INT_RESPONSE that we suppressed earlier. 674 */ 675 if (inhibit) 676 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 677 else { 678 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 679 if (sc->r1bfix_type == R1BFIX_NODATA) 680 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 681 } 682 683 sc->r1bfix_type = R1BFIX_NONE; 684 return (true); 685 } 686 687 static void 688 fsl_sdhci_r1bfix_func(void * arg) 689 { 690 struct fsl_sdhci_softc *sc = arg; 691 boolean_t r1bwait_done; 692 693 mtx_lock(&sc->slot.mtx); 694 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc); 695 mtx_unlock(&sc->slot.mtx); 696 if (r1bwait_done) 697 sdhci_generic_intr(&sc->slot); 698 } 699 700 static void 701 fsl_sdhci_intr(void *arg) 702 { 703 struct fsl_sdhci_softc *sc = arg; 704 uint32_t intmask; 705 706 mtx_lock(&sc->slot.mtx); 707 708 /* 709 * Manually check the DAT0 line for R1B response types that the 710 * controller fails to handle properly. The controller asserts the done 711 * interrupt while the card is still asserting busy with the DAT0 line. 712 * 713 * We check DAT0 immediately because most of the time, especially on a 714 * read, the card will actually be done by time we get here. If it's 715 * not, then the wait_done routine will schedule a callout to re-check 716 * periodically until it is done. In that case we clear the interrupt 717 * out of the hardware now so that we can present it later when the DAT0 718 * line is released. 719 * 720 * If we need to wait for the DAT0 line to be released, we set up a 721 * timeout point 250ms in the future. This number comes from the SD 722 * spec, which allows a command to take that long. In the real world, 723 * cards tend to take 10-20ms for a long-running command such as a write 724 * or erase that spans two pages. 725 */ 726 switch (sc->r1bfix_type) { 727 case R1BFIX_NODATA: 728 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE; 729 break; 730 case R1BFIX_AC12: 731 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END; 732 break; 733 default: 734 intmask = 0; 735 break; 736 } 737 if (intmask) { 738 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 739 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) { 740 WR4(sc, SDHCI_INT_STATUS, intmask); 741 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, 742 BUS_SPACE_BARRIER_WRITE); 743 } 744 } 745 746 mtx_unlock(&sc->slot.mtx); 747 sdhci_generic_intr(&sc->slot); 748 } 749 750 static int 751 fsl_sdhci_get_ro(device_t bus, device_t child) 752 { 753 struct fsl_sdhci_softc *sc = device_get_softc(bus); 754 755 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 756 } 757 758 static bool 759 fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 760 { 761 struct fsl_sdhci_softc *sc = device_get_softc(dev); 762 763 return (sdhci_fdt_gpio_get_present(sc->gpio)); 764 } 765 766 #ifdef __powerpc__ 767 static uint32_t 768 fsl_sdhci_get_platform_clock(device_t dev) 769 { 770 device_t parent; 771 phandle_t node; 772 uint32_t clock; 773 774 node = ofw_bus_get_node(dev); 775 776 /* Get sdhci node properties */ 777 if((OF_getprop(node, "clock-frequency", (void *)&clock, 778 sizeof(clock)) <= 0) || (clock == 0)) { 779 780 /* 781 * Trying to get clock from parent device (soc) if correct 782 * clock cannot be acquired from sdhci node. 783 */ 784 parent = device_get_parent(dev); 785 node = ofw_bus_get_node(parent); 786 787 /* Get soc properties */ 788 if ((OF_getprop(node, "bus-frequency", (void *)&clock, 789 sizeof(clock)) <= 0) || (clock == 0)) { 790 device_printf(dev,"Cannot acquire correct sdhci " 791 "frequency from DTS.\n"); 792 793 return (0); 794 } 795 /* eSDHC clock is 1/2 platform clock. */ 796 clock /= 2; 797 } 798 799 if (bootverbose) 800 device_printf(dev, "Acquired clock: %d from DTS\n", clock); 801 802 return (clock); 803 } 804 #endif 805 806 807 static int 808 fsl_sdhci_detach(device_t dev) 809 { 810 811 /* sdhci_fdt_gpio_teardown(sc->gpio); */ 812 return (EBUSY); 813 } 814 815 static int 816 fsl_sdhci_attach(device_t dev) 817 { 818 struct fsl_sdhci_softc *sc = device_get_softc(dev); 819 int rid, err; 820 #ifdef __powerpc__ 821 phandle_t node; 822 uint32_t protctl; 823 #endif 824 825 sc->dev = dev; 826 827 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 828 if (sc->hwtype == HWTYPE_NONE) 829 panic("Impossible: not compatible in fsl_sdhci_attach()"); 830 831 rid = 0; 832 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 833 RF_ACTIVE); 834 if (!sc->mem_res) { 835 device_printf(dev, "cannot allocate memory window\n"); 836 err = ENXIO; 837 goto fail; 838 } 839 840 rid = 0; 841 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 842 RF_ACTIVE); 843 if (!sc->irq_res) { 844 device_printf(dev, "cannot allocate interrupt\n"); 845 err = ENXIO; 846 goto fail; 847 } 848 849 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 850 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { 851 device_printf(dev, "cannot setup interrupt handler\n"); 852 err = ENXIO; 853 goto fail; 854 } 855 856 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 857 858 /* 859 * DMA is not really broken, I just haven't implemented it yet. 860 */ 861 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 862 863 /* 864 * Set the buffer watermark level to 128 words (512 bytes) for both read 865 * and write. The hardware has a restriction that when the read or 866 * write ready status is asserted, that means you can read exactly the 867 * number of words set in the watermark register before you have to 868 * re-check the status and potentially wait for more data. The main 869 * sdhci driver provides no hook for doing status checking on less than 870 * a full block boundary, so we set the watermark level to be a full 871 * block. Reads and writes where the block size is less than the 872 * watermark size will work correctly too, no need to change the 873 * watermark for different size blocks. However, 128 is the maximum 874 * allowed for the watermark, so PIO is limitted to 512 byte blocks 875 * (which works fine for SD cards, may be a problem for SDIO some day). 876 * 877 * XXX need named constants for this stuff. 878 */ 879 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */ 880 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) 881 WR4(sc, SDHC_WTMK_LVL, 0x10801080); 882 else 883 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 884 885 /* 886 * We read in native byte order in the main driver, but the register 887 * defaults to little endian. 888 */ 889 #ifdef __powerpc__ 890 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); 891 #else 892 sc->baseclk_hz = imx_ccm_sdhci_hz(); 893 #endif 894 sc->slot.max_clk = sc->baseclk_hz; 895 896 /* 897 * Set up any gpio pin handling described in the FDT data. This cannot 898 * fail; see comments in sdhci_fdt_gpio.h for details. 899 */ 900 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 901 902 #ifdef __powerpc__ 903 node = ofw_bus_get_node(dev); 904 /* Default to big-endian on powerpc */ 905 protctl = RD4(sc, SDHC_PROT_CTRL); 906 protctl &= ~SDHC_PROT_EMODE_MASK; 907 if (OF_hasprop(node, "little-endian")) 908 protctl |= SDHC_PROT_EMODE_LITTLE; 909 else 910 protctl |= SDHC_PROT_EMODE_BIG; 911 WR4(sc, SDHC_PROT_CTRL, protctl); 912 #endif 913 914 callout_init(&sc->r1bfix_callout, 1); 915 sdhci_init_slot(dev, &sc->slot, 0); 916 917 bus_generic_probe(dev); 918 bus_generic_attach(dev); 919 920 sdhci_start_slot(&sc->slot); 921 922 return (0); 923 924 fail: 925 if (sc->intr_cookie) 926 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 927 if (sc->irq_res) 928 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 929 if (sc->mem_res) 930 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 931 932 return (err); 933 } 934 935 static int 936 fsl_sdhci_probe(device_t dev) 937 { 938 939 if (!ofw_bus_status_okay(dev)) 940 return (ENXIO); 941 942 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 943 case HWTYPE_ESDHC: 944 device_set_desc(dev, "Freescale eSDHC controller"); 945 return (BUS_PROBE_DEFAULT); 946 case HWTYPE_USDHC: 947 device_set_desc(dev, "Freescale uSDHC controller"); 948 return (BUS_PROBE_DEFAULT); 949 default: 950 break; 951 } 952 return (ENXIO); 953 } 954 955 static device_method_t fsl_sdhci_methods[] = { 956 /* Device interface */ 957 DEVMETHOD(device_probe, fsl_sdhci_probe), 958 DEVMETHOD(device_attach, fsl_sdhci_attach), 959 DEVMETHOD(device_detach, fsl_sdhci_detach), 960 961 /* Bus interface */ 962 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 963 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 964 DEVMETHOD(bus_print_child, bus_generic_print_child), 965 966 /* MMC bridge interface */ 967 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 968 DEVMETHOD(mmcbr_request, sdhci_generic_request), 969 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro), 970 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 971 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 972 973 /* SDHCI accessors */ 974 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1), 975 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2), 976 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4), 977 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4), 978 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1), 979 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2), 980 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4), 981 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4), 982 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present), 983 984 { 0, 0 } 985 }; 986 987 static devclass_t fsl_sdhci_devclass; 988 989 static driver_t fsl_sdhci_driver = { 990 "sdhci_fsl", 991 fsl_sdhci_methods, 992 sizeof(struct fsl_sdhci_softc), 993 }; 994 995 DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass, 0, 0); 996 MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1); 997 DRIVER_MODULE(mmc, sdhci_fsl, mmc_driver, mmc_devclass, NULL, NULL); 998 MODULE_DEPEND(sdhci_fsl, mmc, 1, 1, 1); 999