1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families. 32 * 33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/bus.h> 40 #include <sys/callout.h> 41 #include <sys/kernel.h> 42 #include <sys/libkern.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/resource.h> 48 #include <sys/rman.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 #include <sys/time.h> 52 53 #include <machine/bus.h> 54 #include <machine/resource.h> 55 #ifdef __arm__ 56 #include <machine/intr.h> 57 58 #include <arm/freescale/imx/imx_ccmvar.h> 59 #endif 60 61 #ifdef __powerpc__ 62 #include <powerpc/mpc85xx/mpc85xx.h> 63 #endif 64 65 #include <dev/gpio/gpiobusvar.h> 66 67 #include <dev/ofw/ofw_bus.h> 68 #include <dev/ofw/ofw_bus_subr.h> 69 70 #include <dev/mmc/bridge.h> 71 72 #include <dev/sdhci/sdhci.h> 73 #include <dev/sdhci/sdhci_fdt_gpio.h> 74 75 #include "mmcbr_if.h" 76 #include "sdhci_if.h" 77 78 struct fsl_sdhci_softc { 79 device_t dev; 80 struct resource * mem_res; 81 struct resource * irq_res; 82 void * intr_cookie; 83 struct sdhci_slot slot; 84 struct callout r1bfix_callout; 85 sbintime_t r1bfix_timeout_at; 86 struct sdhci_fdt_gpio * gpio; 87 uint32_t baseclk_hz; 88 uint32_t cmd_and_mode; 89 uint32_t r1bfix_intmask; 90 uint16_t sdclockreg_freq_bits; 91 uint8_t r1bfix_type; 92 uint8_t hwtype; 93 }; 94 95 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ 96 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ 97 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ 98 99 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ 100 #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */ 101 #define HWTYPE_USDHC 2 /* fsl6. */ 102 103 /* 104 * Freescale-specific registers, or in some cases the layout of bits within the 105 * sdhci-defined register is different on Freescale. These names all begin with 106 * SDHC_ (not SDHCI_). 107 */ 108 109 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ 110 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ 111 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ 112 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8) 113 #define SDHC_VEND_IPGEN (1 << 11) 114 #define SDHC_VEND_HCKEN (1 << 12) 115 #define SDHC_VEND_PEREN (1 << 13) 116 117 #define SDHC_PRES_STATE 0x24 118 #define SDHC_PRES_CIHB (1 << 0) 119 #define SDHC_PRES_CDIHB (1 << 1) 120 #define SDHC_PRES_DLA (1 << 2) 121 #define SDHC_PRES_SDSTB (1 << 3) 122 #define SDHC_PRES_IPGOFF (1 << 4) 123 #define SDHC_PRES_HCKOFF (1 << 5) 124 #define SDHC_PRES_PEROFF (1 << 6) 125 #define SDHC_PRES_SDOFF (1 << 7) 126 #define SDHC_PRES_WTA (1 << 8) 127 #define SDHC_PRES_RTA (1 << 9) 128 #define SDHC_PRES_BWEN (1 << 10) 129 #define SDHC_PRES_BREN (1 << 11) 130 #define SDHC_PRES_RTR (1 << 12) 131 #define SDHC_PRES_CINST (1 << 16) 132 #define SDHC_PRES_CDPL (1 << 18) 133 #define SDHC_PRES_WPSPL (1 << 19) 134 #define SDHC_PRES_CLSL (1 << 23) 135 #define SDHC_PRES_DLSL_SHIFT 24 136 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) 137 138 #define SDHC_PROT_CTRL 0x28 139 #define SDHC_PROT_LED (1 << 0) 140 #define SDHC_PROT_WIDTH_1BIT (0 << 1) 141 #define SDHC_PROT_WIDTH_4BIT (1 << 1) 142 #define SDHC_PROT_WIDTH_8BIT (2 << 1) 143 #define SDHC_PROT_WIDTH_MASK (3 << 1) 144 #define SDHC_PROT_D3CD (1 << 3) 145 #define SDHC_PROT_EMODE_BIG (0 << 4) 146 #define SDHC_PROT_EMODE_HALF (1 << 4) 147 #define SDHC_PROT_EMODE_LITTLE (2 << 4) 148 #define SDHC_PROT_EMODE_MASK (3 << 4) 149 #define SDHC_PROT_SDMA (0 << 8) 150 #define SDHC_PROT_ADMA1 (1 << 8) 151 #define SDHC_PROT_ADMA2 (2 << 8) 152 #define SDHC_PROT_ADMA264 (3 << 8) 153 #define SDHC_PROT_DMA_MASK (3 << 8) 154 #define SDHC_PROT_CDTL (1 << 6) 155 #define SDHC_PROT_CDSS (1 << 7) 156 157 #define SDHC_SYS_CTRL 0x2c 158 159 /* 160 * The clock enable bits exist in different registers for ESDHC vs USDHC, but 161 * they are the same bits in both cases. The divisor values go into the 162 * standard sdhci clock register, but in different bit positions and meanings 163 than the sdhci spec values. 164 */ 165 #define SDHC_CLK_IPGEN (1 << 0) 166 #define SDHC_CLK_HCKEN (1 << 1) 167 #define SDHC_CLK_PEREN (1 << 2) 168 #define SDHC_CLK_SDCLKEN (1 << 3) 169 #define SDHC_CLK_ENABLE_MASK 0x0000000f 170 #define SDHC_CLK_DIVISOR_MASK 0x000000f0 171 #define SDHC_CLK_DIVISOR_SHIFT 4 172 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00 173 #define SDHC_CLK_PRESCALE_SHIFT 8 174 175 static struct ofw_compat_data compat_data[] = { 176 {"fsl,imx6q-usdhc", HWTYPE_USDHC}, 177 {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, 178 {"fsl,imx53-esdhc", HWTYPE_ESDHC}, 179 {"fsl,imx51-esdhc", HWTYPE_ESDHC}, 180 {"fsl,esdhc", HWTYPE_ESDHC}, 181 {NULL, HWTYPE_NONE}, 182 }; 183 184 static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc); 185 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val); 186 static void fsl_sdhci_r1bfix_func(void *arg); 187 188 static inline uint32_t 189 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) 190 { 191 192 return (bus_read_4(sc->mem_res, off)); 193 } 194 195 static inline void 196 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) 197 { 198 199 bus_write_4(sc->mem_res, off, val); 200 } 201 202 static uint8_t 203 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 204 { 205 struct fsl_sdhci_softc *sc = device_get_softc(dev); 206 uint32_t val32, wrk32; 207 208 /* 209 * Most of the things in the standard host control register are in the 210 * hardware's wider protocol control register, but some of the bits are 211 * moved around. 212 */ 213 if (off == SDHCI_HOST_CONTROL) { 214 wrk32 = RD4(sc, SDHC_PROT_CTRL); 215 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 216 SDHCI_CTRL_FORCE_CARD); 217 switch (wrk32 & SDHC_PROT_WIDTH_MASK) { 218 case SDHC_PROT_WIDTH_1BIT: 219 /* Value is already 0. */ 220 break; 221 case SDHC_PROT_WIDTH_4BIT: 222 val32 |= SDHCI_CTRL_4BITBUS; 223 break; 224 case SDHC_PROT_WIDTH_8BIT: 225 val32 |= SDHCI_CTRL_8BITBUS; 226 break; 227 } 228 switch (wrk32 & SDHC_PROT_DMA_MASK) { 229 case SDHC_PROT_SDMA: 230 /* Value is already 0. */ 231 break; 232 case SDHC_PROT_ADMA1: 233 /* This value is deprecated, should never appear. */ 234 break; 235 case SDHC_PROT_ADMA2: 236 val32 |= SDHCI_CTRL_ADMA2; 237 break; 238 case SDHC_PROT_ADMA264: 239 val32 |= SDHCI_CTRL_ADMA264; 240 break; 241 } 242 return val32; 243 } 244 245 /* 246 * XXX can't find the bus power on/off knob. For now we have to say the 247 * power is always on and always set to the same voltage. 248 */ 249 if (off == SDHCI_POWER_CONTROL) { 250 return (SDHCI_POWER_ON | SDHCI_POWER_300); 251 } 252 253 254 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 255 } 256 257 static uint16_t 258 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 259 { 260 struct fsl_sdhci_softc *sc = device_get_softc(dev); 261 uint32_t val32; 262 263 if (sc->hwtype == HWTYPE_USDHC) { 264 /* 265 * The USDHC hardware has nothing in the version register, but 266 * it's v3 compatible with all our translation code. 267 */ 268 if (off == SDHCI_HOST_VERSION) { 269 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); 270 } 271 /* 272 * The USDHC hardware moved the transfer mode bits to the mixed 273 * control register, fetch them from there. 274 */ 275 if (off == SDHCI_TRANSFER_MODE) 276 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); 277 278 } else if (sc->hwtype == HWTYPE_ESDHC) { 279 280 /* 281 * The ESDHC hardware has the typical 32-bit combined "command 282 * and mode" register that we have to cache so that command 283 * isn't written until after mode. On a read, just retrieve the 284 * cached values last written. 285 */ 286 if (off == SDHCI_TRANSFER_MODE) { 287 return (sc->cmd_and_mode & 0x0000ffff); 288 } else if (off == SDHCI_COMMAND_FLAGS) { 289 return (sc->cmd_and_mode >> 16); 290 } 291 } 292 293 /* 294 * This hardware only manages one slot. Synthesize a slot interrupt 295 * status register... if there are any enabled interrupts active they 296 * must be coming from our one and only slot. 297 */ 298 if (off == SDHCI_SLOT_INT_STATUS) { 299 val32 = RD4(sc, SDHCI_INT_STATUS); 300 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 301 return (val32 ? 1 : 0); 302 } 303 304 /* 305 * Clock bits are scattered into various registers which differ by 306 * hardware type, complex enough to have their own function. 307 */ 308 if (off == SDHCI_CLOCK_CONTROL) { 309 return (fsl_sdhc_get_clock(sc)); 310 } 311 312 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 313 } 314 315 static uint32_t 316 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 317 { 318 struct fsl_sdhci_softc *sc = device_get_softc(dev); 319 uint32_t val32, wrk32; 320 321 val32 = RD4(sc, off); 322 323 /* 324 * The hardware leaves the base clock frequency out of the capabilities 325 * register, but we filled it in by setting slot->max_clk at attach time 326 * rather than here, because we can't represent frequencies above 63MHz 327 * in an sdhci 2.0 capabliities register. The timeout clock is the same 328 * as the active output sdclock; we indicate that with a quirk setting 329 * so don't populate the timeout frequency bits. 330 * 331 * XXX Turn off (for now) features the hardware can do but this driver 332 * doesn't yet handle (1.8v, suspend/resume, etc). 333 */ 334 if (off == SDHCI_CAPABILITIES) { 335 val32 &= ~SDHCI_CAN_VDD_180; 336 val32 &= ~SDHCI_CAN_DO_SUSPEND; 337 val32 |= SDHCI_CAN_DO_8BITBUS; 338 return (val32); 339 } 340 341 /* 342 * The hardware moves bits around in the present state register to make 343 * room for all 8 data line state bits. To translate, mask out all the 344 * bits which are not in the same position in both registers (this also 345 * masks out some Freescale-specific bits in locations defined as 346 * reserved by sdhci), then shift the data line and retune request bits 347 * down to their standard locations. 348 */ 349 if (off == SDHCI_PRESENT_STATE) { 350 wrk32 = val32; 351 val32 &= 0x000F0F07; 352 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 353 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; 354 return (val32); 355 } 356 357 /* 358 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a 359 * command with an R1B response, mix it into the hardware status. 360 */ 361 if (off == SDHCI_INT_STATUS) { 362 return (val32 | sc->r1bfix_intmask); 363 } 364 365 return val32; 366 } 367 368 static void 369 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 370 uint32_t *data, bus_size_t count) 371 { 372 struct fsl_sdhci_softc *sc = device_get_softc(dev); 373 374 bus_read_multi_4(sc->mem_res, off, data, count); 375 } 376 377 static void 378 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 379 { 380 struct fsl_sdhci_softc *sc = device_get_softc(dev); 381 uint32_t val32; 382 383 /* 384 * Most of the things in the standard host control register are in the 385 * hardware's wider protocol control register, but some of the bits are 386 * moved around. 387 */ 388 if (off == SDHCI_HOST_CONTROL) { 389 val32 = RD4(sc, SDHC_PROT_CTRL); 390 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | 391 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); 392 val32 |= (val & SDHCI_CTRL_LED); 393 if (val & SDHCI_CTRL_8BITBUS) 394 val32 |= SDHC_PROT_WIDTH_8BIT; 395 else 396 val32 |= (val & SDHCI_CTRL_4BITBUS); 397 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; 398 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); 399 WR4(sc, SDHC_PROT_CTRL, val32); 400 return; 401 } 402 403 /* XXX I can't find the bus power on/off knob; do nothing. */ 404 if (off == SDHCI_POWER_CONTROL) { 405 return; 406 } 407 #ifdef __powerpc__ 408 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */ 409 if (off == SDHCI_SOFTWARE_RESET) 410 return; 411 #endif 412 413 val32 = RD4(sc, off & ~3); 414 val32 &= ~(0xff << (off & 3) * 8); 415 val32 |= (val << (off & 3) * 8); 416 417 WR4(sc, off & ~3, val32); 418 } 419 420 static void 421 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 422 { 423 struct fsl_sdhci_softc *sc = device_get_softc(dev); 424 uint32_t val32; 425 426 /* 427 * The clock control stuff is complex enough to have its own function 428 * that can handle the ESDHC versus USDHC differences. 429 */ 430 if (off == SDHCI_CLOCK_CONTROL) { 431 fsl_sdhc_set_clock(sc, val); 432 return; 433 } 434 435 /* 436 * Figure out whether we need to check the DAT0 line for busy status at 437 * interrupt time. The controller should be doing this, but for some 438 * reason it doesn't. There are two cases: 439 * - R1B response with no data transfer should generate a DATA_END (aka 440 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if 441 * there's no data transfer there's no DATA_END interrupt. This is 442 * documented; they seem to think it's a feature. 443 * - R1B response after Auto-CMD12 appears to not work, even though 444 * there's a control bit for it (bit 3) in the vendor register. 445 * When we're starting a command that needs a manual DAT0 line check at 446 * interrupt time, we leave ourselves a note in r1bfix_type so that we 447 * can do the extra work in fsl_sdhci_intr(). 448 */ 449 if (off == SDHCI_COMMAND_FLAGS) { 450 if (val & SDHCI_CMD_DATA) { 451 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; 452 val32 = RD4(sc, USDHC_MIX_CONTROL); 453 if ((val32 & MBAUTOCMD) == MBAUTOCMD) 454 sc->r1bfix_type = R1BFIX_AC12; 455 } else { 456 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { 457 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 458 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 459 sc->r1bfix_type = R1BFIX_NODATA; 460 } 461 } 462 } 463 464 /* 465 * The USDHC hardware moved the transfer mode bits to mixed control; we 466 * just write them there and we're done. The ESDHC hardware has the 467 * typical combined cmd-and-mode register that allows only 32-bit 468 * access, so when writing the mode bits just save them, then later when 469 * writing the command bits, add in the saved mode bits. 470 */ 471 if (sc->hwtype == HWTYPE_USDHC) { 472 if (off == SDHCI_TRANSFER_MODE) { 473 val32 = RD4(sc, USDHC_MIX_CONTROL); 474 val32 &= ~0x3f; 475 val32 |= val & 0x37; 476 // XXX acmd23 not supported here (or by sdhci driver) 477 WR4(sc, USDHC_MIX_CONTROL, val32); 478 return; 479 } 480 } else if (sc->hwtype == HWTYPE_ESDHC) { 481 if (off == SDHCI_TRANSFER_MODE) { 482 sc->cmd_and_mode = 483 (sc->cmd_and_mode & 0xffff0000) | val; 484 return; 485 } else if (off == SDHCI_COMMAND_FLAGS) { 486 sc->cmd_and_mode = 487 (sc->cmd_and_mode & 0xffff) | (val << 16); 488 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 489 return; 490 } 491 } 492 493 val32 = RD4(sc, off & ~3); 494 val32 &= ~(0xffff << (off & 3) * 8); 495 val32 |= ((val & 0xffff) << (off & 3) * 8); 496 WR4(sc, off & ~3, val32); 497 } 498 499 static void 500 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 501 { 502 struct fsl_sdhci_softc *sc = device_get_softc(dev); 503 504 /* Clear synthesized interrupts, then pass the value to the hardware. */ 505 if (off == SDHCI_INT_STATUS) { 506 sc->r1bfix_intmask &= ~val; 507 } 508 509 WR4(sc, off, val); 510 } 511 512 static void 513 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 514 uint32_t *data, bus_size_t count) 515 { 516 struct fsl_sdhci_softc *sc = device_get_softc(dev); 517 518 bus_write_multi_4(sc->mem_res, off, data, count); 519 } 520 521 static uint16_t 522 fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc) 523 { 524 uint16_t val; 525 526 /* 527 * Whenever the sdhci driver writes the clock register we save a 528 * snapshot of just the frequency bits, so that we can play them back 529 * here on a register read without recalculating the frequency from the 530 * prescalar and divisor bits in the real register. We'll start with 531 * those bits, and mix in the clock status and enable bits that come 532 * from different places depending on which hardware we've got. 533 */ 534 val = sc->sdclockreg_freq_bits; 535 536 /* 537 * The internal clock is always enabled (actually, the hardware manages 538 * it). Whether the internal clock is stable yet after a frequency 539 * change comes from the present-state register on both hardware types. 540 */ 541 val |= SDHCI_CLOCK_INT_EN; 542 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) 543 val |= SDHCI_CLOCK_INT_STABLE; 544 545 /* 546 * On i.MX ESDHC hardware the card bus clock enable is in the usual 547 * sdhci register but it's a different bit, so transcribe it (note the 548 * difference between standard SDHCI_ and Freescale SDHC_ prefixes 549 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but 550 * no force-off for the card bus clock (the hardware runs the clock when 551 * transfers are active no matter what), so we always say the clock is 552 * on. 553 * XXX Maybe we should say it's in whatever state the sdhci driver last 554 * set it to. 555 */ 556 if (sc->hwtype == HWTYPE_ESDHC) { 557 #ifdef __arm__ 558 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) 559 #endif 560 val |= SDHCI_CLOCK_CARD_EN; 561 } else { 562 val |= SDHCI_CLOCK_CARD_EN; 563 } 564 565 return (val); 566 } 567 568 static void 569 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val) 570 { 571 uint32_t divisor, freq, prescale, val32; 572 573 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 574 575 /* 576 * Save the frequency-setting bits in SDHCI format so that we can play 577 * them back in get_clock without complex decoding of hardware regs, 578 * then deal with the freqency part of the value based on hardware type. 579 */ 580 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; 581 if (sc->hwtype == HWTYPE_ESDHC) { 582 /* 583 * The i.MX5 ESDHC hardware requires the driver to manually 584 * start and stop the sd bus clock. If the enable bit is not 585 * set, turn off the clock in hardware and we're done, otherwise 586 * decode the requested frequency. ESDHC hardware is sdhci 2.0; 587 * the sdhci driver will use the original 8-bit divisor field 588 * and the "base / 2^N" divisor scheme. 589 */ 590 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 591 #ifdef __arm__ 592 /* On QorIQ, this is a reserved bit. */ 593 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); 594 #endif 595 return; 596 597 } 598 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 599 freq = sc->baseclk_hz >> ffs(divisor); 600 } else { 601 /* 602 * The USDHC hardware provides only "force always on" control 603 * over the sd bus clock, but no way to turn it off. (If a cmd 604 * or data transfer is in progress the clock is on, otherwise it 605 * is off.) If the clock is being disabled, we can just return 606 * now, otherwise we decode the requested frequency. USDHC 607 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit 608 * divisor using the "base / 2*N" divisor scheme. 609 */ 610 if ((val & SDHCI_CLOCK_CARD_EN) == 0) 611 return; 612 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 613 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 614 SDHCI_DIVIDER_MASK_LEN; 615 if (divisor == 0) 616 freq = sc->baseclk_hz; 617 else 618 freq = sc->baseclk_hz / (2 * divisor); 619 } 620 621 /* 622 * Get a prescaler and final divisor to achieve the desired frequency. 623 */ 624 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) 625 prescale <<= 1; 626 627 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) 628 ++divisor; 629 630 #ifdef DEBUG 631 device_printf(sc->dev, 632 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", 633 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, 634 prescale, divisor); 635 #endif 636 637 /* 638 * Adjust to zero-based values, and store them to the hardware. 639 */ 640 prescale >>= 1; 641 divisor -= 1; 642 643 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); 644 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; 645 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; 646 val32 |= SDHC_CLK_IPGEN; 647 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 648 } 649 650 static boolean_t 651 fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc) 652 { 653 uint32_t inhibit; 654 655 mtx_assert(&sc->slot.mtx, MA_OWNED); 656 657 /* 658 * Check the DAT0 line status using both the DLA (data line active) and 659 * CDIHB (data inhibit) bits in the present state register. In theory 660 * just DLA should do the trick, but in practice it takes both. If the 661 * DAT0 line is still being held and we're not yet beyond the timeout 662 * point, just schedule another callout to check again later. 663 */ 664 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); 665 666 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { 667 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, 668 fsl_sdhci_r1bfix_func, sc, 0); 669 return (false); 670 } 671 672 /* 673 * If we reach this point with the inhibit bits still set, we've got a 674 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 675 * line has been released, and we synthesize a DATA_END, and if the type 676 * of fix needed was on a command-without-data we also now add in the 677 * original INT_RESPONSE that we suppressed earlier. 678 */ 679 if (inhibit) 680 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; 681 else { 682 sc->r1bfix_intmask |= SDHCI_INT_DATA_END; 683 if (sc->r1bfix_type == R1BFIX_NODATA) 684 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; 685 } 686 687 sc->r1bfix_type = R1BFIX_NONE; 688 return (true); 689 } 690 691 static void 692 fsl_sdhci_r1bfix_func(void * arg) 693 { 694 struct fsl_sdhci_softc *sc = arg; 695 boolean_t r1bwait_done; 696 697 mtx_lock(&sc->slot.mtx); 698 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc); 699 mtx_unlock(&sc->slot.mtx); 700 if (r1bwait_done) 701 sdhci_generic_intr(&sc->slot); 702 } 703 704 static void 705 fsl_sdhci_intr(void *arg) 706 { 707 struct fsl_sdhci_softc *sc = arg; 708 uint32_t intmask; 709 710 mtx_lock(&sc->slot.mtx); 711 712 /* 713 * Manually check the DAT0 line for R1B response types that the 714 * controller fails to handle properly. The controller asserts the done 715 * interrupt while the card is still asserting busy with the DAT0 line. 716 * 717 * We check DAT0 immediately because most of the time, especially on a 718 * read, the card will actually be done by time we get here. If it's 719 * not, then the wait_done routine will schedule a callout to re-check 720 * periodically until it is done. In that case we clear the interrupt 721 * out of the hardware now so that we can present it later when the DAT0 722 * line is released. 723 * 724 * If we need to wait for the DAT0 line to be released, we set up a 725 * timeout point 250ms in the future. This number comes from the SD 726 * spec, which allows a command to take that long. In the real world, 727 * cards tend to take 10-20ms for a long-running command such as a write 728 * or erase that spans two pages. 729 */ 730 switch (sc->r1bfix_type) { 731 case R1BFIX_NODATA: 732 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE; 733 break; 734 case R1BFIX_AC12: 735 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END; 736 break; 737 default: 738 intmask = 0; 739 break; 740 } 741 if (intmask) { 742 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; 743 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) { 744 WR4(sc, SDHCI_INT_STATUS, intmask); 745 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, 746 BUS_SPACE_BARRIER_WRITE); 747 } 748 } 749 750 mtx_unlock(&sc->slot.mtx); 751 sdhci_generic_intr(&sc->slot); 752 } 753 754 static int 755 fsl_sdhci_get_ro(device_t bus, device_t child) 756 { 757 struct fsl_sdhci_softc *sc = device_get_softc(bus); 758 759 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 760 } 761 762 static bool 763 fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 764 { 765 struct fsl_sdhci_softc *sc = device_get_softc(dev); 766 767 return (sdhci_fdt_gpio_get_present(sc->gpio)); 768 } 769 770 #ifdef __powerpc__ 771 static uint32_t 772 fsl_sdhci_get_platform_clock(device_t dev) 773 { 774 phandle_t node; 775 uint32_t clock; 776 777 node = ofw_bus_get_node(dev); 778 779 /* Get sdhci node properties */ 780 if((OF_getprop(node, "clock-frequency", (void *)&clock, 781 sizeof(clock)) <= 0) || (clock == 0)) { 782 783 clock = mpc85xx_get_system_clock(); 784 785 if (clock == 0) { 786 device_printf(dev,"Cannot acquire correct sdhci " 787 "frequency from DTS.\n"); 788 789 return (0); 790 } 791 } 792 793 if (bootverbose) 794 device_printf(dev, "Acquired clock: %d from DTS\n", clock); 795 796 return (clock); 797 } 798 #endif 799 800 801 static int 802 fsl_sdhci_detach(device_t dev) 803 { 804 805 /* sdhci_fdt_gpio_teardown(sc->gpio); */ 806 return (EBUSY); 807 } 808 809 static int 810 fsl_sdhci_attach(device_t dev) 811 { 812 struct fsl_sdhci_softc *sc = device_get_softc(dev); 813 int rid, err; 814 #ifdef __powerpc__ 815 phandle_t node; 816 uint32_t protctl; 817 #endif 818 819 sc->dev = dev; 820 821 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 822 if (sc->hwtype == HWTYPE_NONE) 823 panic("Impossible: not compatible in fsl_sdhci_attach()"); 824 825 rid = 0; 826 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 827 RF_ACTIVE); 828 if (!sc->mem_res) { 829 device_printf(dev, "cannot allocate memory window\n"); 830 err = ENXIO; 831 goto fail; 832 } 833 834 rid = 0; 835 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 836 RF_ACTIVE); 837 if (!sc->irq_res) { 838 device_printf(dev, "cannot allocate interrupt\n"); 839 err = ENXIO; 840 goto fail; 841 } 842 843 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 844 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { 845 device_printf(dev, "cannot setup interrupt handler\n"); 846 err = ENXIO; 847 goto fail; 848 } 849 850 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 851 852 /* 853 * DMA is not really broken, I just haven't implemented it yet. 854 */ 855 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 856 857 /* 858 * Set the buffer watermark level to 128 words (512 bytes) for both read 859 * and write. The hardware has a restriction that when the read or 860 * write ready status is asserted, that means you can read exactly the 861 * number of words set in the watermark register before you have to 862 * re-check the status and potentially wait for more data. The main 863 * sdhci driver provides no hook for doing status checking on less than 864 * a full block boundary, so we set the watermark level to be a full 865 * block. Reads and writes where the block size is less than the 866 * watermark size will work correctly too, no need to change the 867 * watermark for different size blocks. However, 128 is the maximum 868 * allowed for the watermark, so PIO is limitted to 512 byte blocks 869 * (which works fine for SD cards, may be a problem for SDIO some day). 870 * 871 * XXX need named constants for this stuff. 872 */ 873 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */ 874 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) 875 WR4(sc, SDHC_WTMK_LVL, 0x10801080); 876 else 877 WR4(sc, SDHC_WTMK_LVL, 0x08800880); 878 879 /* 880 * We read in native byte order in the main driver, but the register 881 * defaults to little endian. 882 */ 883 #ifdef __powerpc__ 884 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); 885 #else 886 sc->baseclk_hz = imx_ccm_sdhci_hz(); 887 #endif 888 sc->slot.max_clk = sc->baseclk_hz; 889 890 /* 891 * Set up any gpio pin handling described in the FDT data. This cannot 892 * fail; see comments in sdhci_fdt_gpio.h for details. 893 */ 894 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 895 896 #ifdef __powerpc__ 897 node = ofw_bus_get_node(dev); 898 /* Default to big-endian on powerpc */ 899 protctl = RD4(sc, SDHC_PROT_CTRL); 900 protctl &= ~SDHC_PROT_EMODE_MASK; 901 if (OF_hasprop(node, "little-endian")) 902 protctl |= SDHC_PROT_EMODE_LITTLE; 903 else 904 protctl |= SDHC_PROT_EMODE_BIG; 905 WR4(sc, SDHC_PROT_CTRL, protctl); 906 #endif 907 908 callout_init(&sc->r1bfix_callout, 1); 909 sdhci_init_slot(dev, &sc->slot, 0); 910 911 bus_generic_probe(dev); 912 bus_generic_attach(dev); 913 914 sdhci_start_slot(&sc->slot); 915 916 return (0); 917 918 fail: 919 if (sc->intr_cookie) 920 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 921 if (sc->irq_res) 922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 923 if (sc->mem_res) 924 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 925 926 return (err); 927 } 928 929 static int 930 fsl_sdhci_probe(device_t dev) 931 { 932 933 if (!ofw_bus_status_okay(dev)) 934 return (ENXIO); 935 936 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 937 case HWTYPE_ESDHC: 938 device_set_desc(dev, "Freescale eSDHC controller"); 939 return (BUS_PROBE_DEFAULT); 940 case HWTYPE_USDHC: 941 device_set_desc(dev, "Freescale uSDHC controller"); 942 return (BUS_PROBE_DEFAULT); 943 default: 944 break; 945 } 946 return (ENXIO); 947 } 948 949 static device_method_t fsl_sdhci_methods[] = { 950 /* Device interface */ 951 DEVMETHOD(device_probe, fsl_sdhci_probe), 952 DEVMETHOD(device_attach, fsl_sdhci_attach), 953 DEVMETHOD(device_detach, fsl_sdhci_detach), 954 955 /* Bus interface */ 956 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 957 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 958 959 /* MMC bridge interface */ 960 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 961 DEVMETHOD(mmcbr_request, sdhci_generic_request), 962 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro), 963 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 964 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 965 966 /* SDHCI accessors */ 967 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1), 968 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2), 969 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4), 970 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4), 971 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1), 972 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2), 973 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4), 974 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4), 975 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present), 976 977 DEVMETHOD_END 978 }; 979 980 static devclass_t fsl_sdhci_devclass; 981 982 static driver_t fsl_sdhci_driver = { 983 "sdhci_fsl", 984 fsl_sdhci_methods, 985 sizeof(struct fsl_sdhci_softc), 986 }; 987 988 DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass, 989 NULL, NULL); 990 MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1); 991 MMC_DECLARE_BRIDGE(sdhci_fsl); 992