xref: /freebsd/sys/dev/scc/scc_bfe.h (revision 1669d8afc64812c8d2d1d147ae1fd42ff441e1b1)
1 /*-
2  * Copyright (c) 2004-2006 Marcel Moolenaar
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  */
28 
29 #ifndef _DEV_SCC_BFE_H_
30 #define _DEV_SCC_BFE_H_
31 
32 #include <sys/serial.h>
33 
34 /*
35  * Bus access structure. This structure holds the minimum information needed
36  * to access the SCC. The rclk field, although not important to actually
37  * access the SCC, is important for baudrate programming, delay loops and
38  * other timing related computations.
39  */
40 struct scc_bas {
41 	bus_space_tag_t	bst;
42 	bus_space_handle_t bsh;
43 	u_int		range;
44 	u_int		rclk;
45 	u_int		regshft;
46 };
47 
48 #define	scc_regofs(bas, reg)		((reg) << (bas)->regshft)
49 
50 #define	scc_getreg(bas, reg)		\
51 	bus_space_read_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg))
52 #define	scc_setreg(bas, reg, value)	\
53 	bus_space_write_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg), value)
54 
55 #define	scc_barrier(bas)		\
56 	bus_space_barrier((bas)->bst, (bas)->bsh, 0, (bas)->range,	\
57 	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
58 
59 /*
60  * SCC mode (child) and channel control structures.
61  */
62 
63 #define	SCC_NMODES	3
64 #define	SCC_ISRCCNT	5
65 
66 struct scc_chan;
67 
68 struct scc_mode {
69 	struct scc_chan	*m_chan;
70 	device_t	m_dev;
71 
72 	u_int		m_mode;
73 	int		m_attached:1;
74 	int		m_fastintr:1;
75 	int		m_hasintr:1;
76 	int		m_probed:1;
77 	int		m_sysdev:1;
78 
79 	driver_filter_t	*ih;
80 	serdev_intr_t	*ih_src[SCC_ISRCCNT];
81 	void		*ih_arg;
82 };
83 
84 struct scc_chan {
85 	struct resource ch_rres;
86 	struct resource_list ch_rlist;
87 
88 	struct resource *ch_ires;	/* Interrupt resource. */
89 	void		*ch_icookie;
90 	int		ch_irid;
91 
92 	struct scc_mode	ch_mode[SCC_NMODES];
93 
94 	u_int		ch_nr;
95 	int		ch_enabled:1;
96 	int		ch_sysdev:1;
97 
98 	uint32_t	ch_ipend;
99 	uint32_t	ch_hwsig;
100 };
101 
102 /*
103  * SCC class & instance (=softc)
104  */
105 struct scc_class {
106 	KOBJ_CLASS_FIELDS;
107 	u_int		cl_channels;	/* Number of independent channels. */
108 	u_int		cl_class;	/* SCC bus class ID. */
109 	u_int		cl_modes;	/* Supported modes (bitset). */
110 	int		cl_range;
111 };
112 
113 extern struct scc_class scc_sab82532_class;
114 extern struct scc_class scc_z8530_class;
115 
116 struct scc_softc {
117 	KOBJ_FIELDS;
118 	struct scc_class *sc_class;
119 	struct scc_bas	sc_bas;
120 	device_t	sc_dev;
121 
122 	struct mtx	sc_hwmtx;	/* Spinlock protecting hardware. */
123 
124 	struct resource	*sc_rres;	/* Register resource. */
125 	int		sc_rrid;
126 	int		sc_rtype;	/* SYS_RES_{IOPORT|MEMORY}. */
127 
128 	struct scc_chan	*sc_chan;
129 
130 	int		sc_fastintr:1;
131 	int		sc_leaving:1;
132 	int		sc_polled:1;
133 
134 	uint32_t        sc_hwsig;       /* Signal state. Used by HW driver. */
135 };
136 
137 extern devclass_t scc_devclass;
138 extern char scc_driver_name[];
139 
140 int scc_bfe_attach(device_t dev);
141 int scc_bfe_detach(device_t dev);
142 int scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid);
143 
144 struct resource *scc_bus_alloc_resource(device_t, device_t, int, int *,
145     u_long, u_long, u_long, u_int);
146 int scc_bus_get_resource(device_t, device_t, int, int, u_long *, u_long *);
147 int scc_bus_read_ivar(device_t, device_t, int, uintptr_t *);
148 int scc_bus_release_resource(device_t, device_t, int, int, struct resource *);
149 int scc_bus_setup_intr(device_t, device_t, struct resource *, int,
150     driver_filter_t *, void (*)(void *), void *, void **);
151 int scc_bus_teardown_intr(device_t, device_t, struct resource *, void *);
152 
153 #endif /* _DEV_SCC_BFE_H_ */
154