1 /*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 #ifndef _SAFE_SAFEVAR_H_ 30 #define _SAFE_SAFEVAR_H_ 31 32 /* Maximum queue length */ 33 #ifndef SAFE_MAX_NQUEUE 34 #define SAFE_MAX_NQUEUE 60 35 #endif 36 37 #define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ 38 #define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ 39 #define SAFE_MAX_DSIZE MCLBYTES /* Fixed scatter particle size */ 40 #define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ 41 #define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ 42 /* total src+dst particle descriptors */ 43 #define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) 44 #define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) 45 46 #define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ 47 48 #define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) 49 #define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) 50 #define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) 51 52 #define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ 53 #define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ 54 #define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ 55 56 #ifdef _KERNEL 57 /* 58 * State associated with the allocation of each chunk 59 * of memory setup for DMA. 60 */ 61 struct safe_dma_alloc { 62 u_int32_t dma_paddr; /* physical address */ 63 caddr_t dma_vaddr; /* virtual address */ 64 bus_dma_tag_t dma_tag; /* bus dma tag used */ 65 bus_dmamap_t dma_map; /* associated map */ 66 bus_dma_segment_t dma_seg; 67 bus_size_t dma_size; /* mapped memory size (bytes) */ 68 int dma_nseg; /* number of segments */ 69 }; 70 71 /* 72 * Cryptographic operand state. One of these exists for each 73 * source and destination operand passed in from the crypto 74 * subsystem. When possible source and destination operands 75 * refer to the same memory. More often they are distinct. 76 * We track the virtual address of each operand as well as 77 * where each is mapped for DMA. 78 */ 79 struct safe_operand { 80 union { 81 struct mbuf *m; 82 struct uio *io; 83 } u; 84 bus_dmamap_t map; 85 bus_size_t mapsize; 86 int nsegs; 87 bus_dma_segment_t segs[SAFE_MAX_PART]; 88 }; 89 90 /* 91 * Packet engine ring entry and cryptographic operation state. 92 * The packet engine requires a ring of descriptors that contain 93 * pointers to various cryptographic state. However the ring 94 * configuration register allows you to specify an arbitrary size 95 * for ring entries. We use this feature to collect most of the 96 * state for each cryptographic request into one spot. Other than 97 * ring entries only the ``particle descriptors'' (scatter/gather 98 * lists) and the actual operand data are kept separate. The 99 * particle descriptors must also be organized in rings. The 100 * operand data can be located aribtrarily (modulo alignment constraints). 101 * 102 * Note that the descriptor ring is mapped onto the PCI bus so 103 * the hardware can DMA data. This means the entire ring must be 104 * contiguous. 105 */ 106 struct safe_ringentry { 107 struct safe_desc re_desc; /* command descriptor */ 108 struct safe_sarec re_sa; /* SA record */ 109 struct safe_sastate re_sastate; /* SA state record */ 110 struct cryptop *re_crp; /* crypto operation */ 111 112 struct safe_operand re_src; /* source operand */ 113 struct safe_operand re_dst; /* destination operand */ 114 115 int re_sesn; /* crypto session ID */ 116 int re_flags; 117 #define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ 118 #define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ 119 }; 120 121 #define re_src_m re_src.u.m 122 #define re_src_io re_src.u.io 123 #define re_src_map re_src.map 124 #define re_src_nsegs re_src.nsegs 125 #define re_src_segs re_src.segs 126 #define re_src_mapsize re_src.mapsize 127 128 #define re_dst_m re_dst.u.m 129 #define re_dst_io re_dst.u.io 130 #define re_dst_map re_dst.map 131 #define re_dst_nsegs re_dst.nsegs 132 #define re_dst_segs re_dst.segs 133 #define re_dst_mapsize re_dst.mapsize 134 135 struct rndstate_test; 136 137 struct safe_session { 138 u_int32_t ses_used; 139 u_int32_t ses_klen; /* key length in bits */ 140 u_int32_t ses_key[8]; /* DES/3DES/AES key */ 141 u_int32_t ses_mlen; /* hmac length in bytes */ 142 u_int32_t ses_hminner[5]; /* hmac inner state */ 143 u_int32_t ses_hmouter[5]; /* hmac outer state */ 144 u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ 145 }; 146 147 struct safe_softc { 148 device_t sc_dev; /* device backpointer */ 149 struct resource *sc_irq; 150 void *sc_ih; /* interrupt handler cookie */ 151 bus_space_handle_t sc_sh; /* memory handle */ 152 bus_space_tag_t sc_st; /* memory tag */ 153 struct resource *sc_sr; /* memory resource */ 154 bus_dma_tag_t sc_srcdmat; /* source dma tag */ 155 bus_dma_tag_t sc_dstdmat; /* destination dma tag */ 156 u_int sc_chiprev; /* major/minor chip revision */ 157 int sc_flags; /* device specific flags */ 158 #define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ 159 #define SAFE_FLAGS_RNG 0x02 /* hardware rng */ 160 int sc_suspended; 161 int sc_needwakeup; /* notify crypto layer */ 162 int32_t sc_cid; /* crypto tag */ 163 struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ 164 struct safe_ringentry *sc_ring; /* PE ring */ 165 struct safe_ringentry *sc_ringtop; /* PE ring top */ 166 struct safe_ringentry *sc_front; /* next free entry */ 167 struct safe_ringentry *sc_back; /* next pending entry */ 168 int sc_nqchip; /* # passed to chip */ 169 struct mtx sc_ringmtx; /* PE ring lock */ 170 struct safe_pdesc *sc_spring; /* src particle ring */ 171 struct safe_pdesc *sc_springtop; /* src particle ring top */ 172 struct safe_pdesc *sc_spfree; /* next free src particle */ 173 struct safe_dma_alloc sc_spalloc; /* src particle ring state */ 174 struct safe_pdesc *sc_dpring; /* dest particle ring */ 175 struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ 176 struct safe_pdesc *sc_dpfree; /* next free dest particle */ 177 struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ 178 int sc_nsessions; /* # of sessions */ 179 struct safe_session *sc_sessions; /* sessions */ 180 181 struct callout sc_rngto; /* rng timeout */ 182 struct rndtest_state *sc_rndtest; /* RNG test state */ 183 void (*sc_harvest)(struct rndtest_state *, 184 void *, u_int); 185 }; 186 #endif /* _KERNEL */ 187 188 struct safe_stats { 189 u_int64_t st_ibytes; 190 u_int64_t st_obytes; 191 u_int32_t st_ipackets; 192 u_int32_t st_opackets; 193 u_int32_t st_invalid; /* invalid argument */ 194 u_int32_t st_badsession; /* invalid session id */ 195 u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ 196 u_int32_t st_nodesc; /* op submitted w/o descriptors */ 197 u_int32_t st_badalg; /* unsupported algorithm */ 198 u_int32_t st_ringfull; /* PE descriptor ring full */ 199 u_int32_t st_peoperr; /* PE marked error */ 200 u_int32_t st_dmaerr; /* PE DMA error */ 201 u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ 202 u_int32_t st_skipmismatch; /* enc part begins before auth part */ 203 u_int32_t st_lenmismatch; /* enc length different auth length */ 204 u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ 205 u_int32_t st_cofftoobig; /* crypto offset > 255 words */ 206 u_int32_t st_iovmisaligned; /* iov op not aligned */ 207 u_int32_t st_iovnotuniform; /* iov op not suitable */ 208 u_int32_t st_unaligned; /* unaligned src caused copy */ 209 u_int32_t st_notuniform; /* non-uniform src caused copy */ 210 u_int32_t st_nomap; /* bus_dmamap_create failed */ 211 u_int32_t st_noload; /* bus_dmamap_load_* failed */ 212 u_int32_t st_nombuf; /* MGET* failed */ 213 u_int32_t st_nomcl; /* MCLGET* failed */ 214 u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ 215 u_int32_t st_rng; /* RNG requests */ 216 u_int32_t st_rngalarm; /* RNG alarm requests */ 217 u_int32_t st_noicvcopy; /* ICV data copies suppressed */ 218 }; 219 #endif /* _SAFE_SAFEVAR_H_ */ 220