1 /*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 #ifndef _SAFE_SAFEREG_H_ 30 #define _SAFE_SAFEREG_H_ 31 32 /* 33 * Register definitions for SafeNet SafeXcel-1141 crypto device. 34 * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. 35 */ 36 37 #define BS_BAR 0x10 /* DMA base address register */ 38 #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ 39 #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ 40 41 #define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ 42 43 /* SafeNet */ 44 #define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ 45 46 #define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ 47 #define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ 48 #define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ 49 #define SAFE_PE_SA 0x000c /* Packet Engine SA */ 50 #define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ 51 #define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ 52 #define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ 53 #define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ 54 #define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ 55 #define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ 56 #define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ 57 #define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ 58 #define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ 59 #define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ 60 #define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ 61 #define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ 62 #define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ 63 #define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ 64 #define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ 65 #define SAFE_DEVID 0x0084 /* Device ID */ 66 #define SAFE_DEVINFO 0x0088 /* Device Info */ 67 #define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ 68 #define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ 69 #define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ 70 #define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ 71 #define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ 72 #define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ 73 #define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ 74 #define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ 75 #define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ 76 #define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ 77 #define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ 78 #define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ 79 #define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ 80 #define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ 81 #define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ 82 #define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ 83 #define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ 84 #define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ 85 #define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ 86 #define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ 87 #define SAFE_PK_FUNC 0x081c /* Public Key Function */ 88 #define SAFE_RNG_OUT 0x0100 /* RNG Output */ 89 #define SAFE_RNG_STAT 0x0104 /* RNG Status */ 90 #define SAFE_RNG_CTRL 0x0108 /* RNG Control */ 91 #define SAFE_RNG_A 0x010c /* RNG A */ 92 #define SAFE_RNG_B 0x0110 /* RNG B */ 93 #define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ 94 #define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ 95 #define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ 96 #define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ 97 #define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ 98 #define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ 99 #define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ 100 #define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ 101 #define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ 102 #define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ 103 104 #define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ 105 #define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ 106 #define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ 107 #define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ 108 #define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ 109 #define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ 110 #define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ 111 #define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ 112 #define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ 113 #define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ 114 #define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ 115 #define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ 116 #define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ 117 #define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ 118 #define SAFE_PE_CSR_XECODE_S 20 119 #define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ 120 #define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ 121 #define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ 122 #define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ 123 #define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ 124 #define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ 125 #define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ 126 #define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ 127 #define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ 128 #define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ 129 #define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ 130 #define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ 131 #define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ 132 #define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ 133 #define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ 134 135 /* 136 * Check the CSR to see if the PE has returned ownership to 137 * the host. Note that before processing a descriptor this 138 * must be done followed by a check of the SAFE_PE_LEN register 139 * status bits to avoid premature processing of a descriptor 140 * on its way back to the host. 141 */ 142 #define SAFE_PE_CSR_IS_DONE(_csr) \ 143 (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) 144 145 #define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ 146 #define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ 147 #define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ 148 #define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ 149 #define SAFE_PE_LEN_BYPASS_S 24 150 151 #define SAFE_PE_LEN_IS_DONE(_len) \ 152 (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) 153 154 /* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ 155 #define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ 156 #define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ 157 #define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ 158 #define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ 159 160 #define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ 161 #define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ 162 #define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ 163 164 #define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ 165 #define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ 166 167 #define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ 168 #define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ 169 #define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ 170 #define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ 171 #define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ 172 #define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ 173 #define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ 174 #define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ 175 #define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ 176 #define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ 177 #define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ 178 #define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ 179 #define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ 180 #define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ 181 #define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ 182 #define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ 183 #define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ 184 185 #define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ 186 #define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ 187 #define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ 188 #define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ 189 #define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ 190 #define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ 191 #define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ 192 #define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ 193 #define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ 194 #define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ 195 #define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ 196 #define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ 197 #define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ 198 #define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ 199 200 #define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ 201 #define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ 202 #define SAFE_PE_RINGCFG_OFFSET_S 16 203 204 #define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ 205 #define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ 206 #define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ 207 208 #define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ 209 210 #define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ 211 #define SAFE_PE_ERNGSTAT_NEXT_S 16 212 213 #define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ 214 #define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ 215 216 #define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ 217 #define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ 218 #define SAFE_PE_PARTCFG_GBURST_2 0x00000000 219 #define SAFE_PE_PARTCFG_GBURST_4 0x00010000 220 #define SAFE_PE_PARTCFG_GBURST_8 0x00020000 221 #define SAFE_PE_PARTCFG_GBURST_16 0x00030000 222 #define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ 223 #define SAFE_PE_PARTCFG_SBURST_2 0x00000000 224 #define SAFE_PE_PARTCFG_SBURST_4 0x00040000 225 #define SAFE_PE_PARTCFG_SBURST_8 0x00080000 226 #define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 227 228 #define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ 229 #define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ 230 231 #define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ 232 #define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ 233 #define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ 234 235 #define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ 236 #define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ 237 #define SAFE_DEVINFO_REV_MAJ_S 4 238 #define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ 239 #define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ 240 #define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ 241 #define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ 242 #define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ 243 #define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ 244 #define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ 245 #define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ 246 #define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ 247 #define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ 248 #define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ 249 250 #define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) 251 #define SAFE_REV_MAJ(_chiprev) \ 252 (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) 253 #define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) 254 255 #define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ 256 #define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ 257 #define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ 258 #define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ 259 #define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ 260 #define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ 261 #define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ 262 #define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ 263 #define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ 264 #define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ 265 #define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ 266 267 #define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ 268 269 #define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ 270 #define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ 271 #define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ 272 #define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ 273 #define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ 274 #define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ 275 #define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ 276 #define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ 277 #define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ 278 #define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ 279 280 /* 281 * Packet engine descriptor. Note that d_csr is a copy of the 282 * SAFE_PE_CSR register and all definitions apply, and d_len 283 * is a copy of the SAFE_PE_LEN register and all definitions apply. 284 * d_src and d_len may point directly to contiguous data or to a 285 * list of ``particle descriptors'' when using scatter/gather i/o. 286 */ 287 struct safe_desc { 288 u_int32_t d_csr; /* per-packet control/status */ 289 u_int32_t d_src; /* source address */ 290 u_int32_t d_dst; /* destination address */ 291 u_int32_t d_sa; /* SA address */ 292 u_int32_t d_len; /* length, bypass, status */ 293 }; 294 295 /* 296 * Scatter/Gather particle descriptor. 297 * 298 * NB: scatter descriptors do not specify a size; this is fixed 299 * by the setting of the SAFE_PE_PARTCFG register. 300 */ 301 struct safe_pdesc { 302 u_int32_t pd_addr; /* particle address */ 303 u_int16_t pd_flags; /* control word */ 304 u_int16_t pd_size; /* particle size (bytes) */ 305 }; 306 307 #define SAFE_PD_READY 0x0001 /* ready for processing */ 308 #define SAFE_PD_DONE 0x0002 /* h/w completed processing */ 309 310 /* 311 * Security Association (SA) Record (Rev 1). One of these is 312 * required for each operation processed by the packet engine. 313 */ 314 struct safe_sarec { 315 u_int32_t sa_cmd0; 316 u_int32_t sa_cmd1; 317 u_int32_t sa_resv0; 318 u_int32_t sa_resv1; 319 u_int32_t sa_key[8]; /* DES/3DES/AES key */ 320 u_int32_t sa_indigest[5]; /* inner digest */ 321 u_int32_t sa_outdigest[5]; /* outer digest */ 322 u_int32_t sa_spi; /* SPI */ 323 u_int32_t sa_seqnum; /* sequence number */ 324 u_int32_t sa_seqmask[2]; /* sequence number mask */ 325 u_int32_t sa_resv2; 326 u_int32_t sa_staterec; /* address of state record */ 327 u_int32_t sa_resv3[2]; 328 u_int32_t sa_samgmt0; /* SA management field 0 */ 329 u_int32_t sa_samgmt1; /* SA management field 0 */ 330 }; 331 332 #define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ 333 #define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ 334 #define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ 335 #define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ 336 #define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ 337 #define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ 338 #define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ 339 #define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ 340 #define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ 341 #define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ 342 #define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ 343 #define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ 344 #define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ 345 #define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ 346 #define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ 347 #define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ 348 #define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ 349 #define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ 350 #define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ 351 #define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ 352 #define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ 353 #define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ 354 #define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ 355 #define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ 356 #define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ 357 #define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ 358 #define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ 359 #define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ 360 #define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ 361 #define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ 362 #define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ 363 #define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ 364 #define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ 365 #define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ 366 #define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ 367 #define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ 368 #define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ 369 #define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ 370 #define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ 371 #define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ 372 #define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ 373 #define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ 374 #define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ 375 376 #define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ 377 #define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ 378 #define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ 379 #define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ 380 #define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ 381 #define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ 382 #define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ 383 #define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ 384 #define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ 385 #define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ 386 #define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ 387 #define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ 388 #define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ 389 #define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ 390 #define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ 391 #define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ 392 #define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ 393 #define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ 394 #define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ 395 #define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS 396 #define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ 397 #define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ 398 #define SAFE_SA_CMD1_OFFSET_S 16 399 #define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ 400 #define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ 401 #define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ 402 #define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ 403 404 /* 405 * Security Associate State Record (Rev 1). 406 */ 407 struct safe_sastate { 408 u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ 409 u_int32_t sa_saved_hashbc; /* saved hash byte count */ 410 u_int32_t sa_saved_indigest[5]; /* saved inner digest */ 411 }; 412 #endif /* _SAFE_SAFEREG_H_ */ 413