1 /*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * SafeNet SafeXcel-1141 hardware crypto accelerator 33 */ 34 #include "opt_safe.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/proc.h> 39 #include <sys/errno.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/mbuf.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/sysctl.h> 46 #include <sys/endian.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 51 #include <machine/clock.h> 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <sys/bus.h> 55 #include <sys/rman.h> 56 57 #include <crypto/sha1.h> 58 #include <opencrypto/cryptodev.h> 59 #include <opencrypto/cryptosoft.h> 60 #include <sys/md5.h> 61 #include <sys/random.h> 62 63 #include <pci/pcivar.h> 64 #include <pci/pcireg.h> 65 66 #ifdef SAFE_RNDTEST 67 #include <dev/rndtest/rndtest.h> 68 #endif 69 #include <dev/safe/safereg.h> 70 #include <dev/safe/safevar.h> 71 72 #ifndef bswap32 73 #define bswap32 NTOHL 74 #endif 75 76 /* 77 * Prototypes and count for the pci_device structure 78 */ 79 static int safe_probe(device_t); 80 static int safe_attach(device_t); 81 static int safe_detach(device_t); 82 static int safe_suspend(device_t); 83 static int safe_resume(device_t); 84 static void safe_shutdown(device_t); 85 86 static device_method_t safe_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_probe, safe_probe), 89 DEVMETHOD(device_attach, safe_attach), 90 DEVMETHOD(device_detach, safe_detach), 91 DEVMETHOD(device_suspend, safe_suspend), 92 DEVMETHOD(device_resume, safe_resume), 93 DEVMETHOD(device_shutdown, safe_shutdown), 94 95 /* bus interface */ 96 DEVMETHOD(bus_print_child, bus_generic_print_child), 97 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 98 99 { 0, 0 } 100 }; 101 static driver_t safe_driver = { 102 "safe", 103 safe_methods, 104 sizeof (struct safe_softc) 105 }; 106 static devclass_t safe_devclass; 107 108 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 109 MODULE_DEPEND(safe, crypto, 1, 1, 1); 110 #ifdef SAFE_RNDTEST 111 MODULE_DEPEND(safe, rndtest, 1, 1, 1); 112 #endif 113 114 static void safe_intr(void *); 115 static int safe_newsession(void *, u_int32_t *, struct cryptoini *); 116 static int safe_freesession(void *, u_int64_t); 117 static int safe_process(void *, struct cryptop *, int); 118 static void safe_callback(struct safe_softc *, struct safe_ringentry *); 119 static void safe_feed(struct safe_softc *, struct safe_ringentry *); 120 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 121 #ifndef SAFE_NO_RNG 122 static void safe_rng_init(struct safe_softc *); 123 static void safe_rng(void *); 124 #endif /* SAFE_NO_RNG */ 125 static int safe_dma_malloc(struct safe_softc *, bus_size_t, 126 struct safe_dma_alloc *, int); 127 #define safe_dma_sync(_dma, _flags) \ 128 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 129 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 130 static int safe_dmamap_aligned(const struct safe_operand *); 131 static int safe_dmamap_uniform(const struct safe_operand *); 132 133 static void safe_reset_board(struct safe_softc *); 134 static void safe_init_board(struct safe_softc *); 135 static void safe_init_pciregs(device_t dev); 136 static void safe_cleanchip(struct safe_softc *); 137 static void safe_totalreset(struct safe_softc *); 138 139 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 140 141 SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 142 143 #ifdef SAFE_DEBUG 144 static void safe_dump_dmastatus(struct safe_softc *, const char *); 145 static void safe_dump_ringstate(struct safe_softc *, const char *); 146 static void safe_dump_intrstate(struct safe_softc *, const char *); 147 static void safe_dump_request(struct safe_softc *, const char *, 148 struct safe_ringentry *); 149 150 static struct safe_softc *safec; /* for use by hw.safe.dump */ 151 152 static int safe_debug = 0; 153 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 154 0, "control debugging msgs"); 155 #define DPRINTF(_x) if (safe_debug) printf _x 156 #else 157 #define DPRINTF(_x) 158 #endif 159 160 #define READ_REG(sc,r) \ 161 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 162 163 #define WRITE_REG(sc,reg,val) \ 164 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 165 166 struct safe_stats safestats; 167 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 168 safe_stats, "driver statistics"); 169 #ifndef SAFE_NO_RNG 170 static int safe_rnginterval = 1; /* poll once a second */ 171 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 172 0, "RNG polling interval (secs)"); 173 static int safe_rngbufsize = 16; /* 64 bytes each poll */ 174 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 175 0, "RNG polling buffer size (32-bit words)"); 176 static int safe_rngmaxalarm = 8; /* max alarms before reset */ 177 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 178 0, "RNG max alarms before reset"); 179 #endif /* SAFE_NO_RNG */ 180 181 static int 182 safe_probe(device_t dev) 183 { 184 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 185 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 186 return (0); 187 return (ENXIO); 188 } 189 190 static const char* 191 safe_partname(struct safe_softc *sc) 192 { 193 /* XXX sprintf numbers when not decoded */ 194 switch (pci_get_vendor(sc->sc_dev)) { 195 case PCI_VENDOR_SAFENET: 196 switch (pci_get_device(sc->sc_dev)) { 197 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 198 } 199 return "SafeNet unknown-part"; 200 } 201 return "Unknown-vendor unknown-part"; 202 } 203 204 #ifndef SAFE_NO_RNG 205 static void 206 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 207 { 208 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 209 } 210 #endif /* SAFE_NO_RNG */ 211 212 static int 213 safe_attach(device_t dev) 214 { 215 struct safe_softc *sc = device_get_softc(dev); 216 u_int32_t raddr; 217 u_int32_t cmd, i, devinfo; 218 int rid; 219 220 bzero(sc, sizeof (*sc)); 221 sc->sc_dev = dev; 222 223 /* XXX handle power management */ 224 225 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 226 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 227 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 228 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 229 230 if (!(cmd & PCIM_CMD_MEMEN)) { 231 device_printf(dev, "failed to enable memory mapping\n"); 232 goto bad; 233 } 234 235 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 236 device_printf(dev, "failed to enable bus mastering\n"); 237 goto bad; 238 } 239 240 /* 241 * Setup memory-mapping of PCI registers. 242 */ 243 rid = BS_BAR; 244 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 245 0, ~0, 1, RF_ACTIVE); 246 if (sc->sc_sr == NULL) { 247 device_printf(dev, "cannot map register space\n"); 248 goto bad; 249 } 250 sc->sc_st = rman_get_bustag(sc->sc_sr); 251 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 252 253 /* 254 * Arrange interrupt line. 255 */ 256 rid = 0; 257 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 258 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 259 if (sc->sc_irq == NULL) { 260 device_printf(dev, "could not map interrupt\n"); 261 goto bad1; 262 } 263 /* 264 * NB: Network code assumes we are blocked with splimp() 265 * so make sure the IRQ is mapped appropriately. 266 */ 267 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 268 safe_intr, sc, &sc->sc_ih)) { 269 device_printf(dev, "could not establish interrupt\n"); 270 goto bad2; 271 } 272 273 sc->sc_cid = crypto_get_driverid(0); 274 if (sc->sc_cid < 0) { 275 device_printf(dev, "could not get crypto driver id\n"); 276 goto bad3; 277 } 278 279 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 280 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 281 282 /* 283 * Setup DMA descriptor area. 284 */ 285 if (bus_dma_tag_create(NULL, /* parent */ 286 1, /* alignment */ 287 SAFE_DMA_BOUNDARY, /* boundary */ 288 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 289 BUS_SPACE_MAXADDR, /* highaddr */ 290 NULL, NULL, /* filter, filterarg */ 291 SAFE_MAX_DMA, /* maxsize */ 292 SAFE_MAX_PART, /* nsegments */ 293 SAFE_MAX_SSIZE, /* maxsegsize */ 294 BUS_DMA_ALLOCNOW, /* flags */ 295 NULL, NULL, /* locking */ 296 &sc->sc_srcdmat)) { 297 device_printf(dev, "cannot allocate DMA tag\n"); 298 goto bad4; 299 } 300 if (bus_dma_tag_create(NULL, /* parent */ 301 sizeof(u_int32_t), /* alignment */ 302 SAFE_MAX_DSIZE, /* boundary */ 303 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 304 BUS_SPACE_MAXADDR, /* highaddr */ 305 NULL, NULL, /* filter, filterarg */ 306 SAFE_MAX_DMA, /* maxsize */ 307 SAFE_MAX_PART, /* nsegments */ 308 SAFE_MAX_DSIZE, /* maxsegsize */ 309 BUS_DMA_ALLOCNOW, /* flags */ 310 NULL, NULL, /* locking */ 311 &sc->sc_dstdmat)) { 312 device_printf(dev, "cannot allocate DMA tag\n"); 313 goto bad4; 314 } 315 316 /* 317 * Allocate packet engine descriptors. 318 */ 319 if (safe_dma_malloc(sc, 320 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 321 &sc->sc_ringalloc, 0)) { 322 device_printf(dev, "cannot allocate PE descriptor ring\n"); 323 bus_dma_tag_destroy(sc->sc_srcdmat); 324 goto bad4; 325 } 326 /* 327 * Hookup the static portion of all our data structures. 328 */ 329 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 330 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 331 sc->sc_front = sc->sc_ring; 332 sc->sc_back = sc->sc_ring; 333 raddr = sc->sc_ringalloc.dma_paddr; 334 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 335 for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 336 struct safe_ringentry *re = &sc->sc_ring[i]; 337 338 re->re_desc.d_sa = raddr + 339 offsetof(struct safe_ringentry, re_sa); 340 re->re_sa.sa_staterec = raddr + 341 offsetof(struct safe_ringentry, re_sastate); 342 343 raddr += sizeof (struct safe_ringentry); 344 } 345 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 346 "packet engine ring", MTX_DEF); 347 348 /* 349 * Allocate scatter and gather particle descriptors. 350 */ 351 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 352 &sc->sc_spalloc, 0)) { 353 device_printf(dev, "cannot allocate source particle " 354 "descriptor ring\n"); 355 mtx_destroy(&sc->sc_ringmtx); 356 safe_dma_free(sc, &sc->sc_ringalloc); 357 bus_dma_tag_destroy(sc->sc_srcdmat); 358 goto bad4; 359 } 360 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 361 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 362 sc->sc_spfree = sc->sc_spring; 363 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 364 365 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 366 &sc->sc_dpalloc, 0)) { 367 device_printf(dev, "cannot allocate destination particle " 368 "descriptor ring\n"); 369 mtx_destroy(&sc->sc_ringmtx); 370 safe_dma_free(sc, &sc->sc_spalloc); 371 safe_dma_free(sc, &sc->sc_ringalloc); 372 bus_dma_tag_destroy(sc->sc_dstdmat); 373 goto bad4; 374 } 375 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 376 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 377 sc->sc_dpfree = sc->sc_dpring; 378 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 379 380 device_printf(sc->sc_dev, "%s", safe_partname(sc)); 381 382 devinfo = READ_REG(sc, SAFE_DEVINFO); 383 if (devinfo & SAFE_DEVINFO_RNG) { 384 sc->sc_flags |= SAFE_FLAGS_RNG; 385 printf(" rng"); 386 } 387 if (devinfo & SAFE_DEVINFO_PKEY) { 388 #if 0 389 printf(" key"); 390 sc->sc_flags |= SAFE_FLAGS_KEY; 391 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 392 safe_kprocess, sc); 393 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 394 safe_kprocess, sc); 395 #endif 396 } 397 if (devinfo & SAFE_DEVINFO_DES) { 398 printf(" des/3des"); 399 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 400 safe_newsession, safe_freesession, safe_process, sc); 401 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 402 safe_newsession, safe_freesession, safe_process, sc); 403 } 404 if (devinfo & SAFE_DEVINFO_AES) { 405 printf(" aes"); 406 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 407 safe_newsession, safe_freesession, safe_process, sc); 408 } 409 if (devinfo & SAFE_DEVINFO_MD5) { 410 printf(" md5"); 411 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 412 safe_newsession, safe_freesession, safe_process, sc); 413 } 414 if (devinfo & SAFE_DEVINFO_SHA1) { 415 printf(" sha1"); 416 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 417 safe_newsession, safe_freesession, safe_process, sc); 418 } 419 printf(" null"); 420 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0, 421 safe_newsession, safe_freesession, safe_process, sc); 422 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0, 423 safe_newsession, safe_freesession, safe_process, sc); 424 /* XXX other supported algorithms */ 425 printf("\n"); 426 427 safe_reset_board(sc); /* reset h/w */ 428 safe_init_pciregs(dev); /* init pci settings */ 429 safe_init_board(sc); /* init h/w */ 430 431 #ifndef SAFE_NO_RNG 432 if (sc->sc_flags & SAFE_FLAGS_RNG) { 433 #ifdef SAFE_RNDTEST 434 sc->sc_rndtest = rndtest_attach(dev); 435 if (sc->sc_rndtest) 436 sc->sc_harvest = rndtest_harvest; 437 else 438 sc->sc_harvest = default_harvest; 439 #else 440 sc->sc_harvest = default_harvest; 441 #endif 442 safe_rng_init(sc); 443 444 /* NB: 1 means the callout runs w/o Giant locked */ 445 callout_init(&sc->sc_rngto, 1); 446 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 447 } 448 #endif /* SAFE_NO_RNG */ 449 #ifdef SAFE_DEBUG 450 safec = sc; /* for use by hw.safe.dump */ 451 #endif 452 return (0); 453 bad4: 454 crypto_unregister_all(sc->sc_cid); 455 bad3: 456 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 457 bad2: 458 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 459 bad1: 460 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 461 bad: 462 return (ENXIO); 463 } 464 465 /* 466 * Detach a device that successfully probed. 467 */ 468 static int 469 safe_detach(device_t dev) 470 { 471 struct safe_softc *sc = device_get_softc(dev); 472 473 /* XXX wait/abort active ops */ 474 475 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 476 477 callout_stop(&sc->sc_rngto); 478 479 crypto_unregister_all(sc->sc_cid); 480 481 #ifdef SAFE_RNDTEST 482 if (sc->sc_rndtest) 483 rndtest_detach(sc->sc_rndtest); 484 #endif 485 486 safe_cleanchip(sc); 487 safe_dma_free(sc, &sc->sc_dpalloc); 488 safe_dma_free(sc, &sc->sc_spalloc); 489 mtx_destroy(&sc->sc_ringmtx); 490 safe_dma_free(sc, &sc->sc_ringalloc); 491 492 bus_generic_detach(dev); 493 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 494 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 495 496 bus_dma_tag_destroy(sc->sc_srcdmat); 497 bus_dma_tag_destroy(sc->sc_dstdmat); 498 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 499 500 return (0); 501 } 502 503 /* 504 * Stop all chip i/o so that the kernel's probe routines don't 505 * get confused by errant DMAs when rebooting. 506 */ 507 static void 508 safe_shutdown(device_t dev) 509 { 510 #ifdef notyet 511 safe_stop(device_get_softc(dev)); 512 #endif 513 } 514 515 /* 516 * Device suspend routine. 517 */ 518 static int 519 safe_suspend(device_t dev) 520 { 521 struct safe_softc *sc = device_get_softc(dev); 522 523 #ifdef notyet 524 /* XXX stop the device and save PCI settings */ 525 #endif 526 sc->sc_suspended = 1; 527 528 return (0); 529 } 530 531 static int 532 safe_resume(device_t dev) 533 { 534 struct safe_softc *sc = device_get_softc(dev); 535 536 #ifdef notyet 537 /* XXX retore PCI settings and start the device */ 538 #endif 539 sc->sc_suspended = 0; 540 return (0); 541 } 542 543 /* 544 * SafeXcel Interrupt routine 545 */ 546 static void 547 safe_intr(void *arg) 548 { 549 struct safe_softc *sc = arg; 550 volatile u_int32_t stat; 551 552 stat = READ_REG(sc, SAFE_HM_STAT); 553 if (stat == 0) /* shared irq, not for us */ 554 return; 555 556 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 557 558 if ((stat & SAFE_INT_PE_DDONE)) { 559 /* 560 * Descriptor(s) done; scan the ring and 561 * process completed operations. 562 */ 563 mtx_lock(&sc->sc_ringmtx); 564 while (sc->sc_back != sc->sc_front) { 565 struct safe_ringentry *re = sc->sc_back; 566 #ifdef SAFE_DEBUG 567 if (safe_debug) { 568 safe_dump_ringstate(sc, __func__); 569 safe_dump_request(sc, __func__, re); 570 } 571 #endif 572 /* 573 * safe_process marks ring entries that were allocated 574 * but not used with a csr of zero. This insures the 575 * ring front pointer never needs to be set backwards 576 * in the event that an entry is allocated but not used 577 * because of a setup error. 578 */ 579 if (re->re_desc.d_csr != 0) { 580 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 581 break; 582 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 583 break; 584 sc->sc_nqchip--; 585 safe_callback(sc, re); 586 } 587 if (++(sc->sc_back) == sc->sc_ringtop) 588 sc->sc_back = sc->sc_ring; 589 } 590 mtx_unlock(&sc->sc_ringmtx); 591 } 592 593 /* 594 * Check to see if we got any DMA Error 595 */ 596 if (stat & SAFE_INT_PE_ERROR) { 597 DPRINTF(("dmaerr dmastat %08x\n", 598 READ_REG(sc, SAFE_PE_DMASTAT))); 599 safestats.st_dmaerr++; 600 safe_totalreset(sc); 601 #if 0 602 safe_feed(sc); 603 #endif 604 } 605 606 if (sc->sc_needwakeup) { /* XXX check high watermark */ 607 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 608 DPRINTF(("%s: wakeup crypto %x\n", __func__, 609 sc->sc_needwakeup)); 610 sc->sc_needwakeup &= ~wakeup; 611 crypto_unblock(sc->sc_cid, wakeup); 612 } 613 } 614 615 /* 616 * safe_feed() - post a request to chip 617 */ 618 static void 619 safe_feed(struct safe_softc *sc, struct safe_ringentry *re) 620 { 621 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 622 if (re->re_dst_map != NULL) 623 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 624 BUS_DMASYNC_PREREAD); 625 /* XXX have no smaller granularity */ 626 safe_dma_sync(&sc->sc_ringalloc, 627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 628 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 629 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 630 631 #ifdef SAFE_DEBUG 632 if (safe_debug) { 633 safe_dump_ringstate(sc, __func__); 634 safe_dump_request(sc, __func__, re); 635 } 636 #endif 637 sc->sc_nqchip++; 638 if (sc->sc_nqchip > safestats.st_maxqchip) 639 safestats.st_maxqchip = sc->sc_nqchip; 640 /* poke h/w to check descriptor ring, any value can be written */ 641 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 642 } 643 644 /* 645 * Allocate a new 'session' and return an encoded session id. 'sidp' 646 * contains our registration id, and should contain an encoded session 647 * id on successful allocation. 648 */ 649 static int 650 safe_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 651 { 652 #define N(a) (sizeof(a) / sizeof (a[0])) 653 struct cryptoini *c, *encini = NULL, *macini = NULL; 654 struct safe_softc *sc = arg; 655 struct safe_session *ses = NULL; 656 MD5_CTX md5ctx; 657 SHA1_CTX sha1ctx; 658 int i, sesn; 659 660 if (sidp == NULL || cri == NULL || sc == NULL) 661 return (EINVAL); 662 663 for (c = cri; c != NULL; c = c->cri_next) { 664 if (c->cri_alg == CRYPTO_MD5_HMAC || 665 c->cri_alg == CRYPTO_SHA1_HMAC || 666 c->cri_alg == CRYPTO_NULL_HMAC) { 667 if (macini) 668 return (EINVAL); 669 macini = c; 670 } else if (c->cri_alg == CRYPTO_DES_CBC || 671 c->cri_alg == CRYPTO_3DES_CBC || 672 c->cri_alg == CRYPTO_AES_CBC || 673 c->cri_alg == CRYPTO_NULL_CBC) { 674 if (encini) 675 return (EINVAL); 676 encini = c; 677 } else 678 return (EINVAL); 679 } 680 if (encini == NULL && macini == NULL) 681 return (EINVAL); 682 if (encini) { /* validate key length */ 683 switch (encini->cri_alg) { 684 case CRYPTO_DES_CBC: 685 if (encini->cri_klen != 64) 686 return (EINVAL); 687 break; 688 case CRYPTO_3DES_CBC: 689 if (encini->cri_klen != 192) 690 return (EINVAL); 691 break; 692 case CRYPTO_AES_CBC: 693 if (encini->cri_klen != 128 && 694 encini->cri_klen != 192 && 695 encini->cri_klen != 256) 696 return (EINVAL); 697 break; 698 } 699 } 700 701 if (sc->sc_sessions == NULL) { 702 ses = sc->sc_sessions = (struct safe_session *)malloc( 703 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 704 if (ses == NULL) 705 return (ENOMEM); 706 sesn = 0; 707 sc->sc_nsessions = 1; 708 } else { 709 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 710 if (sc->sc_sessions[sesn].ses_used == 0) { 711 ses = &sc->sc_sessions[sesn]; 712 break; 713 } 714 } 715 716 if (ses == NULL) { 717 sesn = sc->sc_nsessions; 718 ses = (struct safe_session *)malloc((sesn + 1) * 719 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 720 if (ses == NULL) 721 return (ENOMEM); 722 bcopy(sc->sc_sessions, ses, sesn * 723 sizeof(struct safe_session)); 724 bzero(sc->sc_sessions, sesn * 725 sizeof(struct safe_session)); 726 free(sc->sc_sessions, M_DEVBUF); 727 sc->sc_sessions = ses; 728 ses = &sc->sc_sessions[sesn]; 729 sc->sc_nsessions++; 730 } 731 } 732 733 bzero(ses, sizeof(struct safe_session)); 734 ses->ses_used = 1; 735 736 if (encini) { 737 /* get an IV */ 738 /* XXX may read fewer than requested */ 739 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 740 741 ses->ses_klen = encini->cri_klen; 742 bcopy(encini->cri_key, ses->ses_key, ses->ses_klen / 8); 743 744 /* PE is little-endian, insure proper byte order */ 745 for (i = 0; i < N(ses->ses_key); i++) 746 ses->ses_key[i] = htole32(ses->ses_key[i]); 747 } 748 749 if (macini) { 750 for (i = 0; i < macini->cri_klen / 8; i++) 751 macini->cri_key[i] ^= HMAC_IPAD_VAL; 752 753 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 754 MD5Init(&md5ctx); 755 MD5Update(&md5ctx, macini->cri_key, 756 macini->cri_klen / 8); 757 MD5Update(&md5ctx, hmac_ipad_buffer, 758 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 759 bcopy(md5ctx.state, ses->ses_hminner, 760 sizeof(md5ctx.state)); 761 } else { 762 SHA1Init(&sha1ctx); 763 SHA1Update(&sha1ctx, macini->cri_key, 764 macini->cri_klen / 8); 765 SHA1Update(&sha1ctx, hmac_ipad_buffer, 766 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 767 bcopy(sha1ctx.h.b32, ses->ses_hminner, 768 sizeof(sha1ctx.h.b32)); 769 } 770 771 for (i = 0; i < macini->cri_klen / 8; i++) 772 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 773 774 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 775 MD5Init(&md5ctx); 776 MD5Update(&md5ctx, macini->cri_key, 777 macini->cri_klen / 8); 778 MD5Update(&md5ctx, hmac_opad_buffer, 779 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 780 bcopy(md5ctx.state, ses->ses_hmouter, 781 sizeof(md5ctx.state)); 782 } else { 783 SHA1Init(&sha1ctx); 784 SHA1Update(&sha1ctx, macini->cri_key, 785 macini->cri_klen / 8); 786 SHA1Update(&sha1ctx, hmac_opad_buffer, 787 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 788 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 789 sizeof(sha1ctx.h.b32)); 790 } 791 792 for (i = 0; i < macini->cri_klen / 8; i++) 793 macini->cri_key[i] ^= HMAC_OPAD_VAL; 794 795 /* PE is little-endian, insure proper byte order */ 796 for (i = 0; i < N(ses->ses_hminner); i++) { 797 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 798 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 799 } 800 } 801 802 *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 803 return (0); 804 #undef N 805 } 806 807 /* 808 * Deallocate a session. 809 */ 810 static int 811 safe_freesession(void *arg, u_int64_t tid) 812 { 813 struct safe_softc *sc = arg; 814 int session, ret; 815 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 816 817 if (sc == NULL) 818 return (EINVAL); 819 820 session = SAFE_SESSION(sid); 821 if (session < sc->sc_nsessions) { 822 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 823 ret = 0; 824 } else 825 ret = EINVAL; 826 return (ret); 827 } 828 829 static void 830 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 831 { 832 struct safe_operand *op = arg; 833 834 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 835 (u_int) mapsize, nsegs, error)); 836 if (error != 0) 837 return; 838 op->mapsize = mapsize; 839 op->nsegs = nsegs; 840 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 841 } 842 843 static int 844 safe_process(void *arg, struct cryptop *crp, int hint) 845 { 846 int err = 0, i, nicealign, uniform; 847 struct safe_softc *sc = arg; 848 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 849 int bypass, oplen, ivsize; 850 caddr_t iv; 851 int16_t coffset; 852 struct safe_session *ses; 853 struct safe_ringentry *re; 854 struct safe_sarec *sa; 855 struct safe_pdesc *pd; 856 u_int32_t cmd0, cmd1, staterec; 857 858 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 859 safestats.st_invalid++; 860 return (EINVAL); 861 } 862 if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 863 safestats.st_badsession++; 864 return (EINVAL); 865 } 866 867 mtx_lock(&sc->sc_ringmtx); 868 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 869 safestats.st_ringfull++; 870 sc->sc_needwakeup |= CRYPTO_SYMQ; 871 mtx_unlock(&sc->sc_ringmtx); 872 return (ERESTART); 873 } 874 re = sc->sc_front; 875 876 staterec = re->re_sa.sa_staterec; /* save */ 877 /* NB: zero everything but the PE descriptor */ 878 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 879 re->re_sa.sa_staterec = staterec; /* restore */ 880 881 re->re_crp = crp; 882 re->re_sesn = SAFE_SESSION(crp->crp_sid); 883 884 if (crp->crp_flags & CRYPTO_F_IMBUF) { 885 re->re_src_m = (struct mbuf *)crp->crp_buf; 886 re->re_dst_m = (struct mbuf *)crp->crp_buf; 887 } else if (crp->crp_flags & CRYPTO_F_IOV) { 888 re->re_src_io = (struct uio *)crp->crp_buf; 889 re->re_dst_io = (struct uio *)crp->crp_buf; 890 } else { 891 safestats.st_badflags++; 892 err = EINVAL; 893 goto errout; /* XXX we don't handle contiguous blocks! */ 894 } 895 896 sa = &re->re_sa; 897 ses = &sc->sc_sessions[re->re_sesn]; 898 899 crd1 = crp->crp_desc; 900 if (crd1 == NULL) { 901 safestats.st_nodesc++; 902 err = EINVAL; 903 goto errout; 904 } 905 crd2 = crd1->crd_next; 906 907 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 908 cmd1 = 0; 909 if (crd2 == NULL) { 910 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 911 crd1->crd_alg == CRYPTO_SHA1_HMAC || 912 crd1->crd_alg == CRYPTO_NULL_HMAC) { 913 maccrd = crd1; 914 enccrd = NULL; 915 cmd0 |= SAFE_SA_CMD0_OP_HASH; 916 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 917 crd1->crd_alg == CRYPTO_3DES_CBC || 918 crd1->crd_alg == CRYPTO_AES_CBC || 919 crd1->crd_alg == CRYPTO_NULL_CBC) { 920 maccrd = NULL; 921 enccrd = crd1; 922 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 923 } else { 924 safestats.st_badalg++; 925 err = EINVAL; 926 goto errout; 927 } 928 } else { 929 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 930 crd1->crd_alg == CRYPTO_SHA1_HMAC || 931 crd1->crd_alg == CRYPTO_NULL_HMAC) && 932 (crd2->crd_alg == CRYPTO_DES_CBC || 933 crd2->crd_alg == CRYPTO_3DES_CBC || 934 crd2->crd_alg == CRYPTO_AES_CBC || 935 crd2->crd_alg == CRYPTO_NULL_CBC) && 936 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 937 maccrd = crd1; 938 enccrd = crd2; 939 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 940 crd1->crd_alg == CRYPTO_3DES_CBC || 941 crd1->crd_alg == CRYPTO_AES_CBC || 942 crd1->crd_alg == CRYPTO_NULL_CBC) && 943 (crd2->crd_alg == CRYPTO_MD5_HMAC || 944 crd2->crd_alg == CRYPTO_SHA1_HMAC || 945 crd2->crd_alg == CRYPTO_NULL_HMAC) && 946 (crd1->crd_flags & CRD_F_ENCRYPT)) { 947 enccrd = crd1; 948 maccrd = crd2; 949 } else { 950 safestats.st_badalg++; 951 err = EINVAL; 952 goto errout; 953 } 954 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 955 } 956 957 if (enccrd) { 958 if (enccrd->crd_alg == CRYPTO_DES_CBC) { 959 cmd0 |= SAFE_SA_CMD0_DES; 960 cmd1 |= SAFE_SA_CMD1_CBC; 961 ivsize = 2*sizeof(u_int32_t); 962 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 963 cmd0 |= SAFE_SA_CMD0_3DES; 964 cmd1 |= SAFE_SA_CMD1_CBC; 965 ivsize = 2*sizeof(u_int32_t); 966 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 967 cmd0 |= SAFE_SA_CMD0_AES; 968 cmd1 |= SAFE_SA_CMD1_CBC; 969 if (ses->ses_klen == 128) 970 cmd1 |= SAFE_SA_CMD1_AES128; 971 else if (ses->ses_klen == 192) 972 cmd1 |= SAFE_SA_CMD1_AES192; 973 else 974 cmd1 |= SAFE_SA_CMD1_AES256; 975 ivsize = 4*sizeof(u_int32_t); 976 } else { 977 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 978 ivsize = 0; 979 } 980 981 /* 982 * Setup encrypt/decrypt state. When using basic ops 983 * we can't use an inline IV because hash/crypt offset 984 * must be from the end of the IV to the start of the 985 * crypt data and this leaves out the preceding header 986 * from the hash calculation. Instead we place the IV 987 * in the state record and set the hash/crypt offset to 988 * copy both the header+IV. 989 */ 990 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 991 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 992 993 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 994 iv = enccrd->crd_iv; 995 else 996 iv = (caddr_t) ses->ses_iv; 997 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 998 if (crp->crp_flags & CRYPTO_F_IMBUF) 999 m_copyback(re->re_src_m, 1000 enccrd->crd_inject, ivsize, iv); 1001 else if (crp->crp_flags & CRYPTO_F_IOV) 1002 cuio_copyback(re->re_src_io, 1003 enccrd->crd_inject, ivsize, iv); 1004 } 1005 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1006 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1007 re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1008 } else { 1009 cmd0 |= SAFE_SA_CMD0_INBOUND; 1010 1011 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1012 bcopy(enccrd->crd_iv, 1013 re->re_sastate.sa_saved_iv, ivsize); 1014 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1015 m_copydata(re->re_src_m, enccrd->crd_inject, 1016 ivsize, 1017 (caddr_t)re->re_sastate.sa_saved_iv); 1018 else if (crp->crp_flags & CRYPTO_F_IOV) 1019 cuio_copydata(re->re_src_io, enccrd->crd_inject, 1020 ivsize, 1021 (caddr_t)re->re_sastate.sa_saved_iv); 1022 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1023 } 1024 /* 1025 * For basic encryption use the zero pad algorithm. 1026 * This pads results to an 8-byte boundary and 1027 * suppresses padding verification for inbound (i.e. 1028 * decrypt) operations. 1029 * 1030 * NB: Not sure if the 8-byte pad boundary is a problem. 1031 */ 1032 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1033 1034 /* XXX assert key bufs have the same size */ 1035 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1036 } 1037 1038 if (maccrd) { 1039 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1040 cmd0 |= SAFE_SA_CMD0_MD5; 1041 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1042 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1043 cmd0 |= SAFE_SA_CMD0_SHA1; 1044 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1045 } else { 1046 cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1047 } 1048 /* 1049 * Digest data is loaded from the SA and the hash 1050 * result is saved to the state block where we 1051 * retrieve it for return to the caller. 1052 */ 1053 /* XXX assert digest bufs have the same size */ 1054 bcopy(ses->ses_hminner, sa->sa_indigest, 1055 sizeof(sa->sa_indigest)); 1056 bcopy(ses->ses_hmouter, sa->sa_outdigest, 1057 sizeof(sa->sa_outdigest)); 1058 1059 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1060 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1061 } 1062 1063 if (enccrd && maccrd) { 1064 /* 1065 * The offset from hash data to the start of 1066 * crypt data is the difference in the skips. 1067 */ 1068 bypass = maccrd->crd_skip; 1069 coffset = enccrd->crd_skip - maccrd->crd_skip; 1070 if (coffset < 0) { 1071 DPRINTF(("%s: hash does not precede crypt; " 1072 "mac skip %u enc skip %u\n", 1073 __func__, maccrd->crd_skip, enccrd->crd_skip)); 1074 safestats.st_skipmismatch++; 1075 err = EINVAL; 1076 goto errout; 1077 } 1078 oplen = enccrd->crd_skip + enccrd->crd_len; 1079 if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1080 DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1081 __func__, maccrd->crd_skip + maccrd->crd_len, 1082 oplen)); 1083 safestats.st_lenmismatch++; 1084 err = EINVAL; 1085 goto errout; 1086 } 1087 #ifdef SAFE_DEBUG 1088 if (safe_debug) { 1089 printf("mac: skip %d, len %d, inject %d\n", 1090 maccrd->crd_skip, maccrd->crd_len, 1091 maccrd->crd_inject); 1092 printf("enc: skip %d, len %d, inject %d\n", 1093 enccrd->crd_skip, enccrd->crd_len, 1094 enccrd->crd_inject); 1095 printf("bypass %d coffset %d oplen %d\n", 1096 bypass, coffset, oplen); 1097 } 1098 #endif 1099 if (coffset & 3) { /* offset must be 32-bit aligned */ 1100 DPRINTF(("%s: coffset %u misaligned\n", 1101 __func__, coffset)); 1102 safestats.st_coffmisaligned++; 1103 err = EINVAL; 1104 goto errout; 1105 } 1106 coffset >>= 2; 1107 if (coffset > 255) { /* offset must be <256 dwords */ 1108 DPRINTF(("%s: coffset %u too big\n", 1109 __func__, coffset)); 1110 safestats.st_cofftoobig++; 1111 err = EINVAL; 1112 goto errout; 1113 } 1114 /* 1115 * Tell the hardware to copy the header to the output. 1116 * The header is defined as the data from the end of 1117 * the bypass to the start of data to be encrypted. 1118 * Typically this is the inline IV. Note that you need 1119 * to do this even if src+dst are the same; it appears 1120 * that w/o this bit the crypted data is written 1121 * immediately after the bypass data. 1122 */ 1123 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1124 /* 1125 * Disable IP header mutable bit handling. This is 1126 * needed to get correct HMAC calculations. 1127 */ 1128 cmd1 |= SAFE_SA_CMD1_MUTABLE; 1129 } else { 1130 if (enccrd) { 1131 bypass = enccrd->crd_skip; 1132 oplen = bypass + enccrd->crd_len; 1133 } else { 1134 bypass = maccrd->crd_skip; 1135 oplen = bypass + maccrd->crd_len; 1136 } 1137 coffset = 0; 1138 } 1139 /* XXX verify multiple of 4 when using s/g */ 1140 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1141 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1142 safestats.st_bypasstoobig++; 1143 err = EINVAL; 1144 goto errout; 1145 } 1146 1147 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1148 safestats.st_nomap++; 1149 err = ENOMEM; 1150 goto errout; 1151 } 1152 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1153 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1154 re->re_src_m, safe_op_cb, 1155 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1156 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1157 re->re_src_map = NULL; 1158 safestats.st_noload++; 1159 err = ENOMEM; 1160 goto errout; 1161 } 1162 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1163 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1164 re->re_src_io, safe_op_cb, 1165 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1166 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1167 re->re_src_map = NULL; 1168 safestats.st_noload++; 1169 err = ENOMEM; 1170 goto errout; 1171 } 1172 } 1173 nicealign = safe_dmamap_aligned(&re->re_src); 1174 uniform = safe_dmamap_uniform(&re->re_src); 1175 1176 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1177 nicealign, uniform, re->re_src.nsegs)); 1178 if (re->re_src.nsegs > 1) { 1179 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1180 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1181 for (i = 0; i < re->re_src_nsegs; i++) { 1182 /* NB: no need to check if there's space */ 1183 pd = sc->sc_spfree; 1184 if (++(sc->sc_spfree) == sc->sc_springtop) 1185 sc->sc_spfree = sc->sc_spring; 1186 1187 KASSERT((pd->pd_flags&3) == 0 || 1188 (pd->pd_flags&3) == SAFE_PD_DONE, 1189 ("bogus source particle descriptor; flags %x", 1190 pd->pd_flags)); 1191 pd->pd_addr = re->re_src_segs[i].ds_addr; 1192 pd->pd_size = re->re_src_segs[i].ds_len; 1193 pd->pd_flags = SAFE_PD_READY; 1194 } 1195 cmd0 |= SAFE_SA_CMD0_IGATHER; 1196 } else { 1197 /* 1198 * No need for gather, reference the operand directly. 1199 */ 1200 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1201 } 1202 1203 if (enccrd == NULL && maccrd != NULL) { 1204 /* 1205 * Hash op; no destination needed. 1206 */ 1207 } else { 1208 if (crp->crp_flags & CRYPTO_F_IOV) { 1209 if (!nicealign) { 1210 safestats.st_iovmisaligned++; 1211 err = EINVAL; 1212 goto errout; 1213 } 1214 if (uniform != 1) { 1215 /* 1216 * Source is not suitable for direct use as 1217 * the destination. Create a new scatter/gather 1218 * list based on the destination requirements 1219 * and check if that's ok. 1220 */ 1221 if (bus_dmamap_create(sc->sc_dstdmat, 1222 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1223 safestats.st_nomap++; 1224 err = ENOMEM; 1225 goto errout; 1226 } 1227 if (bus_dmamap_load_uio(sc->sc_dstdmat, 1228 re->re_dst_map, re->re_dst_io, 1229 safe_op_cb, &re->re_dst, 1230 BUS_DMA_NOWAIT) != 0) { 1231 bus_dmamap_destroy(sc->sc_dstdmat, 1232 re->re_dst_map); 1233 re->re_dst_map = NULL; 1234 safestats.st_noload++; 1235 err = ENOMEM; 1236 goto errout; 1237 } 1238 uniform = safe_dmamap_uniform(&re->re_dst); 1239 if (!uniform) { 1240 /* 1241 * There's no way to handle the DMA 1242 * requirements with this uio. We 1243 * could create a separate DMA area for 1244 * the result and then copy it back, 1245 * but for now we just bail and return 1246 * an error. Note that uio requests 1247 * > SAFE_MAX_DSIZE are handled because 1248 * the DMA map and segment list for the 1249 * destination wil result in a 1250 * destination particle list that does 1251 * the necessary scatter DMA. 1252 */ 1253 safestats.st_iovnotuniform++; 1254 err = EINVAL; 1255 goto errout; 1256 } 1257 } 1258 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1259 if (nicealign && uniform == 1) { 1260 /* 1261 * Source layout is suitable for direct 1262 * sharing of the DMA map and segment list. 1263 */ 1264 re->re_dst = re->re_src; 1265 } else if (nicealign && uniform == 2) { 1266 /* 1267 * The source is properly aligned but requires a 1268 * different particle list to handle DMA of the 1269 * result. Create a new map and do the load to 1270 * create the segment list. The particle 1271 * descriptor setup code below will handle the 1272 * rest. 1273 */ 1274 if (bus_dmamap_create(sc->sc_dstdmat, 1275 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1276 safestats.st_nomap++; 1277 err = ENOMEM; 1278 goto errout; 1279 } 1280 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1281 re->re_dst_map, re->re_dst_m, 1282 safe_op_cb, &re->re_dst, 1283 BUS_DMA_NOWAIT) != 0) { 1284 bus_dmamap_destroy(sc->sc_dstdmat, 1285 re->re_dst_map); 1286 re->re_dst_map = NULL; 1287 safestats.st_noload++; 1288 err = ENOMEM; 1289 goto errout; 1290 } 1291 } else { /* !(aligned and/or uniform) */ 1292 int totlen, len; 1293 struct mbuf *m, *top, **mp; 1294 1295 /* 1296 * DMA constraints require that we allocate a 1297 * new mbuf chain for the destination. We 1298 * allocate an entire new set of mbufs of 1299 * optimal/required size and then tell the 1300 * hardware to copy any bits that are not 1301 * created as a byproduct of the operation. 1302 */ 1303 if (!nicealign) 1304 safestats.st_unaligned++; 1305 if (!uniform) 1306 safestats.st_notuniform++; 1307 totlen = re->re_src_mapsize; 1308 if (re->re_src_m->m_flags & M_PKTHDR) { 1309 len = MHLEN; 1310 MGETHDR(m, M_DONTWAIT, MT_DATA); 1311 if (m && !m_dup_pkthdr(m, re->re_src_m, 1312 M_DONTWAIT)) { 1313 m_free(m); 1314 m = NULL; 1315 } 1316 } else { 1317 len = MLEN; 1318 MGET(m, M_DONTWAIT, MT_DATA); 1319 } 1320 if (m == NULL) { 1321 safestats.st_nombuf++; 1322 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1323 goto errout; 1324 } 1325 if (totlen >= MINCLSIZE) { 1326 MCLGET(m, M_DONTWAIT); 1327 if ((m->m_flags & M_EXT) == 0) { 1328 m_free(m); 1329 safestats.st_nomcl++; 1330 err = sc->sc_nqchip ? 1331 ERESTART : ENOMEM; 1332 goto errout; 1333 } 1334 len = MCLBYTES; 1335 } 1336 m->m_len = len; 1337 top = NULL; 1338 mp = ⊤ 1339 1340 while (totlen > 0) { 1341 if (top) { 1342 MGET(m, M_DONTWAIT, MT_DATA); 1343 if (m == NULL) { 1344 m_freem(top); 1345 safestats.st_nombuf++; 1346 err = sc->sc_nqchip ? 1347 ERESTART : ENOMEM; 1348 goto errout; 1349 } 1350 len = MLEN; 1351 } 1352 if (top && totlen >= MINCLSIZE) { 1353 MCLGET(m, M_DONTWAIT); 1354 if ((m->m_flags & M_EXT) == 0) { 1355 *mp = m; 1356 m_freem(top); 1357 safestats.st_nomcl++; 1358 err = sc->sc_nqchip ? 1359 ERESTART : ENOMEM; 1360 goto errout; 1361 } 1362 len = MCLBYTES; 1363 } 1364 m->m_len = len = min(totlen, len); 1365 totlen -= len; 1366 *mp = m; 1367 mp = &m->m_next; 1368 } 1369 re->re_dst_m = top; 1370 if (bus_dmamap_create(sc->sc_dstdmat, 1371 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1372 safestats.st_nomap++; 1373 err = ENOMEM; 1374 goto errout; 1375 } 1376 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1377 re->re_dst_map, re->re_dst_m, 1378 safe_op_cb, &re->re_dst, 1379 BUS_DMA_NOWAIT) != 0) { 1380 bus_dmamap_destroy(sc->sc_dstdmat, 1381 re->re_dst_map); 1382 re->re_dst_map = NULL; 1383 safestats.st_noload++; 1384 err = ENOMEM; 1385 goto errout; 1386 } 1387 if (re->re_src.mapsize > oplen) { 1388 /* 1389 * There's data following what the 1390 * hardware will copy for us. If this 1391 * isn't just the ICV (that's going to 1392 * be written on completion), copy it 1393 * to the new mbufs 1394 */ 1395 if (!(maccrd && 1396 (re->re_src.mapsize-oplen) == 12 && 1397 maccrd->crd_inject == oplen)) 1398 safe_mcopy(re->re_src_m, 1399 re->re_dst_m, 1400 oplen); 1401 else 1402 safestats.st_noicvcopy++; 1403 } 1404 } 1405 } else { 1406 safestats.st_badflags++; 1407 err = EINVAL; 1408 goto errout; 1409 } 1410 1411 if (re->re_dst.nsegs > 1) { 1412 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1413 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1414 for (i = 0; i < re->re_dst_nsegs; i++) { 1415 pd = sc->sc_dpfree; 1416 KASSERT((pd->pd_flags&3) == 0 || 1417 (pd->pd_flags&3) == SAFE_PD_DONE, 1418 ("bogus dest particle descriptor; flags %x", 1419 pd->pd_flags)); 1420 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1421 sc->sc_dpfree = sc->sc_dpring; 1422 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1423 pd->pd_flags = SAFE_PD_READY; 1424 } 1425 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1426 } else { 1427 /* 1428 * No need for scatter, reference the operand directly. 1429 */ 1430 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1431 } 1432 } 1433 1434 /* 1435 * All done with setup; fillin the SA command words 1436 * and the packet engine descriptor. The operation 1437 * is now ready for submission to the hardware. 1438 */ 1439 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1440 sa->sa_cmd1 = cmd1 1441 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1442 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1443 | SAFE_SA_CMD1_SRPCI 1444 ; 1445 /* 1446 * NB: the order of writes is important here. In case the 1447 * chip is scanning the ring because of an outstanding request 1448 * it might nab this one too. In that case we need to make 1449 * sure the setup is complete before we write the length 1450 * field of the descriptor as it signals the descriptor is 1451 * ready for processing. 1452 */ 1453 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1454 if (maccrd) 1455 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1456 re->re_desc.d_len = oplen 1457 | SAFE_PE_LEN_READY 1458 | (bypass << SAFE_PE_LEN_BYPASS_S) 1459 ; 1460 1461 safestats.st_ipackets++; 1462 safestats.st_ibytes += oplen; 1463 1464 if (++(sc->sc_front) == sc->sc_ringtop) 1465 sc->sc_front = sc->sc_ring; 1466 1467 /* XXX honor batching */ 1468 safe_feed(sc, re); 1469 mtx_unlock(&sc->sc_ringmtx); 1470 return (0); 1471 1472 errout: 1473 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1474 m_freem(re->re_dst_m); 1475 1476 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1477 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1478 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1479 } 1480 if (re->re_src_map != NULL) { 1481 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1482 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1483 } 1484 mtx_unlock(&sc->sc_ringmtx); 1485 if (err != ERESTART) { 1486 crp->crp_etype = err; 1487 crypto_done(crp); 1488 } else { 1489 sc->sc_needwakeup |= CRYPTO_SYMQ; 1490 } 1491 return (err); 1492 } 1493 1494 static void 1495 safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1496 { 1497 struct cryptop *crp = (struct cryptop *)re->re_crp; 1498 struct cryptodesc *crd; 1499 1500 safestats.st_opackets++; 1501 safestats.st_obytes += re->re_dst.mapsize; 1502 1503 safe_dma_sync(&sc->sc_ringalloc, 1504 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1505 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1506 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1507 re->re_desc.d_csr, 1508 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1509 safestats.st_peoperr++; 1510 crp->crp_etype = EIO; /* something more meaningful? */ 1511 } 1512 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1513 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1514 BUS_DMASYNC_POSTREAD); 1515 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1516 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1517 } 1518 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1519 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1520 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1521 1522 /* 1523 * If result was written to a differet mbuf chain, swap 1524 * it in as the return value and reclaim the original. 1525 */ 1526 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1527 m_freem(re->re_src_m); 1528 crp->crp_buf = (caddr_t)re->re_dst_m; 1529 } 1530 1531 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1532 /* copy out IV for future use */ 1533 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1534 int ivsize; 1535 1536 if (crd->crd_alg == CRYPTO_DES_CBC || 1537 crd->crd_alg == CRYPTO_3DES_CBC) { 1538 ivsize = 2*sizeof(u_int32_t); 1539 } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1540 ivsize = 4*sizeof(u_int32_t); 1541 } else 1542 continue; 1543 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1544 m_copydata((struct mbuf *)crp->crp_buf, 1545 crd->crd_skip + crd->crd_len - ivsize, 1546 ivsize, 1547 (caddr_t) sc->sc_sessions[re->re_sesn].ses_iv); 1548 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1549 cuio_copydata((struct uio *)crp->crp_buf, 1550 crd->crd_skip + crd->crd_len - ivsize, 1551 ivsize, 1552 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1553 } 1554 break; 1555 } 1556 } 1557 1558 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1559 /* copy out ICV result */ 1560 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1561 if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1562 crd->crd_alg == CRYPTO_SHA1_HMAC || 1563 crd->crd_alg == CRYPTO_NULL_HMAC)) 1564 continue; 1565 if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1566 /* 1567 * SHA-1 ICV's are byte-swapped; fix 'em up 1568 * before copy them to their destination. 1569 */ 1570 bswap32(re->re_sastate.sa_saved_indigest[0]); 1571 bswap32(re->re_sastate.sa_saved_indigest[1]); 1572 bswap32(re->re_sastate.sa_saved_indigest[2]); 1573 } 1574 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1575 m_copyback((struct mbuf *)crp->crp_buf, 1576 crd->crd_inject, 12, 1577 (caddr_t)re->re_sastate.sa_saved_indigest); 1578 } else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) { 1579 bcopy((caddr_t)re->re_sastate.sa_saved_indigest, 1580 crp->crp_mac, 12); 1581 } 1582 break; 1583 } 1584 } 1585 crypto_done(crp); 1586 } 1587 1588 /* 1589 * Copy all data past offset from srcm to dstm. 1590 */ 1591 static void 1592 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1593 { 1594 u_int j, dlen, slen; 1595 caddr_t dptr, sptr; 1596 1597 /* 1598 * Advance src and dst to offset. 1599 */ 1600 j = offset; 1601 while (j >= 0) { 1602 if (srcm->m_len > j) 1603 break; 1604 j -= srcm->m_len; 1605 srcm = srcm->m_next; 1606 if (srcm == NULL) 1607 return; 1608 } 1609 sptr = mtod(srcm, caddr_t) + j; 1610 slen = srcm->m_len - j; 1611 1612 j = offset; 1613 while (j >= 0) { 1614 if (dstm->m_len > j) 1615 break; 1616 j -= dstm->m_len; 1617 dstm = dstm->m_next; 1618 if (dstm == NULL) 1619 return; 1620 } 1621 dptr = mtod(dstm, caddr_t) + j; 1622 dlen = dstm->m_len - j; 1623 1624 /* 1625 * Copy everything that remains. 1626 */ 1627 for (;;) { 1628 j = min(slen, dlen); 1629 bcopy(sptr, dptr, j); 1630 if (slen == j) { 1631 srcm = srcm->m_next; 1632 if (srcm == NULL) 1633 return; 1634 sptr = srcm->m_data; 1635 slen = srcm->m_len; 1636 } else 1637 sptr += j, slen -= j; 1638 if (dlen == j) { 1639 dstm = dstm->m_next; 1640 if (dstm == NULL) 1641 return; 1642 dptr = dstm->m_data; 1643 dlen = dstm->m_len; 1644 } else 1645 dptr += j, dlen -= j; 1646 } 1647 } 1648 1649 #ifndef SAFE_NO_RNG 1650 #define SAFE_RNG_MAXWAIT 1000 1651 1652 static void 1653 safe_rng_init(struct safe_softc *sc) 1654 { 1655 u_int32_t w, v; 1656 int i; 1657 1658 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1659 /* use default value according to the manual */ 1660 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1661 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1662 1663 /* 1664 * There is a bug in rev 1.0 of the 1140 that when the RNG 1665 * is brought out of reset the ready status flag does not 1666 * work until the RNG has finished its internal initialization. 1667 * 1668 * So in order to determine the device is through its 1669 * initialization we must read the data register, using the 1670 * status reg in the read in case it is initialized. Then read 1671 * the data register until it changes from the first read. 1672 * Once it changes read the data register until it changes 1673 * again. At this time the RNG is considered initialized. 1674 * This could take between 750ms - 1000ms in time. 1675 */ 1676 i = 0; 1677 w = READ_REG(sc, SAFE_RNG_OUT); 1678 do { 1679 v = READ_REG(sc, SAFE_RNG_OUT); 1680 if (v != w) { 1681 w = v; 1682 break; 1683 } 1684 DELAY(10); 1685 } while (++i < SAFE_RNG_MAXWAIT); 1686 1687 /* Wait Until data changes again */ 1688 i = 0; 1689 do { 1690 v = READ_REG(sc, SAFE_RNG_OUT); 1691 if (v != w) 1692 break; 1693 DELAY(10); 1694 } while (++i < SAFE_RNG_MAXWAIT); 1695 } 1696 1697 static __inline void 1698 safe_rng_disable_short_cycle(struct safe_softc *sc) 1699 { 1700 WRITE_REG(sc, SAFE_RNG_CTRL, 1701 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1702 } 1703 1704 static __inline void 1705 safe_rng_enable_short_cycle(struct safe_softc *sc) 1706 { 1707 WRITE_REG(sc, SAFE_RNG_CTRL, 1708 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1709 } 1710 1711 static __inline u_int32_t 1712 safe_rng_read(struct safe_softc *sc) 1713 { 1714 int i; 1715 1716 i = 0; 1717 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1718 ; 1719 return READ_REG(sc, SAFE_RNG_OUT); 1720 } 1721 1722 static void 1723 safe_rng(void *arg) 1724 { 1725 struct safe_softc *sc = arg; 1726 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1727 u_int maxwords; 1728 int i; 1729 1730 safestats.st_rng++; 1731 /* 1732 * Fetch the next block of data. 1733 */ 1734 maxwords = safe_rngbufsize; 1735 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1736 maxwords = SAFE_RNG_MAXBUFSIZ; 1737 retry: 1738 for (i = 0; i < maxwords; i++) 1739 buf[i] = safe_rng_read(sc); 1740 /* 1741 * Check the comparator alarm count and reset the h/w if 1742 * it exceeds our threshold. This guards against the 1743 * hardware oscillators resonating with external signals. 1744 */ 1745 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1746 u_int32_t freq_inc, w; 1747 1748 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1749 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1750 safestats.st_rngalarm++; 1751 safe_rng_enable_short_cycle(sc); 1752 freq_inc = 18; 1753 for (i = 0; i < 64; i++) { 1754 w = READ_REG(sc, SAFE_RNG_CNFG); 1755 freq_inc = ((w + freq_inc) & 0x3fL); 1756 w = ((w & ~0x3fL) | freq_inc); 1757 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1758 1759 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1760 1761 (void) safe_rng_read(sc); 1762 DELAY(25); 1763 1764 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1765 safe_rng_disable_short_cycle(sc); 1766 goto retry; 1767 } 1768 freq_inc = 1; 1769 } 1770 safe_rng_disable_short_cycle(sc); 1771 } else 1772 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1773 1774 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1775 callout_reset(&sc->sc_rngto, 1776 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1777 } 1778 #endif /* SAFE_NO_RNG */ 1779 1780 static void 1781 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1782 { 1783 bus_addr_t *paddr = (bus_addr_t*) arg; 1784 *paddr = segs->ds_addr; 1785 } 1786 1787 static int 1788 safe_dma_malloc( 1789 struct safe_softc *sc, 1790 bus_size_t size, 1791 struct safe_dma_alloc *dma, 1792 int mapflags 1793 ) 1794 { 1795 int r; 1796 1797 r = bus_dma_tag_create(NULL, /* parent */ 1798 sizeof(u_int32_t), 0, /* alignment, bounds */ 1799 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1800 BUS_SPACE_MAXADDR, /* highaddr */ 1801 NULL, NULL, /* filter, filterarg */ 1802 size, /* maxsize */ 1803 1, /* nsegments */ 1804 size, /* maxsegsize */ 1805 BUS_DMA_ALLOCNOW, /* flags */ 1806 NULL, NULL, /* locking */ 1807 &dma->dma_tag); 1808 if (r != 0) { 1809 device_printf(sc->sc_dev, "safe_dma_malloc: " 1810 "bus_dma_tag_create failed; error %u\n", r); 1811 goto fail_0; 1812 } 1813 1814 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1815 if (r != 0) { 1816 device_printf(sc->sc_dev, "safe_dma_malloc: " 1817 "bus_dmamap_create failed; error %u\n", r); 1818 goto fail_1; 1819 } 1820 1821 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1822 BUS_DMA_NOWAIT, &dma->dma_map); 1823 if (r != 0) { 1824 device_printf(sc->sc_dev, "safe_dma_malloc: " 1825 "bus_dmammem_alloc failed; size %zu, error %u\n", 1826 size, r); 1827 goto fail_2; 1828 } 1829 1830 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1831 size, 1832 safe_dmamap_cb, 1833 &dma->dma_paddr, 1834 mapflags | BUS_DMA_NOWAIT); 1835 if (r != 0) { 1836 device_printf(sc->sc_dev, "safe_dma_malloc: " 1837 "bus_dmamap_load failed; error %u\n", r); 1838 goto fail_3; 1839 } 1840 1841 dma->dma_size = size; 1842 return (0); 1843 1844 fail_3: 1845 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1846 fail_2: 1847 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1848 fail_1: 1849 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1850 bus_dma_tag_destroy(dma->dma_tag); 1851 fail_0: 1852 dma->dma_map = NULL; 1853 dma->dma_tag = NULL; 1854 return (r); 1855 } 1856 1857 static void 1858 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1859 { 1860 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1861 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1862 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1863 bus_dma_tag_destroy(dma->dma_tag); 1864 } 1865 1866 /* 1867 * Resets the board. Values in the regesters are left as is 1868 * from the reset (i.e. initial values are assigned elsewhere). 1869 */ 1870 static void 1871 safe_reset_board(struct safe_softc *sc) 1872 { 1873 u_int32_t v; 1874 /* 1875 * Reset the device. The manual says no delay 1876 * is needed between marking and clearing reset. 1877 */ 1878 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1879 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1880 SAFE_PE_DMACFG_SGRESET); 1881 WRITE_REG(sc, SAFE_PE_DMACFG, v 1882 | SAFE_PE_DMACFG_PERESET 1883 | SAFE_PE_DMACFG_PDRRESET 1884 | SAFE_PE_DMACFG_SGRESET); 1885 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1886 } 1887 1888 /* 1889 * Initialize registers we need to touch only once. 1890 */ 1891 static void 1892 safe_init_board(struct safe_softc *sc) 1893 { 1894 u_int32_t v, dwords; 1895 1896 v = READ_REG(sc, SAFE_PE_DMACFG);; 1897 v &=~ SAFE_PE_DMACFG_PEMODE; 1898 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1899 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1900 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1901 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1902 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1903 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1904 ; 1905 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1906 #if 0 1907 /* XXX select byte swap based on host byte order */ 1908 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1909 #endif 1910 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1911 /* 1912 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1913 * "target mode transfers" done while the chip is DMA'ing 1914 * >1020 bytes cause the hardware to lockup. To avoid this 1915 * we reduce the max PCI transfer size and use small source 1916 * particle descriptors (<= 256 bytes). 1917 */ 1918 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1919 device_printf(sc->sc_dev, 1920 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1921 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1922 SAFE_REV_MAJ(sc->sc_chiprev), 1923 SAFE_REV_MIN(sc->sc_chiprev)); 1924 } 1925 1926 /* NB: operands+results are overlaid */ 1927 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1928 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1929 /* 1930 * Configure ring entry size and number of items in the ring. 1931 */ 1932 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1933 ("PE ring entry not 32-bit aligned!")); 1934 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1935 WRITE_REG(sc, SAFE_PE_RINGCFG, 1936 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1937 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1938 1939 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1940 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1941 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1942 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1943 /* 1944 * NB: destination particles are fixed size. We use 1945 * an mbuf cluster and require all results go to 1946 * clusters or smaller. 1947 */ 1948 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1949 1950 /* it's now safe to enable PE mode, do it */ 1951 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1952 1953 /* 1954 * Configure hardware to use level-triggered interrupts and 1955 * to interrupt after each descriptor is processed. 1956 */ 1957 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1958 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1959 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1960 } 1961 1962 /* 1963 * Init PCI registers 1964 */ 1965 static void 1966 safe_init_pciregs(device_t dev) 1967 { 1968 } 1969 1970 /* 1971 * Clean up after a chip crash. 1972 * It is assumed that the caller in splimp() 1973 */ 1974 static void 1975 safe_cleanchip(struct safe_softc *sc) 1976 { 1977 1978 if (sc->sc_nqchip != 0) { 1979 struct safe_ringentry *re = sc->sc_back; 1980 1981 while (re != sc->sc_front) { 1982 if (re->re_desc.d_csr != 0) 1983 safe_free_entry(sc, re); 1984 if (++re == sc->sc_ringtop) 1985 re = sc->sc_ring; 1986 } 1987 sc->sc_back = re; 1988 sc->sc_nqchip = 0; 1989 } 1990 } 1991 1992 /* 1993 * free a safe_q 1994 * It is assumed that the caller is within splimp(). 1995 */ 1996 static int 1997 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 1998 { 1999 struct cryptop *crp; 2000 2001 /* 2002 * Free header MCR 2003 */ 2004 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2005 m_freem(re->re_dst_m); 2006 2007 crp = (struct cryptop *)re->re_crp; 2008 2009 re->re_desc.d_csr = 0; 2010 2011 crp->crp_etype = EFAULT; 2012 crypto_done(crp); 2013 return(0); 2014 } 2015 2016 /* 2017 * Routine to reset the chip and clean up. 2018 * It is assumed that the caller is in splimp() 2019 */ 2020 static void 2021 safe_totalreset(struct safe_softc *sc) 2022 { 2023 safe_reset_board(sc); 2024 safe_init_board(sc); 2025 safe_cleanchip(sc); 2026 } 2027 2028 /* 2029 * Is the operand suitable aligned for direct DMA. Each 2030 * segment must be aligned on a 32-bit boundary and all 2031 * but the last segment must be a multiple of 4 bytes. 2032 */ 2033 static int 2034 safe_dmamap_aligned(const struct safe_operand *op) 2035 { 2036 int i; 2037 2038 for (i = 0; i < op->nsegs; i++) { 2039 if (op->segs[i].ds_addr & 3) 2040 return (0); 2041 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2042 return (0); 2043 } 2044 return (1); 2045 } 2046 2047 /* 2048 * Is the operand suitable for direct DMA as the destination 2049 * of an operation. The hardware requires that each ``particle'' 2050 * but the last in an operation result have the same size. We 2051 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2052 * 0 if some segment is not a multiple of of this size, 1 if all 2053 * segments are exactly this size, or 2 if segments are at worst 2054 * a multple of this size. 2055 */ 2056 static int 2057 safe_dmamap_uniform(const struct safe_operand *op) 2058 { 2059 int result = 1; 2060 2061 if (op->nsegs > 0) { 2062 int i; 2063 2064 for (i = 0; i < op->nsegs-1; i++) 2065 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2066 return (0); 2067 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2068 result = 2; 2069 } 2070 return (result); 2071 } 2072 2073 #ifdef SAFE_DEBUG 2074 static void 2075 safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2076 { 2077 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2078 , tag 2079 , READ_REG(sc, SAFE_DMA_ENDIAN) 2080 , READ_REG(sc, SAFE_DMA_SRCADDR) 2081 , READ_REG(sc, SAFE_DMA_DSTADDR) 2082 , READ_REG(sc, SAFE_DMA_STAT) 2083 ); 2084 } 2085 2086 static void 2087 safe_dump_intrstate(struct safe_softc *sc, const char *tag) 2088 { 2089 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2090 , tag 2091 , READ_REG(sc, SAFE_HI_CFG) 2092 , READ_REG(sc, SAFE_HI_MASK) 2093 , READ_REG(sc, SAFE_HI_DESC_CNT) 2094 , READ_REG(sc, SAFE_HU_STAT) 2095 , READ_REG(sc, SAFE_HM_STAT) 2096 ); 2097 } 2098 2099 static void 2100 safe_dump_ringstate(struct safe_softc *sc, const char *tag) 2101 { 2102 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2103 2104 /* NB: assume caller has lock on ring */ 2105 printf("%s: ERNGSTAT %x (next %u) back %u front %u\n", 2106 tag, 2107 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2108 sc->sc_back - sc->sc_ring, 2109 sc->sc_front - sc->sc_ring); 2110 } 2111 2112 static void 2113 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2114 { 2115 int ix, nsegs; 2116 2117 ix = re - sc->sc_ring; 2118 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2119 , tag 2120 , re, ix 2121 , re->re_desc.d_csr 2122 , re->re_desc.d_src 2123 , re->re_desc.d_dst 2124 , re->re_desc.d_sa 2125 , re->re_desc.d_len 2126 ); 2127 if (re->re_src.nsegs > 1) { 2128 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2129 sizeof(struct safe_pdesc); 2130 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2131 printf(" spd[%u] %p: %p size %u flags %x" 2132 , ix, &sc->sc_spring[ix] 2133 , (caddr_t) sc->sc_spring[ix].pd_addr 2134 , sc->sc_spring[ix].pd_size 2135 , sc->sc_spring[ix].pd_flags 2136 ); 2137 if (sc->sc_spring[ix].pd_size == 0) 2138 printf(" (zero!)"); 2139 printf("\n"); 2140 if (++ix == SAFE_TOTAL_SPART) 2141 ix = 0; 2142 } 2143 } 2144 if (re->re_dst.nsegs > 1) { 2145 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2146 sizeof(struct safe_pdesc); 2147 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2148 printf(" dpd[%u] %p: %p flags %x\n" 2149 , ix, &sc->sc_dpring[ix] 2150 , (caddr_t) sc->sc_dpring[ix].pd_addr 2151 , sc->sc_dpring[ix].pd_flags 2152 ); 2153 if (++ix == SAFE_TOTAL_DPART) 2154 ix = 0; 2155 } 2156 } 2157 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2158 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2159 printf("sa: key %x %x %x %x %x %x %x %x\n" 2160 , re->re_sa.sa_key[0] 2161 , re->re_sa.sa_key[1] 2162 , re->re_sa.sa_key[2] 2163 , re->re_sa.sa_key[3] 2164 , re->re_sa.sa_key[4] 2165 , re->re_sa.sa_key[5] 2166 , re->re_sa.sa_key[6] 2167 , re->re_sa.sa_key[7] 2168 ); 2169 printf("sa: indigest %x %x %x %x %x\n" 2170 , re->re_sa.sa_indigest[0] 2171 , re->re_sa.sa_indigest[1] 2172 , re->re_sa.sa_indigest[2] 2173 , re->re_sa.sa_indigest[3] 2174 , re->re_sa.sa_indigest[4] 2175 ); 2176 printf("sa: outdigest %x %x %x %x %x\n" 2177 , re->re_sa.sa_outdigest[0] 2178 , re->re_sa.sa_outdigest[1] 2179 , re->re_sa.sa_outdigest[2] 2180 , re->re_sa.sa_outdigest[3] 2181 , re->re_sa.sa_outdigest[4] 2182 ); 2183 printf("sr: iv %x %x %x %x\n" 2184 , re->re_sastate.sa_saved_iv[0] 2185 , re->re_sastate.sa_saved_iv[1] 2186 , re->re_sastate.sa_saved_iv[2] 2187 , re->re_sastate.sa_saved_iv[3] 2188 ); 2189 printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2190 , re->re_sastate.sa_saved_hashbc 2191 , re->re_sastate.sa_saved_indigest[0] 2192 , re->re_sastate.sa_saved_indigest[1] 2193 , re->re_sastate.sa_saved_indigest[2] 2194 , re->re_sastate.sa_saved_indigest[3] 2195 , re->re_sastate.sa_saved_indigest[4] 2196 ); 2197 } 2198 2199 static void 2200 safe_dump_ring(struct safe_softc *sc, const char *tag) 2201 { 2202 mtx_lock(&sc->sc_ringmtx); 2203 printf("\nSafeNet Ring State:\n"); 2204 safe_dump_intrstate(sc, tag); 2205 safe_dump_dmastatus(sc, tag); 2206 safe_dump_ringstate(sc, tag); 2207 if (sc->sc_nqchip) { 2208 struct safe_ringentry *re = sc->sc_back; 2209 do { 2210 safe_dump_request(sc, tag, re); 2211 if (++re == sc->sc_ringtop) 2212 re = sc->sc_ring; 2213 } while (re != sc->sc_front); 2214 } 2215 mtx_unlock(&sc->sc_ringmtx); 2216 } 2217 2218 static int 2219 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2220 { 2221 char dmode[64]; 2222 int error; 2223 2224 strncpy(dmode, "", sizeof(dmode) - 1); 2225 dmode[sizeof(dmode) - 1] = '\0'; 2226 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2227 2228 if (error == 0 && req->newptr != NULL) { 2229 struct safe_softc *sc = safec; 2230 2231 if (!sc) 2232 return EINVAL; 2233 if (strncmp(dmode, "dma", 3) == 0) 2234 safe_dump_dmastatus(sc, "safe0"); 2235 else if (strncmp(dmode, "int", 3) == 0) 2236 safe_dump_intrstate(sc, "safe0"); 2237 else if (strncmp(dmode, "ring", 4) == 0) 2238 safe_dump_ring(sc, "safe0"); 2239 else 2240 return EINVAL; 2241 } 2242 return error; 2243 } 2244 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2245 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2246 #endif /* SAFE_DEBUG */ 2247