1 /*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * SafeNet SafeXcel-1141 hardware crypto accelerator 33 */ 34 #include "opt_safe.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/proc.h> 39 #include <sys/errno.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/mbuf.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/sysctl.h> 47 #include <sys/endian.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 52 #include <machine/clock.h> 53 #include <machine/bus.h> 54 #include <machine/resource.h> 55 #include <sys/bus.h> 56 #include <sys/rman.h> 57 58 #include <crypto/sha1.h> 59 #include <opencrypto/cryptodev.h> 60 #include <opencrypto/cryptosoft.h> 61 #include <sys/md5.h> 62 #include <sys/random.h> 63 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 67 #ifdef SAFE_RNDTEST 68 #include <dev/rndtest/rndtest.h> 69 #endif 70 #include <dev/safe/safereg.h> 71 #include <dev/safe/safevar.h> 72 73 #ifndef bswap32 74 #define bswap32 NTOHL 75 #endif 76 77 /* 78 * Prototypes and count for the pci_device structure 79 */ 80 static int safe_probe(device_t); 81 static int safe_attach(device_t); 82 static int safe_detach(device_t); 83 static int safe_suspend(device_t); 84 static int safe_resume(device_t); 85 static void safe_shutdown(device_t); 86 87 static device_method_t safe_methods[] = { 88 /* Device interface */ 89 DEVMETHOD(device_probe, safe_probe), 90 DEVMETHOD(device_attach, safe_attach), 91 DEVMETHOD(device_detach, safe_detach), 92 DEVMETHOD(device_suspend, safe_suspend), 93 DEVMETHOD(device_resume, safe_resume), 94 DEVMETHOD(device_shutdown, safe_shutdown), 95 96 /* bus interface */ 97 DEVMETHOD(bus_print_child, bus_generic_print_child), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 100 { 0, 0 } 101 }; 102 static driver_t safe_driver = { 103 "safe", 104 safe_methods, 105 sizeof (struct safe_softc) 106 }; 107 static devclass_t safe_devclass; 108 109 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 110 MODULE_DEPEND(safe, crypto, 1, 1, 1); 111 #ifdef SAFE_RNDTEST 112 MODULE_DEPEND(safe, rndtest, 1, 1, 1); 113 #endif 114 115 static void safe_intr(void *); 116 static int safe_newsession(void *, u_int32_t *, struct cryptoini *); 117 static int safe_freesession(void *, u_int64_t); 118 static int safe_process(void *, struct cryptop *, int); 119 static void safe_callback(struct safe_softc *, struct safe_ringentry *); 120 static void safe_feed(struct safe_softc *, struct safe_ringentry *); 121 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 122 #ifndef SAFE_NO_RNG 123 static void safe_rng_init(struct safe_softc *); 124 static void safe_rng(void *); 125 #endif /* SAFE_NO_RNG */ 126 static int safe_dma_malloc(struct safe_softc *, bus_size_t, 127 struct safe_dma_alloc *, int); 128 #define safe_dma_sync(_dma, _flags) \ 129 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 130 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 131 static int safe_dmamap_aligned(const struct safe_operand *); 132 static int safe_dmamap_uniform(const struct safe_operand *); 133 134 static void safe_reset_board(struct safe_softc *); 135 static void safe_init_board(struct safe_softc *); 136 static void safe_init_pciregs(device_t dev); 137 static void safe_cleanchip(struct safe_softc *); 138 static void safe_totalreset(struct safe_softc *); 139 140 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 141 142 SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 143 144 #ifdef SAFE_DEBUG 145 static void safe_dump_dmastatus(struct safe_softc *, const char *); 146 static void safe_dump_ringstate(struct safe_softc *, const char *); 147 static void safe_dump_intrstate(struct safe_softc *, const char *); 148 static void safe_dump_request(struct safe_softc *, const char *, 149 struct safe_ringentry *); 150 151 static struct safe_softc *safec; /* for use by hw.safe.dump */ 152 153 static int safe_debug = 0; 154 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 155 0, "control debugging msgs"); 156 #define DPRINTF(_x) if (safe_debug) printf _x 157 #else 158 #define DPRINTF(_x) 159 #endif 160 161 #define READ_REG(sc,r) \ 162 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 163 164 #define WRITE_REG(sc,reg,val) \ 165 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 166 167 struct safe_stats safestats; 168 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 169 safe_stats, "driver statistics"); 170 #ifndef SAFE_NO_RNG 171 static int safe_rnginterval = 1; /* poll once a second */ 172 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 173 0, "RNG polling interval (secs)"); 174 static int safe_rngbufsize = 16; /* 64 bytes each poll */ 175 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 176 0, "RNG polling buffer size (32-bit words)"); 177 static int safe_rngmaxalarm = 8; /* max alarms before reset */ 178 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 179 0, "RNG max alarms before reset"); 180 #endif /* SAFE_NO_RNG */ 181 182 static int 183 safe_probe(device_t dev) 184 { 185 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 186 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 187 return (BUS_PROBE_DEFAULT); 188 return (ENXIO); 189 } 190 191 static const char* 192 safe_partname(struct safe_softc *sc) 193 { 194 /* XXX sprintf numbers when not decoded */ 195 switch (pci_get_vendor(sc->sc_dev)) { 196 case PCI_VENDOR_SAFENET: 197 switch (pci_get_device(sc->sc_dev)) { 198 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 199 } 200 return "SafeNet unknown-part"; 201 } 202 return "Unknown-vendor unknown-part"; 203 } 204 205 #ifndef SAFE_NO_RNG 206 static void 207 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 208 { 209 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 210 } 211 #endif /* SAFE_NO_RNG */ 212 213 static int 214 safe_attach(device_t dev) 215 { 216 struct safe_softc *sc = device_get_softc(dev); 217 u_int32_t raddr; 218 u_int32_t cmd, i, devinfo; 219 int rid; 220 221 bzero(sc, sizeof (*sc)); 222 sc->sc_dev = dev; 223 224 /* XXX handle power management */ 225 226 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 227 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 228 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 229 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 230 231 if (!(cmd & PCIM_CMD_MEMEN)) { 232 device_printf(dev, "failed to enable memory mapping\n"); 233 goto bad; 234 } 235 236 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 237 device_printf(dev, "failed to enable bus mastering\n"); 238 goto bad; 239 } 240 241 /* 242 * Setup memory-mapping of PCI registers. 243 */ 244 rid = BS_BAR; 245 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 246 RF_ACTIVE); 247 if (sc->sc_sr == NULL) { 248 device_printf(dev, "cannot map register space\n"); 249 goto bad; 250 } 251 sc->sc_st = rman_get_bustag(sc->sc_sr); 252 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 253 254 /* 255 * Arrange interrupt line. 256 */ 257 rid = 0; 258 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 259 RF_SHAREABLE|RF_ACTIVE); 260 if (sc->sc_irq == NULL) { 261 device_printf(dev, "could not map interrupt\n"); 262 goto bad1; 263 } 264 /* 265 * NB: Network code assumes we are blocked with splimp() 266 * so make sure the IRQ is mapped appropriately. 267 */ 268 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 269 safe_intr, sc, &sc->sc_ih)) { 270 device_printf(dev, "could not establish interrupt\n"); 271 goto bad2; 272 } 273 274 sc->sc_cid = crypto_get_driverid(0); 275 if (sc->sc_cid < 0) { 276 device_printf(dev, "could not get crypto driver id\n"); 277 goto bad3; 278 } 279 280 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 281 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 282 283 /* 284 * Setup DMA descriptor area. 285 */ 286 if (bus_dma_tag_create(NULL, /* parent */ 287 1, /* alignment */ 288 SAFE_DMA_BOUNDARY, /* boundary */ 289 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 290 BUS_SPACE_MAXADDR, /* highaddr */ 291 NULL, NULL, /* filter, filterarg */ 292 SAFE_MAX_DMA, /* maxsize */ 293 SAFE_MAX_PART, /* nsegments */ 294 SAFE_MAX_SSIZE, /* maxsegsize */ 295 BUS_DMA_ALLOCNOW, /* flags */ 296 NULL, NULL, /* locking */ 297 &sc->sc_srcdmat)) { 298 device_printf(dev, "cannot allocate DMA tag\n"); 299 goto bad4; 300 } 301 if (bus_dma_tag_create(NULL, /* parent */ 302 sizeof(u_int32_t), /* alignment */ 303 SAFE_MAX_DSIZE, /* boundary */ 304 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 305 BUS_SPACE_MAXADDR, /* highaddr */ 306 NULL, NULL, /* filter, filterarg */ 307 SAFE_MAX_DMA, /* maxsize */ 308 SAFE_MAX_PART, /* nsegments */ 309 SAFE_MAX_DSIZE, /* maxsegsize */ 310 BUS_DMA_ALLOCNOW, /* flags */ 311 NULL, NULL, /* locking */ 312 &sc->sc_dstdmat)) { 313 device_printf(dev, "cannot allocate DMA tag\n"); 314 goto bad4; 315 } 316 317 /* 318 * Allocate packet engine descriptors. 319 */ 320 if (safe_dma_malloc(sc, 321 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 322 &sc->sc_ringalloc, 0)) { 323 device_printf(dev, "cannot allocate PE descriptor ring\n"); 324 bus_dma_tag_destroy(sc->sc_srcdmat); 325 goto bad4; 326 } 327 /* 328 * Hookup the static portion of all our data structures. 329 */ 330 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 331 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 332 sc->sc_front = sc->sc_ring; 333 sc->sc_back = sc->sc_ring; 334 raddr = sc->sc_ringalloc.dma_paddr; 335 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 336 for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 337 struct safe_ringentry *re = &sc->sc_ring[i]; 338 339 re->re_desc.d_sa = raddr + 340 offsetof(struct safe_ringentry, re_sa); 341 re->re_sa.sa_staterec = raddr + 342 offsetof(struct safe_ringentry, re_sastate); 343 344 raddr += sizeof (struct safe_ringentry); 345 } 346 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 347 "packet engine ring", MTX_DEF); 348 349 /* 350 * Allocate scatter and gather particle descriptors. 351 */ 352 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 353 &sc->sc_spalloc, 0)) { 354 device_printf(dev, "cannot allocate source particle " 355 "descriptor ring\n"); 356 mtx_destroy(&sc->sc_ringmtx); 357 safe_dma_free(sc, &sc->sc_ringalloc); 358 bus_dma_tag_destroy(sc->sc_srcdmat); 359 goto bad4; 360 } 361 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 362 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 363 sc->sc_spfree = sc->sc_spring; 364 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 365 366 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 367 &sc->sc_dpalloc, 0)) { 368 device_printf(dev, "cannot allocate destination particle " 369 "descriptor ring\n"); 370 mtx_destroy(&sc->sc_ringmtx); 371 safe_dma_free(sc, &sc->sc_spalloc); 372 safe_dma_free(sc, &sc->sc_ringalloc); 373 bus_dma_tag_destroy(sc->sc_dstdmat); 374 goto bad4; 375 } 376 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 377 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 378 sc->sc_dpfree = sc->sc_dpring; 379 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 380 381 device_printf(sc->sc_dev, "%s", safe_partname(sc)); 382 383 devinfo = READ_REG(sc, SAFE_DEVINFO); 384 if (devinfo & SAFE_DEVINFO_RNG) { 385 sc->sc_flags |= SAFE_FLAGS_RNG; 386 printf(" rng"); 387 } 388 if (devinfo & SAFE_DEVINFO_PKEY) { 389 #if 0 390 printf(" key"); 391 sc->sc_flags |= SAFE_FLAGS_KEY; 392 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 393 safe_kprocess, sc); 394 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 395 safe_kprocess, sc); 396 #endif 397 } 398 if (devinfo & SAFE_DEVINFO_DES) { 399 printf(" des/3des"); 400 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 401 safe_newsession, safe_freesession, safe_process, sc); 402 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 403 safe_newsession, safe_freesession, safe_process, sc); 404 } 405 if (devinfo & SAFE_DEVINFO_AES) { 406 printf(" aes"); 407 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0, 408 safe_newsession, safe_freesession, safe_process, sc); 409 } 410 if (devinfo & SAFE_DEVINFO_MD5) { 411 printf(" md5"); 412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 413 safe_newsession, safe_freesession, safe_process, sc); 414 } 415 if (devinfo & SAFE_DEVINFO_SHA1) { 416 printf(" sha1"); 417 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 418 safe_newsession, safe_freesession, safe_process, sc); 419 } 420 printf(" null"); 421 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0, 422 safe_newsession, safe_freesession, safe_process, sc); 423 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0, 424 safe_newsession, safe_freesession, safe_process, sc); 425 /* XXX other supported algorithms */ 426 printf("\n"); 427 428 safe_reset_board(sc); /* reset h/w */ 429 safe_init_pciregs(dev); /* init pci settings */ 430 safe_init_board(sc); /* init h/w */ 431 432 #ifndef SAFE_NO_RNG 433 if (sc->sc_flags & SAFE_FLAGS_RNG) { 434 #ifdef SAFE_RNDTEST 435 sc->sc_rndtest = rndtest_attach(dev); 436 if (sc->sc_rndtest) 437 sc->sc_harvest = rndtest_harvest; 438 else 439 sc->sc_harvest = default_harvest; 440 #else 441 sc->sc_harvest = default_harvest; 442 #endif 443 safe_rng_init(sc); 444 445 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 446 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 447 } 448 #endif /* SAFE_NO_RNG */ 449 #ifdef SAFE_DEBUG 450 safec = sc; /* for use by hw.safe.dump */ 451 #endif 452 return (0); 453 bad4: 454 crypto_unregister_all(sc->sc_cid); 455 bad3: 456 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 457 bad2: 458 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 459 bad1: 460 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 461 bad: 462 return (ENXIO); 463 } 464 465 /* 466 * Detach a device that successfully probed. 467 */ 468 static int 469 safe_detach(device_t dev) 470 { 471 struct safe_softc *sc = device_get_softc(dev); 472 473 /* XXX wait/abort active ops */ 474 475 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 476 477 callout_stop(&sc->sc_rngto); 478 479 crypto_unregister_all(sc->sc_cid); 480 481 #ifdef SAFE_RNDTEST 482 if (sc->sc_rndtest) 483 rndtest_detach(sc->sc_rndtest); 484 #endif 485 486 safe_cleanchip(sc); 487 safe_dma_free(sc, &sc->sc_dpalloc); 488 safe_dma_free(sc, &sc->sc_spalloc); 489 mtx_destroy(&sc->sc_ringmtx); 490 safe_dma_free(sc, &sc->sc_ringalloc); 491 492 bus_generic_detach(dev); 493 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 494 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 495 496 bus_dma_tag_destroy(sc->sc_srcdmat); 497 bus_dma_tag_destroy(sc->sc_dstdmat); 498 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 499 500 return (0); 501 } 502 503 /* 504 * Stop all chip i/o so that the kernel's probe routines don't 505 * get confused by errant DMAs when rebooting. 506 */ 507 static void 508 safe_shutdown(device_t dev) 509 { 510 #ifdef notyet 511 safe_stop(device_get_softc(dev)); 512 #endif 513 } 514 515 /* 516 * Device suspend routine. 517 */ 518 static int 519 safe_suspend(device_t dev) 520 { 521 struct safe_softc *sc = device_get_softc(dev); 522 523 #ifdef notyet 524 /* XXX stop the device and save PCI settings */ 525 #endif 526 sc->sc_suspended = 1; 527 528 return (0); 529 } 530 531 static int 532 safe_resume(device_t dev) 533 { 534 struct safe_softc *sc = device_get_softc(dev); 535 536 #ifdef notyet 537 /* XXX retore PCI settings and start the device */ 538 #endif 539 sc->sc_suspended = 0; 540 return (0); 541 } 542 543 /* 544 * SafeXcel Interrupt routine 545 */ 546 static void 547 safe_intr(void *arg) 548 { 549 struct safe_softc *sc = arg; 550 volatile u_int32_t stat; 551 552 stat = READ_REG(sc, SAFE_HM_STAT); 553 if (stat == 0) /* shared irq, not for us */ 554 return; 555 556 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 557 558 if ((stat & SAFE_INT_PE_DDONE)) { 559 /* 560 * Descriptor(s) done; scan the ring and 561 * process completed operations. 562 */ 563 mtx_lock(&sc->sc_ringmtx); 564 while (sc->sc_back != sc->sc_front) { 565 struct safe_ringentry *re = sc->sc_back; 566 #ifdef SAFE_DEBUG 567 if (safe_debug) { 568 safe_dump_ringstate(sc, __func__); 569 safe_dump_request(sc, __func__, re); 570 } 571 #endif 572 /* 573 * safe_process marks ring entries that were allocated 574 * but not used with a csr of zero. This insures the 575 * ring front pointer never needs to be set backwards 576 * in the event that an entry is allocated but not used 577 * because of a setup error. 578 */ 579 if (re->re_desc.d_csr != 0) { 580 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 581 break; 582 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 583 break; 584 sc->sc_nqchip--; 585 safe_callback(sc, re); 586 } 587 if (++(sc->sc_back) == sc->sc_ringtop) 588 sc->sc_back = sc->sc_ring; 589 } 590 mtx_unlock(&sc->sc_ringmtx); 591 } 592 593 /* 594 * Check to see if we got any DMA Error 595 */ 596 if (stat & SAFE_INT_PE_ERROR) { 597 DPRINTF(("dmaerr dmastat %08x\n", 598 READ_REG(sc, SAFE_PE_DMASTAT))); 599 safestats.st_dmaerr++; 600 safe_totalreset(sc); 601 #if 0 602 safe_feed(sc); 603 #endif 604 } 605 606 if (sc->sc_needwakeup) { /* XXX check high watermark */ 607 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 608 DPRINTF(("%s: wakeup crypto %x\n", __func__, 609 sc->sc_needwakeup)); 610 sc->sc_needwakeup &= ~wakeup; 611 crypto_unblock(sc->sc_cid, wakeup); 612 } 613 } 614 615 /* 616 * safe_feed() - post a request to chip 617 */ 618 static void 619 safe_feed(struct safe_softc *sc, struct safe_ringentry *re) 620 { 621 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 622 if (re->re_dst_map != NULL) 623 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 624 BUS_DMASYNC_PREREAD); 625 /* XXX have no smaller granularity */ 626 safe_dma_sync(&sc->sc_ringalloc, 627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 628 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 629 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 630 631 #ifdef SAFE_DEBUG 632 if (safe_debug) { 633 safe_dump_ringstate(sc, __func__); 634 safe_dump_request(sc, __func__, re); 635 } 636 #endif 637 sc->sc_nqchip++; 638 if (sc->sc_nqchip > safestats.st_maxqchip) 639 safestats.st_maxqchip = sc->sc_nqchip; 640 /* poke h/w to check descriptor ring, any value can be written */ 641 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 642 } 643 644 /* 645 * Allocate a new 'session' and return an encoded session id. 'sidp' 646 * contains our registration id, and should contain an encoded session 647 * id on successful allocation. 648 */ 649 static int 650 safe_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 651 { 652 #define N(a) (sizeof(a) / sizeof (a[0])) 653 struct cryptoini *c, *encini = NULL, *macini = NULL; 654 struct safe_softc *sc = arg; 655 struct safe_session *ses = NULL; 656 MD5_CTX md5ctx; 657 SHA1_CTX sha1ctx; 658 int i, sesn; 659 660 if (sidp == NULL || cri == NULL || sc == NULL) 661 return (EINVAL); 662 663 for (c = cri; c != NULL; c = c->cri_next) { 664 if (c->cri_alg == CRYPTO_MD5_HMAC || 665 c->cri_alg == CRYPTO_SHA1_HMAC || 666 c->cri_alg == CRYPTO_NULL_HMAC) { 667 if (macini) 668 return (EINVAL); 669 macini = c; 670 } else if (c->cri_alg == CRYPTO_DES_CBC || 671 c->cri_alg == CRYPTO_3DES_CBC || 672 c->cri_alg == CRYPTO_AES_CBC || 673 c->cri_alg == CRYPTO_NULL_CBC) { 674 if (encini) 675 return (EINVAL); 676 encini = c; 677 } else 678 return (EINVAL); 679 } 680 if (encini == NULL && macini == NULL) 681 return (EINVAL); 682 if (encini) { /* validate key length */ 683 switch (encini->cri_alg) { 684 case CRYPTO_DES_CBC: 685 if (encini->cri_klen != 64) 686 return (EINVAL); 687 break; 688 case CRYPTO_3DES_CBC: 689 if (encini->cri_klen != 192) 690 return (EINVAL); 691 break; 692 case CRYPTO_AES_CBC: 693 if (encini->cri_klen != 128 && 694 encini->cri_klen != 192 && 695 encini->cri_klen != 256) 696 return (EINVAL); 697 break; 698 } 699 } 700 701 if (sc->sc_sessions == NULL) { 702 ses = sc->sc_sessions = (struct safe_session *)malloc( 703 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 704 if (ses == NULL) 705 return (ENOMEM); 706 sesn = 0; 707 sc->sc_nsessions = 1; 708 } else { 709 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 710 if (sc->sc_sessions[sesn].ses_used == 0) { 711 ses = &sc->sc_sessions[sesn]; 712 break; 713 } 714 } 715 716 if (ses == NULL) { 717 sesn = sc->sc_nsessions; 718 ses = (struct safe_session *)malloc((sesn + 1) * 719 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 720 if (ses == NULL) 721 return (ENOMEM); 722 bcopy(sc->sc_sessions, ses, sesn * 723 sizeof(struct safe_session)); 724 bzero(sc->sc_sessions, sesn * 725 sizeof(struct safe_session)); 726 free(sc->sc_sessions, M_DEVBUF); 727 sc->sc_sessions = ses; 728 ses = &sc->sc_sessions[sesn]; 729 sc->sc_nsessions++; 730 } 731 } 732 733 bzero(ses, sizeof(struct safe_session)); 734 ses->ses_used = 1; 735 736 if (encini) { 737 /* get an IV */ 738 /* XXX may read fewer than requested */ 739 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 740 741 ses->ses_klen = encini->cri_klen; 742 bcopy(encini->cri_key, ses->ses_key, ses->ses_klen / 8); 743 744 /* PE is little-endian, insure proper byte order */ 745 for (i = 0; i < N(ses->ses_key); i++) 746 ses->ses_key[i] = htole32(ses->ses_key[i]); 747 } 748 749 if (macini) { 750 for (i = 0; i < macini->cri_klen / 8; i++) 751 macini->cri_key[i] ^= HMAC_IPAD_VAL; 752 753 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 754 MD5Init(&md5ctx); 755 MD5Update(&md5ctx, macini->cri_key, 756 macini->cri_klen / 8); 757 MD5Update(&md5ctx, hmac_ipad_buffer, 758 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 759 bcopy(md5ctx.state, ses->ses_hminner, 760 sizeof(md5ctx.state)); 761 } else { 762 SHA1Init(&sha1ctx); 763 SHA1Update(&sha1ctx, macini->cri_key, 764 macini->cri_klen / 8); 765 SHA1Update(&sha1ctx, hmac_ipad_buffer, 766 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 767 bcopy(sha1ctx.h.b32, ses->ses_hminner, 768 sizeof(sha1ctx.h.b32)); 769 } 770 771 for (i = 0; i < macini->cri_klen / 8; i++) 772 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 773 774 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 775 MD5Init(&md5ctx); 776 MD5Update(&md5ctx, macini->cri_key, 777 macini->cri_klen / 8); 778 MD5Update(&md5ctx, hmac_opad_buffer, 779 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 780 bcopy(md5ctx.state, ses->ses_hmouter, 781 sizeof(md5ctx.state)); 782 } else { 783 SHA1Init(&sha1ctx); 784 SHA1Update(&sha1ctx, macini->cri_key, 785 macini->cri_klen / 8); 786 SHA1Update(&sha1ctx, hmac_opad_buffer, 787 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 788 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 789 sizeof(sha1ctx.h.b32)); 790 } 791 792 for (i = 0; i < macini->cri_klen / 8; i++) 793 macini->cri_key[i] ^= HMAC_OPAD_VAL; 794 795 /* PE is little-endian, insure proper byte order */ 796 for (i = 0; i < N(ses->ses_hminner); i++) { 797 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 798 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 799 } 800 } 801 802 *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 803 return (0); 804 #undef N 805 } 806 807 /* 808 * Deallocate a session. 809 */ 810 static int 811 safe_freesession(void *arg, u_int64_t tid) 812 { 813 struct safe_softc *sc = arg; 814 int session, ret; 815 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 816 817 if (sc == NULL) 818 return (EINVAL); 819 820 session = SAFE_SESSION(sid); 821 if (session < sc->sc_nsessions) { 822 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 823 ret = 0; 824 } else 825 ret = EINVAL; 826 return (ret); 827 } 828 829 static void 830 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 831 { 832 struct safe_operand *op = arg; 833 834 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 835 (u_int) mapsize, nsegs, error)); 836 if (error != 0) 837 return; 838 op->mapsize = mapsize; 839 op->nsegs = nsegs; 840 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 841 } 842 843 static int 844 safe_process(void *arg, struct cryptop *crp, int hint) 845 { 846 int err = 0, i, nicealign, uniform; 847 struct safe_softc *sc = arg; 848 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 849 int bypass, oplen, ivsize; 850 caddr_t iv; 851 int16_t coffset; 852 struct safe_session *ses; 853 struct safe_ringentry *re; 854 struct safe_sarec *sa; 855 struct safe_pdesc *pd; 856 u_int32_t cmd0, cmd1, staterec; 857 858 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 859 safestats.st_invalid++; 860 return (EINVAL); 861 } 862 if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 863 safestats.st_badsession++; 864 return (EINVAL); 865 } 866 867 mtx_lock(&sc->sc_ringmtx); 868 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 869 safestats.st_ringfull++; 870 sc->sc_needwakeup |= CRYPTO_SYMQ; 871 mtx_unlock(&sc->sc_ringmtx); 872 return (ERESTART); 873 } 874 re = sc->sc_front; 875 876 staterec = re->re_sa.sa_staterec; /* save */ 877 /* NB: zero everything but the PE descriptor */ 878 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 879 re->re_sa.sa_staterec = staterec; /* restore */ 880 881 re->re_crp = crp; 882 re->re_sesn = SAFE_SESSION(crp->crp_sid); 883 884 if (crp->crp_flags & CRYPTO_F_IMBUF) { 885 re->re_src_m = (struct mbuf *)crp->crp_buf; 886 re->re_dst_m = (struct mbuf *)crp->crp_buf; 887 } else if (crp->crp_flags & CRYPTO_F_IOV) { 888 re->re_src_io = (struct uio *)crp->crp_buf; 889 re->re_dst_io = (struct uio *)crp->crp_buf; 890 } else { 891 safestats.st_badflags++; 892 err = EINVAL; 893 goto errout; /* XXX we don't handle contiguous blocks! */ 894 } 895 896 sa = &re->re_sa; 897 ses = &sc->sc_sessions[re->re_sesn]; 898 899 crd1 = crp->crp_desc; 900 if (crd1 == NULL) { 901 safestats.st_nodesc++; 902 err = EINVAL; 903 goto errout; 904 } 905 crd2 = crd1->crd_next; 906 907 if ((crd1->crd_flags & CRD_F_KEY_EXPLICIT) || 908 (crd2 != NULL && (crd2->crd_flags & CRD_F_KEY_EXPLICIT))) { 909 safestats.st_badflags++; 910 err = EINVAL; 911 goto errout; 912 } 913 914 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 915 cmd1 = 0; 916 if (crd2 == NULL) { 917 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 918 crd1->crd_alg == CRYPTO_SHA1_HMAC || 919 crd1->crd_alg == CRYPTO_NULL_HMAC) { 920 maccrd = crd1; 921 enccrd = NULL; 922 cmd0 |= SAFE_SA_CMD0_OP_HASH; 923 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 924 crd1->crd_alg == CRYPTO_3DES_CBC || 925 crd1->crd_alg == CRYPTO_AES_CBC || 926 crd1->crd_alg == CRYPTO_NULL_CBC) { 927 maccrd = NULL; 928 enccrd = crd1; 929 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 930 } else { 931 safestats.st_badalg++; 932 err = EINVAL; 933 goto errout; 934 } 935 } else { 936 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 937 crd1->crd_alg == CRYPTO_SHA1_HMAC || 938 crd1->crd_alg == CRYPTO_NULL_HMAC) && 939 (crd2->crd_alg == CRYPTO_DES_CBC || 940 crd2->crd_alg == CRYPTO_3DES_CBC || 941 crd2->crd_alg == CRYPTO_AES_CBC || 942 crd2->crd_alg == CRYPTO_NULL_CBC) && 943 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 944 maccrd = crd1; 945 enccrd = crd2; 946 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 947 crd1->crd_alg == CRYPTO_3DES_CBC || 948 crd1->crd_alg == CRYPTO_AES_CBC || 949 crd1->crd_alg == CRYPTO_NULL_CBC) && 950 (crd2->crd_alg == CRYPTO_MD5_HMAC || 951 crd2->crd_alg == CRYPTO_SHA1_HMAC || 952 crd2->crd_alg == CRYPTO_NULL_HMAC) && 953 (crd1->crd_flags & CRD_F_ENCRYPT)) { 954 enccrd = crd1; 955 maccrd = crd2; 956 } else { 957 safestats.st_badalg++; 958 err = EINVAL; 959 goto errout; 960 } 961 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 962 } 963 964 if (enccrd) { 965 if (enccrd->crd_alg == CRYPTO_DES_CBC) { 966 cmd0 |= SAFE_SA_CMD0_DES; 967 cmd1 |= SAFE_SA_CMD1_CBC; 968 ivsize = 2*sizeof(u_int32_t); 969 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 970 cmd0 |= SAFE_SA_CMD0_3DES; 971 cmd1 |= SAFE_SA_CMD1_CBC; 972 ivsize = 2*sizeof(u_int32_t); 973 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 974 cmd0 |= SAFE_SA_CMD0_AES; 975 cmd1 |= SAFE_SA_CMD1_CBC; 976 if (ses->ses_klen == 128) 977 cmd1 |= SAFE_SA_CMD1_AES128; 978 else if (ses->ses_klen == 192) 979 cmd1 |= SAFE_SA_CMD1_AES192; 980 else 981 cmd1 |= SAFE_SA_CMD1_AES256; 982 ivsize = 4*sizeof(u_int32_t); 983 } else { 984 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 985 ivsize = 0; 986 } 987 988 /* 989 * Setup encrypt/decrypt state. When using basic ops 990 * we can't use an inline IV because hash/crypt offset 991 * must be from the end of the IV to the start of the 992 * crypt data and this leaves out the preceding header 993 * from the hash calculation. Instead we place the IV 994 * in the state record and set the hash/crypt offset to 995 * copy both the header+IV. 996 */ 997 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 998 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 999 1000 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1001 iv = enccrd->crd_iv; 1002 else 1003 iv = (caddr_t) ses->ses_iv; 1004 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1005 if (crp->crp_flags & CRYPTO_F_IMBUF) 1006 m_copyback(re->re_src_m, 1007 enccrd->crd_inject, ivsize, iv); 1008 else if (crp->crp_flags & CRYPTO_F_IOV) 1009 cuio_copyback(re->re_src_io, 1010 enccrd->crd_inject, ivsize, iv); 1011 } 1012 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1013 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1014 re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1015 } else { 1016 cmd0 |= SAFE_SA_CMD0_INBOUND; 1017 1018 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1019 bcopy(enccrd->crd_iv, 1020 re->re_sastate.sa_saved_iv, ivsize); 1021 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1022 m_copydata(re->re_src_m, enccrd->crd_inject, 1023 ivsize, 1024 (caddr_t)re->re_sastate.sa_saved_iv); 1025 else if (crp->crp_flags & CRYPTO_F_IOV) 1026 cuio_copydata(re->re_src_io, enccrd->crd_inject, 1027 ivsize, 1028 (caddr_t)re->re_sastate.sa_saved_iv); 1029 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1030 } 1031 /* 1032 * For basic encryption use the zero pad algorithm. 1033 * This pads results to an 8-byte boundary and 1034 * suppresses padding verification for inbound (i.e. 1035 * decrypt) operations. 1036 * 1037 * NB: Not sure if the 8-byte pad boundary is a problem. 1038 */ 1039 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1040 1041 /* XXX assert key bufs have the same size */ 1042 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1043 } 1044 1045 if (maccrd) { 1046 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1047 cmd0 |= SAFE_SA_CMD0_MD5; 1048 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1049 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1050 cmd0 |= SAFE_SA_CMD0_SHA1; 1051 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1052 } else { 1053 cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1054 } 1055 /* 1056 * Digest data is loaded from the SA and the hash 1057 * result is saved to the state block where we 1058 * retrieve it for return to the caller. 1059 */ 1060 /* XXX assert digest bufs have the same size */ 1061 bcopy(ses->ses_hminner, sa->sa_indigest, 1062 sizeof(sa->sa_indigest)); 1063 bcopy(ses->ses_hmouter, sa->sa_outdigest, 1064 sizeof(sa->sa_outdigest)); 1065 1066 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1067 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1068 } 1069 1070 if (enccrd && maccrd) { 1071 /* 1072 * The offset from hash data to the start of 1073 * crypt data is the difference in the skips. 1074 */ 1075 bypass = maccrd->crd_skip; 1076 coffset = enccrd->crd_skip - maccrd->crd_skip; 1077 if (coffset < 0) { 1078 DPRINTF(("%s: hash does not precede crypt; " 1079 "mac skip %u enc skip %u\n", 1080 __func__, maccrd->crd_skip, enccrd->crd_skip)); 1081 safestats.st_skipmismatch++; 1082 err = EINVAL; 1083 goto errout; 1084 } 1085 oplen = enccrd->crd_skip + enccrd->crd_len; 1086 if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1087 DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1088 __func__, maccrd->crd_skip + maccrd->crd_len, 1089 oplen)); 1090 safestats.st_lenmismatch++; 1091 err = EINVAL; 1092 goto errout; 1093 } 1094 #ifdef SAFE_DEBUG 1095 if (safe_debug) { 1096 printf("mac: skip %d, len %d, inject %d\n", 1097 maccrd->crd_skip, maccrd->crd_len, 1098 maccrd->crd_inject); 1099 printf("enc: skip %d, len %d, inject %d\n", 1100 enccrd->crd_skip, enccrd->crd_len, 1101 enccrd->crd_inject); 1102 printf("bypass %d coffset %d oplen %d\n", 1103 bypass, coffset, oplen); 1104 } 1105 #endif 1106 if (coffset & 3) { /* offset must be 32-bit aligned */ 1107 DPRINTF(("%s: coffset %u misaligned\n", 1108 __func__, coffset)); 1109 safestats.st_coffmisaligned++; 1110 err = EINVAL; 1111 goto errout; 1112 } 1113 coffset >>= 2; 1114 if (coffset > 255) { /* offset must be <256 dwords */ 1115 DPRINTF(("%s: coffset %u too big\n", 1116 __func__, coffset)); 1117 safestats.st_cofftoobig++; 1118 err = EINVAL; 1119 goto errout; 1120 } 1121 /* 1122 * Tell the hardware to copy the header to the output. 1123 * The header is defined as the data from the end of 1124 * the bypass to the start of data to be encrypted. 1125 * Typically this is the inline IV. Note that you need 1126 * to do this even if src+dst are the same; it appears 1127 * that w/o this bit the crypted data is written 1128 * immediately after the bypass data. 1129 */ 1130 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1131 /* 1132 * Disable IP header mutable bit handling. This is 1133 * needed to get correct HMAC calculations. 1134 */ 1135 cmd1 |= SAFE_SA_CMD1_MUTABLE; 1136 } else { 1137 if (enccrd) { 1138 bypass = enccrd->crd_skip; 1139 oplen = bypass + enccrd->crd_len; 1140 } else { 1141 bypass = maccrd->crd_skip; 1142 oplen = bypass + maccrd->crd_len; 1143 } 1144 coffset = 0; 1145 } 1146 /* XXX verify multiple of 4 when using s/g */ 1147 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1148 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1149 safestats.st_bypasstoobig++; 1150 err = EINVAL; 1151 goto errout; 1152 } 1153 1154 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1155 safestats.st_nomap++; 1156 err = ENOMEM; 1157 goto errout; 1158 } 1159 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1160 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1161 re->re_src_m, safe_op_cb, 1162 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1163 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1164 re->re_src_map = NULL; 1165 safestats.st_noload++; 1166 err = ENOMEM; 1167 goto errout; 1168 } 1169 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1170 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1171 re->re_src_io, safe_op_cb, 1172 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1173 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1174 re->re_src_map = NULL; 1175 safestats.st_noload++; 1176 err = ENOMEM; 1177 goto errout; 1178 } 1179 } 1180 nicealign = safe_dmamap_aligned(&re->re_src); 1181 uniform = safe_dmamap_uniform(&re->re_src); 1182 1183 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1184 nicealign, uniform, re->re_src.nsegs)); 1185 if (re->re_src.nsegs > 1) { 1186 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1187 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1188 for (i = 0; i < re->re_src_nsegs; i++) { 1189 /* NB: no need to check if there's space */ 1190 pd = sc->sc_spfree; 1191 if (++(sc->sc_spfree) == sc->sc_springtop) 1192 sc->sc_spfree = sc->sc_spring; 1193 1194 KASSERT((pd->pd_flags&3) == 0 || 1195 (pd->pd_flags&3) == SAFE_PD_DONE, 1196 ("bogus source particle descriptor; flags %x", 1197 pd->pd_flags)); 1198 pd->pd_addr = re->re_src_segs[i].ds_addr; 1199 pd->pd_size = re->re_src_segs[i].ds_len; 1200 pd->pd_flags = SAFE_PD_READY; 1201 } 1202 cmd0 |= SAFE_SA_CMD0_IGATHER; 1203 } else { 1204 /* 1205 * No need for gather, reference the operand directly. 1206 */ 1207 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1208 } 1209 1210 if (enccrd == NULL && maccrd != NULL) { 1211 /* 1212 * Hash op; no destination needed. 1213 */ 1214 } else { 1215 if (crp->crp_flags & CRYPTO_F_IOV) { 1216 if (!nicealign) { 1217 safestats.st_iovmisaligned++; 1218 err = EINVAL; 1219 goto errout; 1220 } 1221 if (uniform != 1) { 1222 /* 1223 * Source is not suitable for direct use as 1224 * the destination. Create a new scatter/gather 1225 * list based on the destination requirements 1226 * and check if that's ok. 1227 */ 1228 if (bus_dmamap_create(sc->sc_dstdmat, 1229 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1230 safestats.st_nomap++; 1231 err = ENOMEM; 1232 goto errout; 1233 } 1234 if (bus_dmamap_load_uio(sc->sc_dstdmat, 1235 re->re_dst_map, re->re_dst_io, 1236 safe_op_cb, &re->re_dst, 1237 BUS_DMA_NOWAIT) != 0) { 1238 bus_dmamap_destroy(sc->sc_dstdmat, 1239 re->re_dst_map); 1240 re->re_dst_map = NULL; 1241 safestats.st_noload++; 1242 err = ENOMEM; 1243 goto errout; 1244 } 1245 uniform = safe_dmamap_uniform(&re->re_dst); 1246 if (!uniform) { 1247 /* 1248 * There's no way to handle the DMA 1249 * requirements with this uio. We 1250 * could create a separate DMA area for 1251 * the result and then copy it back, 1252 * but for now we just bail and return 1253 * an error. Note that uio requests 1254 * > SAFE_MAX_DSIZE are handled because 1255 * the DMA map and segment list for the 1256 * destination wil result in a 1257 * destination particle list that does 1258 * the necessary scatter DMA. 1259 */ 1260 safestats.st_iovnotuniform++; 1261 err = EINVAL; 1262 goto errout; 1263 } 1264 } else 1265 re->re_dst = re->re_src; 1266 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1267 if (nicealign && uniform == 1) { 1268 /* 1269 * Source layout is suitable for direct 1270 * sharing of the DMA map and segment list. 1271 */ 1272 re->re_dst = re->re_src; 1273 } else if (nicealign && uniform == 2) { 1274 /* 1275 * The source is properly aligned but requires a 1276 * different particle list to handle DMA of the 1277 * result. Create a new map and do the load to 1278 * create the segment list. The particle 1279 * descriptor setup code below will handle the 1280 * rest. 1281 */ 1282 if (bus_dmamap_create(sc->sc_dstdmat, 1283 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1284 safestats.st_nomap++; 1285 err = ENOMEM; 1286 goto errout; 1287 } 1288 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1289 re->re_dst_map, re->re_dst_m, 1290 safe_op_cb, &re->re_dst, 1291 BUS_DMA_NOWAIT) != 0) { 1292 bus_dmamap_destroy(sc->sc_dstdmat, 1293 re->re_dst_map); 1294 re->re_dst_map = NULL; 1295 safestats.st_noload++; 1296 err = ENOMEM; 1297 goto errout; 1298 } 1299 } else { /* !(aligned and/or uniform) */ 1300 int totlen, len; 1301 struct mbuf *m, *top, **mp; 1302 1303 /* 1304 * DMA constraints require that we allocate a 1305 * new mbuf chain for the destination. We 1306 * allocate an entire new set of mbufs of 1307 * optimal/required size and then tell the 1308 * hardware to copy any bits that are not 1309 * created as a byproduct of the operation. 1310 */ 1311 if (!nicealign) 1312 safestats.st_unaligned++; 1313 if (!uniform) 1314 safestats.st_notuniform++; 1315 totlen = re->re_src_mapsize; 1316 if (re->re_src_m->m_flags & M_PKTHDR) { 1317 len = MHLEN; 1318 MGETHDR(m, M_DONTWAIT, MT_DATA); 1319 if (m && !m_dup_pkthdr(m, re->re_src_m, 1320 M_DONTWAIT)) { 1321 m_free(m); 1322 m = NULL; 1323 } 1324 } else { 1325 len = MLEN; 1326 MGET(m, M_DONTWAIT, MT_DATA); 1327 } 1328 if (m == NULL) { 1329 safestats.st_nombuf++; 1330 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1331 goto errout; 1332 } 1333 if (totlen >= MINCLSIZE) { 1334 MCLGET(m, M_DONTWAIT); 1335 if ((m->m_flags & M_EXT) == 0) { 1336 m_free(m); 1337 safestats.st_nomcl++; 1338 err = sc->sc_nqchip ? 1339 ERESTART : ENOMEM; 1340 goto errout; 1341 } 1342 len = MCLBYTES; 1343 } 1344 m->m_len = len; 1345 top = NULL; 1346 mp = ⊤ 1347 1348 while (totlen > 0) { 1349 if (top) { 1350 MGET(m, M_DONTWAIT, MT_DATA); 1351 if (m == NULL) { 1352 m_freem(top); 1353 safestats.st_nombuf++; 1354 err = sc->sc_nqchip ? 1355 ERESTART : ENOMEM; 1356 goto errout; 1357 } 1358 len = MLEN; 1359 } 1360 if (top && totlen >= MINCLSIZE) { 1361 MCLGET(m, M_DONTWAIT); 1362 if ((m->m_flags & M_EXT) == 0) { 1363 *mp = m; 1364 m_freem(top); 1365 safestats.st_nomcl++; 1366 err = sc->sc_nqchip ? 1367 ERESTART : ENOMEM; 1368 goto errout; 1369 } 1370 len = MCLBYTES; 1371 } 1372 m->m_len = len = min(totlen, len); 1373 totlen -= len; 1374 *mp = m; 1375 mp = &m->m_next; 1376 } 1377 re->re_dst_m = top; 1378 if (bus_dmamap_create(sc->sc_dstdmat, 1379 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1380 safestats.st_nomap++; 1381 err = ENOMEM; 1382 goto errout; 1383 } 1384 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1385 re->re_dst_map, re->re_dst_m, 1386 safe_op_cb, &re->re_dst, 1387 BUS_DMA_NOWAIT) != 0) { 1388 bus_dmamap_destroy(sc->sc_dstdmat, 1389 re->re_dst_map); 1390 re->re_dst_map = NULL; 1391 safestats.st_noload++; 1392 err = ENOMEM; 1393 goto errout; 1394 } 1395 if (re->re_src.mapsize > oplen) { 1396 /* 1397 * There's data following what the 1398 * hardware will copy for us. If this 1399 * isn't just the ICV (that's going to 1400 * be written on completion), copy it 1401 * to the new mbufs 1402 */ 1403 if (!(maccrd && 1404 (re->re_src.mapsize-oplen) == 12 && 1405 maccrd->crd_inject == oplen)) 1406 safe_mcopy(re->re_src_m, 1407 re->re_dst_m, 1408 oplen); 1409 else 1410 safestats.st_noicvcopy++; 1411 } 1412 } 1413 } else { 1414 safestats.st_badflags++; 1415 err = EINVAL; 1416 goto errout; 1417 } 1418 1419 if (re->re_dst.nsegs > 1) { 1420 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1421 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1422 for (i = 0; i < re->re_dst_nsegs; i++) { 1423 pd = sc->sc_dpfree; 1424 KASSERT((pd->pd_flags&3) == 0 || 1425 (pd->pd_flags&3) == SAFE_PD_DONE, 1426 ("bogus dest particle descriptor; flags %x", 1427 pd->pd_flags)); 1428 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1429 sc->sc_dpfree = sc->sc_dpring; 1430 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1431 pd->pd_flags = SAFE_PD_READY; 1432 } 1433 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1434 } else { 1435 /* 1436 * No need for scatter, reference the operand directly. 1437 */ 1438 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1439 } 1440 } 1441 1442 /* 1443 * All done with setup; fillin the SA command words 1444 * and the packet engine descriptor. The operation 1445 * is now ready for submission to the hardware. 1446 */ 1447 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1448 sa->sa_cmd1 = cmd1 1449 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1450 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1451 | SAFE_SA_CMD1_SRPCI 1452 ; 1453 /* 1454 * NB: the order of writes is important here. In case the 1455 * chip is scanning the ring because of an outstanding request 1456 * it might nab this one too. In that case we need to make 1457 * sure the setup is complete before we write the length 1458 * field of the descriptor as it signals the descriptor is 1459 * ready for processing. 1460 */ 1461 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1462 if (maccrd) 1463 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1464 re->re_desc.d_len = oplen 1465 | SAFE_PE_LEN_READY 1466 | (bypass << SAFE_PE_LEN_BYPASS_S) 1467 ; 1468 1469 safestats.st_ipackets++; 1470 safestats.st_ibytes += oplen; 1471 1472 if (++(sc->sc_front) == sc->sc_ringtop) 1473 sc->sc_front = sc->sc_ring; 1474 1475 /* XXX honor batching */ 1476 safe_feed(sc, re); 1477 mtx_unlock(&sc->sc_ringmtx); 1478 return (0); 1479 1480 errout: 1481 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1482 m_freem(re->re_dst_m); 1483 1484 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1485 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1486 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1487 } 1488 if (re->re_src_map != NULL) { 1489 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1490 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1491 } 1492 mtx_unlock(&sc->sc_ringmtx); 1493 if (err != ERESTART) { 1494 crp->crp_etype = err; 1495 crypto_done(crp); 1496 } else { 1497 sc->sc_needwakeup |= CRYPTO_SYMQ; 1498 } 1499 return (err); 1500 } 1501 1502 static void 1503 safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1504 { 1505 struct cryptop *crp = (struct cryptop *)re->re_crp; 1506 struct cryptodesc *crd; 1507 1508 safestats.st_opackets++; 1509 safestats.st_obytes += re->re_dst.mapsize; 1510 1511 safe_dma_sync(&sc->sc_ringalloc, 1512 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1513 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1514 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1515 re->re_desc.d_csr, 1516 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1517 safestats.st_peoperr++; 1518 crp->crp_etype = EIO; /* something more meaningful? */ 1519 } 1520 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1521 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1522 BUS_DMASYNC_POSTREAD); 1523 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1524 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1525 } 1526 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1527 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1528 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1529 1530 /* 1531 * If result was written to a differet mbuf chain, swap 1532 * it in as the return value and reclaim the original. 1533 */ 1534 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1535 m_freem(re->re_src_m); 1536 crp->crp_buf = (caddr_t)re->re_dst_m; 1537 } 1538 1539 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1540 /* copy out IV for future use */ 1541 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1542 int ivsize; 1543 1544 if (crd->crd_alg == CRYPTO_DES_CBC || 1545 crd->crd_alg == CRYPTO_3DES_CBC) { 1546 ivsize = 2*sizeof(u_int32_t); 1547 } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1548 ivsize = 4*sizeof(u_int32_t); 1549 } else 1550 continue; 1551 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1552 m_copydata((struct mbuf *)crp->crp_buf, 1553 crd->crd_skip + crd->crd_len - ivsize, 1554 ivsize, 1555 (caddr_t) sc->sc_sessions[re->re_sesn].ses_iv); 1556 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1557 cuio_copydata((struct uio *)crp->crp_buf, 1558 crd->crd_skip + crd->crd_len - ivsize, 1559 ivsize, 1560 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1561 } 1562 break; 1563 } 1564 } 1565 1566 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1567 /* copy out ICV result */ 1568 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1569 if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1570 crd->crd_alg == CRYPTO_SHA1_HMAC || 1571 crd->crd_alg == CRYPTO_NULL_HMAC)) 1572 continue; 1573 if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1574 /* 1575 * SHA-1 ICV's are byte-swapped; fix 'em up 1576 * before copy them to their destination. 1577 */ 1578 bswap32(re->re_sastate.sa_saved_indigest[0]); 1579 bswap32(re->re_sastate.sa_saved_indigest[1]); 1580 bswap32(re->re_sastate.sa_saved_indigest[2]); 1581 } 1582 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1583 m_copyback((struct mbuf *)crp->crp_buf, 1584 crd->crd_inject, 12, 1585 (caddr_t)re->re_sastate.sa_saved_indigest); 1586 } else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) { 1587 bcopy((caddr_t)re->re_sastate.sa_saved_indigest, 1588 crp->crp_mac, 12); 1589 } 1590 break; 1591 } 1592 } 1593 crypto_done(crp); 1594 } 1595 1596 /* 1597 * Copy all data past offset from srcm to dstm. 1598 */ 1599 static void 1600 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1601 { 1602 u_int j, dlen, slen; 1603 caddr_t dptr, sptr; 1604 1605 /* 1606 * Advance src and dst to offset. 1607 */ 1608 j = offset; 1609 while (j >= 0) { 1610 if (srcm->m_len > j) 1611 break; 1612 j -= srcm->m_len; 1613 srcm = srcm->m_next; 1614 if (srcm == NULL) 1615 return; 1616 } 1617 sptr = mtod(srcm, caddr_t) + j; 1618 slen = srcm->m_len - j; 1619 1620 j = offset; 1621 while (j >= 0) { 1622 if (dstm->m_len > j) 1623 break; 1624 j -= dstm->m_len; 1625 dstm = dstm->m_next; 1626 if (dstm == NULL) 1627 return; 1628 } 1629 dptr = mtod(dstm, caddr_t) + j; 1630 dlen = dstm->m_len - j; 1631 1632 /* 1633 * Copy everything that remains. 1634 */ 1635 for (;;) { 1636 j = min(slen, dlen); 1637 bcopy(sptr, dptr, j); 1638 if (slen == j) { 1639 srcm = srcm->m_next; 1640 if (srcm == NULL) 1641 return; 1642 sptr = srcm->m_data; 1643 slen = srcm->m_len; 1644 } else 1645 sptr += j, slen -= j; 1646 if (dlen == j) { 1647 dstm = dstm->m_next; 1648 if (dstm == NULL) 1649 return; 1650 dptr = dstm->m_data; 1651 dlen = dstm->m_len; 1652 } else 1653 dptr += j, dlen -= j; 1654 } 1655 } 1656 1657 #ifndef SAFE_NO_RNG 1658 #define SAFE_RNG_MAXWAIT 1000 1659 1660 static void 1661 safe_rng_init(struct safe_softc *sc) 1662 { 1663 u_int32_t w, v; 1664 int i; 1665 1666 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1667 /* use default value according to the manual */ 1668 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1669 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1670 1671 /* 1672 * There is a bug in rev 1.0 of the 1140 that when the RNG 1673 * is brought out of reset the ready status flag does not 1674 * work until the RNG has finished its internal initialization. 1675 * 1676 * So in order to determine the device is through its 1677 * initialization we must read the data register, using the 1678 * status reg in the read in case it is initialized. Then read 1679 * the data register until it changes from the first read. 1680 * Once it changes read the data register until it changes 1681 * again. At this time the RNG is considered initialized. 1682 * This could take between 750ms - 1000ms in time. 1683 */ 1684 i = 0; 1685 w = READ_REG(sc, SAFE_RNG_OUT); 1686 do { 1687 v = READ_REG(sc, SAFE_RNG_OUT); 1688 if (v != w) { 1689 w = v; 1690 break; 1691 } 1692 DELAY(10); 1693 } while (++i < SAFE_RNG_MAXWAIT); 1694 1695 /* Wait Until data changes again */ 1696 i = 0; 1697 do { 1698 v = READ_REG(sc, SAFE_RNG_OUT); 1699 if (v != w) 1700 break; 1701 DELAY(10); 1702 } while (++i < SAFE_RNG_MAXWAIT); 1703 } 1704 1705 static __inline void 1706 safe_rng_disable_short_cycle(struct safe_softc *sc) 1707 { 1708 WRITE_REG(sc, SAFE_RNG_CTRL, 1709 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1710 } 1711 1712 static __inline void 1713 safe_rng_enable_short_cycle(struct safe_softc *sc) 1714 { 1715 WRITE_REG(sc, SAFE_RNG_CTRL, 1716 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1717 } 1718 1719 static __inline u_int32_t 1720 safe_rng_read(struct safe_softc *sc) 1721 { 1722 int i; 1723 1724 i = 0; 1725 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1726 ; 1727 return READ_REG(sc, SAFE_RNG_OUT); 1728 } 1729 1730 static void 1731 safe_rng(void *arg) 1732 { 1733 struct safe_softc *sc = arg; 1734 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1735 u_int maxwords; 1736 int i; 1737 1738 safestats.st_rng++; 1739 /* 1740 * Fetch the next block of data. 1741 */ 1742 maxwords = safe_rngbufsize; 1743 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1744 maxwords = SAFE_RNG_MAXBUFSIZ; 1745 retry: 1746 for (i = 0; i < maxwords; i++) 1747 buf[i] = safe_rng_read(sc); 1748 /* 1749 * Check the comparator alarm count and reset the h/w if 1750 * it exceeds our threshold. This guards against the 1751 * hardware oscillators resonating with external signals. 1752 */ 1753 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1754 u_int32_t freq_inc, w; 1755 1756 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1757 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1758 safestats.st_rngalarm++; 1759 safe_rng_enable_short_cycle(sc); 1760 freq_inc = 18; 1761 for (i = 0; i < 64; i++) { 1762 w = READ_REG(sc, SAFE_RNG_CNFG); 1763 freq_inc = ((w + freq_inc) & 0x3fL); 1764 w = ((w & ~0x3fL) | freq_inc); 1765 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1766 1767 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1768 1769 (void) safe_rng_read(sc); 1770 DELAY(25); 1771 1772 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1773 safe_rng_disable_short_cycle(sc); 1774 goto retry; 1775 } 1776 freq_inc = 1; 1777 } 1778 safe_rng_disable_short_cycle(sc); 1779 } else 1780 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1781 1782 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1783 callout_reset(&sc->sc_rngto, 1784 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1785 } 1786 #endif /* SAFE_NO_RNG */ 1787 1788 static void 1789 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1790 { 1791 bus_addr_t *paddr = (bus_addr_t*) arg; 1792 *paddr = segs->ds_addr; 1793 } 1794 1795 static int 1796 safe_dma_malloc( 1797 struct safe_softc *sc, 1798 bus_size_t size, 1799 struct safe_dma_alloc *dma, 1800 int mapflags 1801 ) 1802 { 1803 int r; 1804 1805 r = bus_dma_tag_create(NULL, /* parent */ 1806 sizeof(u_int32_t), 0, /* alignment, bounds */ 1807 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1808 BUS_SPACE_MAXADDR, /* highaddr */ 1809 NULL, NULL, /* filter, filterarg */ 1810 size, /* maxsize */ 1811 1, /* nsegments */ 1812 size, /* maxsegsize */ 1813 BUS_DMA_ALLOCNOW, /* flags */ 1814 NULL, NULL, /* locking */ 1815 &dma->dma_tag); 1816 if (r != 0) { 1817 device_printf(sc->sc_dev, "safe_dma_malloc: " 1818 "bus_dma_tag_create failed; error %u\n", r); 1819 goto fail_0; 1820 } 1821 1822 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1823 if (r != 0) { 1824 device_printf(sc->sc_dev, "safe_dma_malloc: " 1825 "bus_dmamap_create failed; error %u\n", r); 1826 goto fail_1; 1827 } 1828 1829 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1830 BUS_DMA_NOWAIT, &dma->dma_map); 1831 if (r != 0) { 1832 device_printf(sc->sc_dev, "safe_dma_malloc: " 1833 "bus_dmammem_alloc failed; size %zu, error %u\n", 1834 size, r); 1835 goto fail_2; 1836 } 1837 1838 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1839 size, 1840 safe_dmamap_cb, 1841 &dma->dma_paddr, 1842 mapflags | BUS_DMA_NOWAIT); 1843 if (r != 0) { 1844 device_printf(sc->sc_dev, "safe_dma_malloc: " 1845 "bus_dmamap_load failed; error %u\n", r); 1846 goto fail_3; 1847 } 1848 1849 dma->dma_size = size; 1850 return (0); 1851 1852 fail_3: 1853 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1854 fail_2: 1855 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1856 fail_1: 1857 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1858 bus_dma_tag_destroy(dma->dma_tag); 1859 fail_0: 1860 dma->dma_map = NULL; 1861 dma->dma_tag = NULL; 1862 return (r); 1863 } 1864 1865 static void 1866 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1867 { 1868 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1869 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1870 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1871 bus_dma_tag_destroy(dma->dma_tag); 1872 } 1873 1874 /* 1875 * Resets the board. Values in the regesters are left as is 1876 * from the reset (i.e. initial values are assigned elsewhere). 1877 */ 1878 static void 1879 safe_reset_board(struct safe_softc *sc) 1880 { 1881 u_int32_t v; 1882 /* 1883 * Reset the device. The manual says no delay 1884 * is needed between marking and clearing reset. 1885 */ 1886 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1887 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1888 SAFE_PE_DMACFG_SGRESET); 1889 WRITE_REG(sc, SAFE_PE_DMACFG, v 1890 | SAFE_PE_DMACFG_PERESET 1891 | SAFE_PE_DMACFG_PDRRESET 1892 | SAFE_PE_DMACFG_SGRESET); 1893 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1894 } 1895 1896 /* 1897 * Initialize registers we need to touch only once. 1898 */ 1899 static void 1900 safe_init_board(struct safe_softc *sc) 1901 { 1902 u_int32_t v, dwords; 1903 1904 v = READ_REG(sc, SAFE_PE_DMACFG);; 1905 v &=~ SAFE_PE_DMACFG_PEMODE; 1906 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1907 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1908 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1909 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1910 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1911 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1912 ; 1913 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1914 #if 0 1915 /* XXX select byte swap based on host byte order */ 1916 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1917 #endif 1918 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1919 /* 1920 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1921 * "target mode transfers" done while the chip is DMA'ing 1922 * >1020 bytes cause the hardware to lockup. To avoid this 1923 * we reduce the max PCI transfer size and use small source 1924 * particle descriptors (<= 256 bytes). 1925 */ 1926 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1927 device_printf(sc->sc_dev, 1928 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1929 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1930 SAFE_REV_MAJ(sc->sc_chiprev), 1931 SAFE_REV_MIN(sc->sc_chiprev)); 1932 } 1933 1934 /* NB: operands+results are overlaid */ 1935 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1936 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1937 /* 1938 * Configure ring entry size and number of items in the ring. 1939 */ 1940 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1941 ("PE ring entry not 32-bit aligned!")); 1942 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1943 WRITE_REG(sc, SAFE_PE_RINGCFG, 1944 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1945 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1946 1947 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1948 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1949 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1950 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1951 /* 1952 * NB: destination particles are fixed size. We use 1953 * an mbuf cluster and require all results go to 1954 * clusters or smaller. 1955 */ 1956 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1957 1958 /* it's now safe to enable PE mode, do it */ 1959 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1960 1961 /* 1962 * Configure hardware to use level-triggered interrupts and 1963 * to interrupt after each descriptor is processed. 1964 */ 1965 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1966 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1967 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1968 } 1969 1970 /* 1971 * Init PCI registers 1972 */ 1973 static void 1974 safe_init_pciregs(device_t dev) 1975 { 1976 } 1977 1978 /* 1979 * Clean up after a chip crash. 1980 * It is assumed that the caller in splimp() 1981 */ 1982 static void 1983 safe_cleanchip(struct safe_softc *sc) 1984 { 1985 1986 if (sc->sc_nqchip != 0) { 1987 struct safe_ringentry *re = sc->sc_back; 1988 1989 while (re != sc->sc_front) { 1990 if (re->re_desc.d_csr != 0) 1991 safe_free_entry(sc, re); 1992 if (++re == sc->sc_ringtop) 1993 re = sc->sc_ring; 1994 } 1995 sc->sc_back = re; 1996 sc->sc_nqchip = 0; 1997 } 1998 } 1999 2000 /* 2001 * free a safe_q 2002 * It is assumed that the caller is within splimp(). 2003 */ 2004 static int 2005 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2006 { 2007 struct cryptop *crp; 2008 2009 /* 2010 * Free header MCR 2011 */ 2012 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2013 m_freem(re->re_dst_m); 2014 2015 crp = (struct cryptop *)re->re_crp; 2016 2017 re->re_desc.d_csr = 0; 2018 2019 crp->crp_etype = EFAULT; 2020 crypto_done(crp); 2021 return(0); 2022 } 2023 2024 /* 2025 * Routine to reset the chip and clean up. 2026 * It is assumed that the caller is in splimp() 2027 */ 2028 static void 2029 safe_totalreset(struct safe_softc *sc) 2030 { 2031 safe_reset_board(sc); 2032 safe_init_board(sc); 2033 safe_cleanchip(sc); 2034 } 2035 2036 /* 2037 * Is the operand suitable aligned for direct DMA. Each 2038 * segment must be aligned on a 32-bit boundary and all 2039 * but the last segment must be a multiple of 4 bytes. 2040 */ 2041 static int 2042 safe_dmamap_aligned(const struct safe_operand *op) 2043 { 2044 int i; 2045 2046 for (i = 0; i < op->nsegs; i++) { 2047 if (op->segs[i].ds_addr & 3) 2048 return (0); 2049 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2050 return (0); 2051 } 2052 return (1); 2053 } 2054 2055 /* 2056 * Is the operand suitable for direct DMA as the destination 2057 * of an operation. The hardware requires that each ``particle'' 2058 * but the last in an operation result have the same size. We 2059 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2060 * 0 if some segment is not a multiple of of this size, 1 if all 2061 * segments are exactly this size, or 2 if segments are at worst 2062 * a multple of this size. 2063 */ 2064 static int 2065 safe_dmamap_uniform(const struct safe_operand *op) 2066 { 2067 int result = 1; 2068 2069 if (op->nsegs > 0) { 2070 int i; 2071 2072 for (i = 0; i < op->nsegs-1; i++) { 2073 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2074 return (0); 2075 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2076 result = 2; 2077 } 2078 } 2079 return (result); 2080 } 2081 2082 #ifdef SAFE_DEBUG 2083 static void 2084 safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2085 { 2086 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2087 , tag 2088 , READ_REG(sc, SAFE_DMA_ENDIAN) 2089 , READ_REG(sc, SAFE_DMA_SRCADDR) 2090 , READ_REG(sc, SAFE_DMA_DSTADDR) 2091 , READ_REG(sc, SAFE_DMA_STAT) 2092 ); 2093 } 2094 2095 static void 2096 safe_dump_intrstate(struct safe_softc *sc, const char *tag) 2097 { 2098 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2099 , tag 2100 , READ_REG(sc, SAFE_HI_CFG) 2101 , READ_REG(sc, SAFE_HI_MASK) 2102 , READ_REG(sc, SAFE_HI_DESC_CNT) 2103 , READ_REG(sc, SAFE_HU_STAT) 2104 , READ_REG(sc, SAFE_HM_STAT) 2105 ); 2106 } 2107 2108 static void 2109 safe_dump_ringstate(struct safe_softc *sc, const char *tag) 2110 { 2111 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2112 2113 /* NB: assume caller has lock on ring */ 2114 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2115 tag, 2116 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2117 (unsigned long)(sc->sc_back - sc->sc_ring), 2118 (unsigned long)(sc->sc_front - sc->sc_ring)); 2119 } 2120 2121 static void 2122 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2123 { 2124 int ix, nsegs; 2125 2126 ix = re - sc->sc_ring; 2127 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2128 , tag 2129 , re, ix 2130 , re->re_desc.d_csr 2131 , re->re_desc.d_src 2132 , re->re_desc.d_dst 2133 , re->re_desc.d_sa 2134 , re->re_desc.d_len 2135 ); 2136 if (re->re_src.nsegs > 1) { 2137 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2138 sizeof(struct safe_pdesc); 2139 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2140 printf(" spd[%u] %p: %p size %u flags %x" 2141 , ix, &sc->sc_spring[ix] 2142 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2143 , sc->sc_spring[ix].pd_size 2144 , sc->sc_spring[ix].pd_flags 2145 ); 2146 if (sc->sc_spring[ix].pd_size == 0) 2147 printf(" (zero!)"); 2148 printf("\n"); 2149 if (++ix == SAFE_TOTAL_SPART) 2150 ix = 0; 2151 } 2152 } 2153 if (re->re_dst.nsegs > 1) { 2154 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2155 sizeof(struct safe_pdesc); 2156 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2157 printf(" dpd[%u] %p: %p flags %x\n" 2158 , ix, &sc->sc_dpring[ix] 2159 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2160 , sc->sc_dpring[ix].pd_flags 2161 ); 2162 if (++ix == SAFE_TOTAL_DPART) 2163 ix = 0; 2164 } 2165 } 2166 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2167 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2168 printf("sa: key %x %x %x %x %x %x %x %x\n" 2169 , re->re_sa.sa_key[0] 2170 , re->re_sa.sa_key[1] 2171 , re->re_sa.sa_key[2] 2172 , re->re_sa.sa_key[3] 2173 , re->re_sa.sa_key[4] 2174 , re->re_sa.sa_key[5] 2175 , re->re_sa.sa_key[6] 2176 , re->re_sa.sa_key[7] 2177 ); 2178 printf("sa: indigest %x %x %x %x %x\n" 2179 , re->re_sa.sa_indigest[0] 2180 , re->re_sa.sa_indigest[1] 2181 , re->re_sa.sa_indigest[2] 2182 , re->re_sa.sa_indigest[3] 2183 , re->re_sa.sa_indigest[4] 2184 ); 2185 printf("sa: outdigest %x %x %x %x %x\n" 2186 , re->re_sa.sa_outdigest[0] 2187 , re->re_sa.sa_outdigest[1] 2188 , re->re_sa.sa_outdigest[2] 2189 , re->re_sa.sa_outdigest[3] 2190 , re->re_sa.sa_outdigest[4] 2191 ); 2192 printf("sr: iv %x %x %x %x\n" 2193 , re->re_sastate.sa_saved_iv[0] 2194 , re->re_sastate.sa_saved_iv[1] 2195 , re->re_sastate.sa_saved_iv[2] 2196 , re->re_sastate.sa_saved_iv[3] 2197 ); 2198 printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2199 , re->re_sastate.sa_saved_hashbc 2200 , re->re_sastate.sa_saved_indigest[0] 2201 , re->re_sastate.sa_saved_indigest[1] 2202 , re->re_sastate.sa_saved_indigest[2] 2203 , re->re_sastate.sa_saved_indigest[3] 2204 , re->re_sastate.sa_saved_indigest[4] 2205 ); 2206 } 2207 2208 static void 2209 safe_dump_ring(struct safe_softc *sc, const char *tag) 2210 { 2211 mtx_lock(&sc->sc_ringmtx); 2212 printf("\nSafeNet Ring State:\n"); 2213 safe_dump_intrstate(sc, tag); 2214 safe_dump_dmastatus(sc, tag); 2215 safe_dump_ringstate(sc, tag); 2216 if (sc->sc_nqchip) { 2217 struct safe_ringentry *re = sc->sc_back; 2218 do { 2219 safe_dump_request(sc, tag, re); 2220 if (++re == sc->sc_ringtop) 2221 re = sc->sc_ring; 2222 } while (re != sc->sc_front); 2223 } 2224 mtx_unlock(&sc->sc_ringmtx); 2225 } 2226 2227 static int 2228 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2229 { 2230 char dmode[64]; 2231 int error; 2232 2233 strncpy(dmode, "", sizeof(dmode) - 1); 2234 dmode[sizeof(dmode) - 1] = '\0'; 2235 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2236 2237 if (error == 0 && req->newptr != NULL) { 2238 struct safe_softc *sc = safec; 2239 2240 if (!sc) 2241 return EINVAL; 2242 if (strncmp(dmode, "dma", 3) == 0) 2243 safe_dump_dmastatus(sc, "safe0"); 2244 else if (strncmp(dmode, "int", 3) == 0) 2245 safe_dump_intrstate(sc, "safe0"); 2246 else if (strncmp(dmode, "ring", 4) == 0) 2247 safe_dump_ring(sc, "safe0"); 2248 else 2249 return EINVAL; 2250 } 2251 return error; 2252 } 2253 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2254 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2255 #endif /* SAFE_DEBUG */ 2256