1 /*- 2 * Copyright (c) 2003 Sam Leffler, Errno Consulting 3 * Copyright (c) 2003 Global Technology Associates, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * SafeNet SafeXcel-1141 hardware crypto accelerator 33 */ 34 #include "opt_safe.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/proc.h> 39 #include <sys/errno.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/mbuf.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/sysctl.h> 47 #include <sys/endian.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 #include <sys/bus.h> 55 #include <sys/rman.h> 56 57 #include <crypto/sha1.h> 58 #include <opencrypto/cryptodev.h> 59 #include <opencrypto/cryptosoft.h> 60 #include <sys/md5.h> 61 #include <sys/random.h> 62 #include <sys/kobj.h> 63 64 #include "cryptodev_if.h" 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 69 #ifdef SAFE_RNDTEST 70 #include <dev/rndtest/rndtest.h> 71 #endif 72 #include <dev/safe/safereg.h> 73 #include <dev/safe/safevar.h> 74 75 #ifndef bswap32 76 #define bswap32 NTOHL 77 #endif 78 79 /* 80 * Prototypes and count for the pci_device structure 81 */ 82 static int safe_probe(device_t); 83 static int safe_attach(device_t); 84 static int safe_detach(device_t); 85 static int safe_suspend(device_t); 86 static int safe_resume(device_t); 87 static int safe_shutdown(device_t); 88 89 static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); 90 static int safe_freesession(device_t, u_int64_t); 91 static int safe_process(device_t, struct cryptop *, int); 92 93 static device_method_t safe_methods[] = { 94 /* Device interface */ 95 DEVMETHOD(device_probe, safe_probe), 96 DEVMETHOD(device_attach, safe_attach), 97 DEVMETHOD(device_detach, safe_detach), 98 DEVMETHOD(device_suspend, safe_suspend), 99 DEVMETHOD(device_resume, safe_resume), 100 DEVMETHOD(device_shutdown, safe_shutdown), 101 102 /* bus interface */ 103 DEVMETHOD(bus_print_child, bus_generic_print_child), 104 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 105 106 /* crypto device methods */ 107 DEVMETHOD(cryptodev_newsession, safe_newsession), 108 DEVMETHOD(cryptodev_freesession,safe_freesession), 109 DEVMETHOD(cryptodev_process, safe_process), 110 111 { 0, 0 } 112 }; 113 static driver_t safe_driver = { 114 "safe", 115 safe_methods, 116 sizeof (struct safe_softc) 117 }; 118 static devclass_t safe_devclass; 119 120 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0); 121 MODULE_DEPEND(safe, crypto, 1, 1, 1); 122 #ifdef SAFE_RNDTEST 123 MODULE_DEPEND(safe, rndtest, 1, 1, 1); 124 #endif 125 126 static void safe_intr(void *); 127 static void safe_callback(struct safe_softc *, struct safe_ringentry *); 128 static void safe_feed(struct safe_softc *, struct safe_ringentry *); 129 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int); 130 #ifndef SAFE_NO_RNG 131 static void safe_rng_init(struct safe_softc *); 132 static void safe_rng(void *); 133 #endif /* SAFE_NO_RNG */ 134 static int safe_dma_malloc(struct safe_softc *, bus_size_t, 135 struct safe_dma_alloc *, int); 136 #define safe_dma_sync(_dma, _flags) \ 137 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 138 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *); 139 static int safe_dmamap_aligned(const struct safe_operand *); 140 static int safe_dmamap_uniform(const struct safe_operand *); 141 142 static void safe_reset_board(struct safe_softc *); 143 static void safe_init_board(struct safe_softc *); 144 static void safe_init_pciregs(device_t dev); 145 static void safe_cleanchip(struct safe_softc *); 146 static void safe_totalreset(struct safe_softc *); 147 148 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *); 149 150 SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0, "SafeNet driver parameters"); 151 152 #ifdef SAFE_DEBUG 153 static void safe_dump_dmastatus(struct safe_softc *, const char *); 154 static void safe_dump_ringstate(struct safe_softc *, const char *); 155 static void safe_dump_intrstate(struct safe_softc *, const char *); 156 static void safe_dump_request(struct safe_softc *, const char *, 157 struct safe_ringentry *); 158 159 static struct safe_softc *safec; /* for use by hw.safe.dump */ 160 161 static int safe_debug = 0; 162 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug, 163 0, "control debugging msgs"); 164 #define DPRINTF(_x) if (safe_debug) printf _x 165 #else 166 #define DPRINTF(_x) 167 #endif 168 169 #define READ_REG(sc,r) \ 170 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 171 172 #define WRITE_REG(sc,reg,val) \ 173 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 174 175 struct safe_stats safestats; 176 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats, 177 safe_stats, "driver statistics"); 178 #ifndef SAFE_NO_RNG 179 static int safe_rnginterval = 1; /* poll once a second */ 180 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval, 181 0, "RNG polling interval (secs)"); 182 static int safe_rngbufsize = 16; /* 64 bytes each poll */ 183 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize, 184 0, "RNG polling buffer size (32-bit words)"); 185 static int safe_rngmaxalarm = 8; /* max alarms before reset */ 186 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm, 187 0, "RNG max alarms before reset"); 188 #endif /* SAFE_NO_RNG */ 189 190 static int 191 safe_probe(device_t dev) 192 { 193 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET && 194 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL) 195 return (BUS_PROBE_DEFAULT); 196 return (ENXIO); 197 } 198 199 static const char* 200 safe_partname(struct safe_softc *sc) 201 { 202 /* XXX sprintf numbers when not decoded */ 203 switch (pci_get_vendor(sc->sc_dev)) { 204 case PCI_VENDOR_SAFENET: 205 switch (pci_get_device(sc->sc_dev)) { 206 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141"; 207 } 208 return "SafeNet unknown-part"; 209 } 210 return "Unknown-vendor unknown-part"; 211 } 212 213 #ifndef SAFE_NO_RNG 214 static void 215 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 216 { 217 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 218 } 219 #endif /* SAFE_NO_RNG */ 220 221 static int 222 safe_attach(device_t dev) 223 { 224 struct safe_softc *sc = device_get_softc(dev); 225 u_int32_t raddr; 226 u_int32_t cmd, i, devinfo; 227 int rid; 228 229 bzero(sc, sizeof (*sc)); 230 sc->sc_dev = dev; 231 232 /* XXX handle power management */ 233 234 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 235 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 236 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 237 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 238 239 if (!(cmd & PCIM_CMD_MEMEN)) { 240 device_printf(dev, "failed to enable memory mapping\n"); 241 goto bad; 242 } 243 244 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 245 device_printf(dev, "failed to enable bus mastering\n"); 246 goto bad; 247 } 248 249 /* 250 * Setup memory-mapping of PCI registers. 251 */ 252 rid = BS_BAR; 253 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 254 RF_ACTIVE); 255 if (sc->sc_sr == NULL) { 256 device_printf(dev, "cannot map register space\n"); 257 goto bad; 258 } 259 sc->sc_st = rman_get_bustag(sc->sc_sr); 260 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 261 262 /* 263 * Arrange interrupt line. 264 */ 265 rid = 0; 266 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 267 RF_SHAREABLE|RF_ACTIVE); 268 if (sc->sc_irq == NULL) { 269 device_printf(dev, "could not map interrupt\n"); 270 goto bad1; 271 } 272 /* 273 * NB: Network code assumes we are blocked with splimp() 274 * so make sure the IRQ is mapped appropriately. 275 */ 276 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 277 NULL, safe_intr, sc, &sc->sc_ih)) { 278 device_printf(dev, "could not establish interrupt\n"); 279 goto bad2; 280 } 281 282 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 283 if (sc->sc_cid < 0) { 284 device_printf(dev, "could not get crypto driver id\n"); 285 goto bad3; 286 } 287 288 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & 289 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); 290 291 /* 292 * Setup DMA descriptor area. 293 */ 294 if (bus_dma_tag_create(NULL, /* parent */ 295 1, /* alignment */ 296 SAFE_DMA_BOUNDARY, /* boundary */ 297 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 298 BUS_SPACE_MAXADDR, /* highaddr */ 299 NULL, NULL, /* filter, filterarg */ 300 SAFE_MAX_DMA, /* maxsize */ 301 SAFE_MAX_PART, /* nsegments */ 302 SAFE_MAX_SSIZE, /* maxsegsize */ 303 BUS_DMA_ALLOCNOW, /* flags */ 304 NULL, NULL, /* locking */ 305 &sc->sc_srcdmat)) { 306 device_printf(dev, "cannot allocate DMA tag\n"); 307 goto bad4; 308 } 309 if (bus_dma_tag_create(NULL, /* parent */ 310 1, /* alignment */ 311 SAFE_MAX_DSIZE, /* boundary */ 312 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 313 BUS_SPACE_MAXADDR, /* highaddr */ 314 NULL, NULL, /* filter, filterarg */ 315 SAFE_MAX_DMA, /* maxsize */ 316 SAFE_MAX_PART, /* nsegments */ 317 SAFE_MAX_DSIZE, /* maxsegsize */ 318 BUS_DMA_ALLOCNOW, /* flags */ 319 NULL, NULL, /* locking */ 320 &sc->sc_dstdmat)) { 321 device_printf(dev, "cannot allocate DMA tag\n"); 322 goto bad4; 323 } 324 325 /* 326 * Allocate packet engine descriptors. 327 */ 328 if (safe_dma_malloc(sc, 329 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), 330 &sc->sc_ringalloc, 0)) { 331 device_printf(dev, "cannot allocate PE descriptor ring\n"); 332 bus_dma_tag_destroy(sc->sc_srcdmat); 333 goto bad4; 334 } 335 /* 336 * Hookup the static portion of all our data structures. 337 */ 338 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; 339 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; 340 sc->sc_front = sc->sc_ring; 341 sc->sc_back = sc->sc_ring; 342 raddr = sc->sc_ringalloc.dma_paddr; 343 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); 344 for (i = 0; i < SAFE_MAX_NQUEUE; i++) { 345 struct safe_ringentry *re = &sc->sc_ring[i]; 346 347 re->re_desc.d_sa = raddr + 348 offsetof(struct safe_ringentry, re_sa); 349 re->re_sa.sa_staterec = raddr + 350 offsetof(struct safe_ringentry, re_sastate); 351 352 raddr += sizeof (struct safe_ringentry); 353 } 354 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev), 355 "packet engine ring", MTX_DEF); 356 357 /* 358 * Allocate scatter and gather particle descriptors. 359 */ 360 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), 361 &sc->sc_spalloc, 0)) { 362 device_printf(dev, "cannot allocate source particle " 363 "descriptor ring\n"); 364 mtx_destroy(&sc->sc_ringmtx); 365 safe_dma_free(sc, &sc->sc_ringalloc); 366 bus_dma_tag_destroy(sc->sc_srcdmat); 367 goto bad4; 368 } 369 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; 370 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; 371 sc->sc_spfree = sc->sc_spring; 372 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); 373 374 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), 375 &sc->sc_dpalloc, 0)) { 376 device_printf(dev, "cannot allocate destination particle " 377 "descriptor ring\n"); 378 mtx_destroy(&sc->sc_ringmtx); 379 safe_dma_free(sc, &sc->sc_spalloc); 380 safe_dma_free(sc, &sc->sc_ringalloc); 381 bus_dma_tag_destroy(sc->sc_dstdmat); 382 goto bad4; 383 } 384 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; 385 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; 386 sc->sc_dpfree = sc->sc_dpring; 387 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); 388 389 device_printf(sc->sc_dev, "%s", safe_partname(sc)); 390 391 devinfo = READ_REG(sc, SAFE_DEVINFO); 392 if (devinfo & SAFE_DEVINFO_RNG) { 393 sc->sc_flags |= SAFE_FLAGS_RNG; 394 printf(" rng"); 395 } 396 if (devinfo & SAFE_DEVINFO_PKEY) { 397 #if 0 398 printf(" key"); 399 sc->sc_flags |= SAFE_FLAGS_KEY; 400 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 401 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 402 #endif 403 } 404 if (devinfo & SAFE_DEVINFO_DES) { 405 printf(" des/3des"); 406 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 407 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 408 } 409 if (devinfo & SAFE_DEVINFO_AES) { 410 printf(" aes"); 411 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 412 } 413 if (devinfo & SAFE_DEVINFO_MD5) { 414 printf(" md5"); 415 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 416 } 417 if (devinfo & SAFE_DEVINFO_SHA1) { 418 printf(" sha1"); 419 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 420 } 421 printf(" null"); 422 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); 423 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); 424 /* XXX other supported algorithms */ 425 printf("\n"); 426 427 safe_reset_board(sc); /* reset h/w */ 428 safe_init_pciregs(dev); /* init pci settings */ 429 safe_init_board(sc); /* init h/w */ 430 431 #ifndef SAFE_NO_RNG 432 if (sc->sc_flags & SAFE_FLAGS_RNG) { 433 #ifdef SAFE_RNDTEST 434 sc->sc_rndtest = rndtest_attach(dev); 435 if (sc->sc_rndtest) 436 sc->sc_harvest = rndtest_harvest; 437 else 438 sc->sc_harvest = default_harvest; 439 #else 440 sc->sc_harvest = default_harvest; 441 #endif 442 safe_rng_init(sc); 443 444 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 445 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc); 446 } 447 #endif /* SAFE_NO_RNG */ 448 #ifdef SAFE_DEBUG 449 safec = sc; /* for use by hw.safe.dump */ 450 #endif 451 return (0); 452 bad4: 453 crypto_unregister_all(sc->sc_cid); 454 bad3: 455 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 456 bad2: 457 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 458 bad1: 459 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 460 bad: 461 return (ENXIO); 462 } 463 464 /* 465 * Detach a device that successfully probed. 466 */ 467 static int 468 safe_detach(device_t dev) 469 { 470 struct safe_softc *sc = device_get_softc(dev); 471 472 /* XXX wait/abort active ops */ 473 474 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ 475 476 callout_stop(&sc->sc_rngto); 477 478 crypto_unregister_all(sc->sc_cid); 479 480 #ifdef SAFE_RNDTEST 481 if (sc->sc_rndtest) 482 rndtest_detach(sc->sc_rndtest); 483 #endif 484 485 safe_cleanchip(sc); 486 safe_dma_free(sc, &sc->sc_dpalloc); 487 safe_dma_free(sc, &sc->sc_spalloc); 488 mtx_destroy(&sc->sc_ringmtx); 489 safe_dma_free(sc, &sc->sc_ringalloc); 490 491 bus_generic_detach(dev); 492 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 493 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 494 495 bus_dma_tag_destroy(sc->sc_srcdmat); 496 bus_dma_tag_destroy(sc->sc_dstdmat); 497 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 498 499 return (0); 500 } 501 502 /* 503 * Stop all chip i/o so that the kernel's probe routines don't 504 * get confused by errant DMAs when rebooting. 505 */ 506 static int 507 safe_shutdown(device_t dev) 508 { 509 #ifdef notyet 510 safe_stop(device_get_softc(dev)); 511 #endif 512 return (0); 513 } 514 515 /* 516 * Device suspend routine. 517 */ 518 static int 519 safe_suspend(device_t dev) 520 { 521 struct safe_softc *sc = device_get_softc(dev); 522 523 #ifdef notyet 524 /* XXX stop the device and save PCI settings */ 525 #endif 526 sc->sc_suspended = 1; 527 528 return (0); 529 } 530 531 static int 532 safe_resume(device_t dev) 533 { 534 struct safe_softc *sc = device_get_softc(dev); 535 536 #ifdef notyet 537 /* XXX retore PCI settings and start the device */ 538 #endif 539 sc->sc_suspended = 0; 540 return (0); 541 } 542 543 /* 544 * SafeXcel Interrupt routine 545 */ 546 static void 547 safe_intr(void *arg) 548 { 549 struct safe_softc *sc = arg; 550 volatile u_int32_t stat; 551 552 stat = READ_REG(sc, SAFE_HM_STAT); 553 if (stat == 0) /* shared irq, not for us */ 554 return; 555 556 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ 557 558 if ((stat & SAFE_INT_PE_DDONE)) { 559 /* 560 * Descriptor(s) done; scan the ring and 561 * process completed operations. 562 */ 563 mtx_lock(&sc->sc_ringmtx); 564 while (sc->sc_back != sc->sc_front) { 565 struct safe_ringentry *re = sc->sc_back; 566 #ifdef SAFE_DEBUG 567 if (safe_debug) { 568 safe_dump_ringstate(sc, __func__); 569 safe_dump_request(sc, __func__, re); 570 } 571 #endif 572 /* 573 * safe_process marks ring entries that were allocated 574 * but not used with a csr of zero. This insures the 575 * ring front pointer never needs to be set backwards 576 * in the event that an entry is allocated but not used 577 * because of a setup error. 578 */ 579 if (re->re_desc.d_csr != 0) { 580 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) 581 break; 582 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) 583 break; 584 sc->sc_nqchip--; 585 safe_callback(sc, re); 586 } 587 if (++(sc->sc_back) == sc->sc_ringtop) 588 sc->sc_back = sc->sc_ring; 589 } 590 mtx_unlock(&sc->sc_ringmtx); 591 } 592 593 /* 594 * Check to see if we got any DMA Error 595 */ 596 if (stat & SAFE_INT_PE_ERROR) { 597 DPRINTF(("dmaerr dmastat %08x\n", 598 READ_REG(sc, SAFE_PE_DMASTAT))); 599 safestats.st_dmaerr++; 600 safe_totalreset(sc); 601 #if 0 602 safe_feed(sc); 603 #endif 604 } 605 606 if (sc->sc_needwakeup) { /* XXX check high watermark */ 607 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 608 DPRINTF(("%s: wakeup crypto %x\n", __func__, 609 sc->sc_needwakeup)); 610 sc->sc_needwakeup &= ~wakeup; 611 crypto_unblock(sc->sc_cid, wakeup); 612 } 613 } 614 615 /* 616 * safe_feed() - post a request to chip 617 */ 618 static void 619 safe_feed(struct safe_softc *sc, struct safe_ringentry *re) 620 { 621 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE); 622 if (re->re_dst_map != NULL) 623 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 624 BUS_DMASYNC_PREREAD); 625 /* XXX have no smaller granularity */ 626 safe_dma_sync(&sc->sc_ringalloc, 627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 628 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE); 629 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE); 630 631 #ifdef SAFE_DEBUG 632 if (safe_debug) { 633 safe_dump_ringstate(sc, __func__); 634 safe_dump_request(sc, __func__, re); 635 } 636 #endif 637 sc->sc_nqchip++; 638 if (sc->sc_nqchip > safestats.st_maxqchip) 639 safestats.st_maxqchip = sc->sc_nqchip; 640 /* poke h/w to check descriptor ring, any value can be written */ 641 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); 642 } 643 644 #define N(a) (sizeof(a) / sizeof (a[0])) 645 static void 646 safe_setup_enckey(struct safe_session *ses, caddr_t key) 647 { 648 int i; 649 650 bcopy(key, ses->ses_key, ses->ses_klen / 8); 651 652 /* PE is little-endian, insure proper byte order */ 653 for (i = 0; i < N(ses->ses_key); i++) 654 ses->ses_key[i] = htole32(ses->ses_key[i]); 655 } 656 657 static void 658 safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) 659 { 660 MD5_CTX md5ctx; 661 SHA1_CTX sha1ctx; 662 int i; 663 664 665 for (i = 0; i < klen; i++) 666 key[i] ^= HMAC_IPAD_VAL; 667 668 if (algo == CRYPTO_MD5_HMAC) { 669 MD5Init(&md5ctx); 670 MD5Update(&md5ctx, key, klen); 671 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 672 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 673 } else { 674 SHA1Init(&sha1ctx); 675 SHA1Update(&sha1ctx, key, klen); 676 SHA1Update(&sha1ctx, hmac_ipad_buffer, 677 SHA1_HMAC_BLOCK_LEN - klen); 678 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 679 } 680 681 for (i = 0; i < klen; i++) 682 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 683 684 if (algo == CRYPTO_MD5_HMAC) { 685 MD5Init(&md5ctx); 686 MD5Update(&md5ctx, key, klen); 687 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 688 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 689 } else { 690 SHA1Init(&sha1ctx); 691 SHA1Update(&sha1ctx, key, klen); 692 SHA1Update(&sha1ctx, hmac_opad_buffer, 693 SHA1_HMAC_BLOCK_LEN - klen); 694 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 695 } 696 697 for (i = 0; i < klen; i++) 698 key[i] ^= HMAC_OPAD_VAL; 699 700 /* PE is little-endian, insure proper byte order */ 701 for (i = 0; i < N(ses->ses_hminner); i++) { 702 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); 703 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); 704 } 705 } 706 #undef N 707 708 /* 709 * Allocate a new 'session' and return an encoded session id. 'sidp' 710 * contains our registration id, and should contain an encoded session 711 * id on successful allocation. 712 */ 713 static int 714 safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 715 { 716 struct safe_softc *sc = device_get_softc(dev); 717 struct cryptoini *c, *encini = NULL, *macini = NULL; 718 struct safe_session *ses = NULL; 719 int sesn; 720 721 if (sidp == NULL || cri == NULL || sc == NULL) 722 return (EINVAL); 723 724 for (c = cri; c != NULL; c = c->cri_next) { 725 if (c->cri_alg == CRYPTO_MD5_HMAC || 726 c->cri_alg == CRYPTO_SHA1_HMAC || 727 c->cri_alg == CRYPTO_NULL_HMAC) { 728 if (macini) 729 return (EINVAL); 730 macini = c; 731 } else if (c->cri_alg == CRYPTO_DES_CBC || 732 c->cri_alg == CRYPTO_3DES_CBC || 733 c->cri_alg == CRYPTO_AES_CBC || 734 c->cri_alg == CRYPTO_NULL_CBC) { 735 if (encini) 736 return (EINVAL); 737 encini = c; 738 } else 739 return (EINVAL); 740 } 741 if (encini == NULL && macini == NULL) 742 return (EINVAL); 743 if (encini) { /* validate key length */ 744 switch (encini->cri_alg) { 745 case CRYPTO_DES_CBC: 746 if (encini->cri_klen != 64) 747 return (EINVAL); 748 break; 749 case CRYPTO_3DES_CBC: 750 if (encini->cri_klen != 192) 751 return (EINVAL); 752 break; 753 case CRYPTO_AES_CBC: 754 if (encini->cri_klen != 128 && 755 encini->cri_klen != 192 && 756 encini->cri_klen != 256) 757 return (EINVAL); 758 break; 759 } 760 } 761 762 if (sc->sc_sessions == NULL) { 763 ses = sc->sc_sessions = (struct safe_session *)malloc( 764 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 765 if (ses == NULL) 766 return (ENOMEM); 767 sesn = 0; 768 sc->sc_nsessions = 1; 769 } else { 770 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 771 if (sc->sc_sessions[sesn].ses_used == 0) { 772 ses = &sc->sc_sessions[sesn]; 773 break; 774 } 775 } 776 777 if (ses == NULL) { 778 sesn = sc->sc_nsessions; 779 ses = (struct safe_session *)malloc((sesn + 1) * 780 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT); 781 if (ses == NULL) 782 return (ENOMEM); 783 bcopy(sc->sc_sessions, ses, sesn * 784 sizeof(struct safe_session)); 785 bzero(sc->sc_sessions, sesn * 786 sizeof(struct safe_session)); 787 free(sc->sc_sessions, M_DEVBUF); 788 sc->sc_sessions = ses; 789 ses = &sc->sc_sessions[sesn]; 790 sc->sc_nsessions++; 791 } 792 } 793 794 bzero(ses, sizeof(struct safe_session)); 795 ses->ses_used = 1; 796 797 if (encini) { 798 /* get an IV */ 799 /* XXX may read fewer than requested */ 800 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 801 802 ses->ses_klen = encini->cri_klen; 803 if (encini->cri_key != NULL) 804 safe_setup_enckey(ses, encini->cri_key); 805 } 806 807 if (macini) { 808 ses->ses_mlen = macini->cri_mlen; 809 if (ses->ses_mlen == 0) { 810 if (macini->cri_alg == CRYPTO_MD5_HMAC) 811 ses->ses_mlen = MD5_HASH_LEN; 812 else 813 ses->ses_mlen = SHA1_HASH_LEN; 814 } 815 816 if (macini->cri_key != NULL) { 817 safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, 818 macini->cri_klen / 8); 819 } 820 } 821 822 *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); 823 return (0); 824 } 825 826 /* 827 * Deallocate a session. 828 */ 829 static int 830 safe_freesession(device_t dev, u_int64_t tid) 831 { 832 struct safe_softc *sc = device_get_softc(dev); 833 int session, ret; 834 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 835 836 if (sc == NULL) 837 return (EINVAL); 838 839 session = SAFE_SESSION(sid); 840 if (session < sc->sc_nsessions) { 841 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 842 ret = 0; 843 } else 844 ret = EINVAL; 845 return (ret); 846 } 847 848 static void 849 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 850 { 851 struct safe_operand *op = arg; 852 853 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__, 854 (u_int) mapsize, nsegs, error)); 855 if (error != 0) 856 return; 857 op->mapsize = mapsize; 858 op->nsegs = nsegs; 859 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 860 } 861 862 static int 863 safe_process(device_t dev, struct cryptop *crp, int hint) 864 { 865 struct safe_softc *sc = device_get_softc(dev); 866 int err = 0, i, nicealign, uniform; 867 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 868 int bypass, oplen, ivsize; 869 caddr_t iv; 870 int16_t coffset; 871 struct safe_session *ses; 872 struct safe_ringentry *re; 873 struct safe_sarec *sa; 874 struct safe_pdesc *pd; 875 u_int32_t cmd0, cmd1, staterec; 876 877 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 878 safestats.st_invalid++; 879 return (EINVAL); 880 } 881 if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 882 safestats.st_badsession++; 883 return (EINVAL); 884 } 885 886 mtx_lock(&sc->sc_ringmtx); 887 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { 888 safestats.st_ringfull++; 889 sc->sc_needwakeup |= CRYPTO_SYMQ; 890 mtx_unlock(&sc->sc_ringmtx); 891 return (ERESTART); 892 } 893 re = sc->sc_front; 894 895 staterec = re->re_sa.sa_staterec; /* save */ 896 /* NB: zero everything but the PE descriptor */ 897 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); 898 re->re_sa.sa_staterec = staterec; /* restore */ 899 900 re->re_crp = crp; 901 re->re_sesn = SAFE_SESSION(crp->crp_sid); 902 903 if (crp->crp_flags & CRYPTO_F_IMBUF) { 904 re->re_src_m = (struct mbuf *)crp->crp_buf; 905 re->re_dst_m = (struct mbuf *)crp->crp_buf; 906 } else if (crp->crp_flags & CRYPTO_F_IOV) { 907 re->re_src_io = (struct uio *)crp->crp_buf; 908 re->re_dst_io = (struct uio *)crp->crp_buf; 909 } else { 910 safestats.st_badflags++; 911 err = EINVAL; 912 goto errout; /* XXX we don't handle contiguous blocks! */ 913 } 914 915 sa = &re->re_sa; 916 ses = &sc->sc_sessions[re->re_sesn]; 917 918 crd1 = crp->crp_desc; 919 if (crd1 == NULL) { 920 safestats.st_nodesc++; 921 err = EINVAL; 922 goto errout; 923 } 924 crd2 = crd1->crd_next; 925 926 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ 927 cmd1 = 0; 928 if (crd2 == NULL) { 929 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 930 crd1->crd_alg == CRYPTO_SHA1_HMAC || 931 crd1->crd_alg == CRYPTO_NULL_HMAC) { 932 maccrd = crd1; 933 enccrd = NULL; 934 cmd0 |= SAFE_SA_CMD0_OP_HASH; 935 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 936 crd1->crd_alg == CRYPTO_3DES_CBC || 937 crd1->crd_alg == CRYPTO_AES_CBC || 938 crd1->crd_alg == CRYPTO_NULL_CBC) { 939 maccrd = NULL; 940 enccrd = crd1; 941 cmd0 |= SAFE_SA_CMD0_OP_CRYPT; 942 } else { 943 safestats.st_badalg++; 944 err = EINVAL; 945 goto errout; 946 } 947 } else { 948 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 949 crd1->crd_alg == CRYPTO_SHA1_HMAC || 950 crd1->crd_alg == CRYPTO_NULL_HMAC) && 951 (crd2->crd_alg == CRYPTO_DES_CBC || 952 crd2->crd_alg == CRYPTO_3DES_CBC || 953 crd2->crd_alg == CRYPTO_AES_CBC || 954 crd2->crd_alg == CRYPTO_NULL_CBC) && 955 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 956 maccrd = crd1; 957 enccrd = crd2; 958 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 959 crd1->crd_alg == CRYPTO_3DES_CBC || 960 crd1->crd_alg == CRYPTO_AES_CBC || 961 crd1->crd_alg == CRYPTO_NULL_CBC) && 962 (crd2->crd_alg == CRYPTO_MD5_HMAC || 963 crd2->crd_alg == CRYPTO_SHA1_HMAC || 964 crd2->crd_alg == CRYPTO_NULL_HMAC) && 965 (crd1->crd_flags & CRD_F_ENCRYPT)) { 966 enccrd = crd1; 967 maccrd = crd2; 968 } else { 969 safestats.st_badalg++; 970 err = EINVAL; 971 goto errout; 972 } 973 cmd0 |= SAFE_SA_CMD0_OP_BOTH; 974 } 975 976 if (enccrd) { 977 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 978 safe_setup_enckey(ses, enccrd->crd_key); 979 980 if (enccrd->crd_alg == CRYPTO_DES_CBC) { 981 cmd0 |= SAFE_SA_CMD0_DES; 982 cmd1 |= SAFE_SA_CMD1_CBC; 983 ivsize = 2*sizeof(u_int32_t); 984 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { 985 cmd0 |= SAFE_SA_CMD0_3DES; 986 cmd1 |= SAFE_SA_CMD1_CBC; 987 ivsize = 2*sizeof(u_int32_t); 988 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { 989 cmd0 |= SAFE_SA_CMD0_AES; 990 cmd1 |= SAFE_SA_CMD1_CBC; 991 if (ses->ses_klen == 128) 992 cmd1 |= SAFE_SA_CMD1_AES128; 993 else if (ses->ses_klen == 192) 994 cmd1 |= SAFE_SA_CMD1_AES192; 995 else 996 cmd1 |= SAFE_SA_CMD1_AES256; 997 ivsize = 4*sizeof(u_int32_t); 998 } else { 999 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; 1000 ivsize = 0; 1001 } 1002 1003 /* 1004 * Setup encrypt/decrypt state. When using basic ops 1005 * we can't use an inline IV because hash/crypt offset 1006 * must be from the end of the IV to the start of the 1007 * crypt data and this leaves out the preceding header 1008 * from the hash calculation. Instead we place the IV 1009 * in the state record and set the hash/crypt offset to 1010 * copy both the header+IV. 1011 */ 1012 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1013 cmd0 |= SAFE_SA_CMD0_OUTBOUND; 1014 1015 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1016 iv = enccrd->crd_iv; 1017 else 1018 iv = (caddr_t) ses->ses_iv; 1019 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1020 crypto_copyback(crp->crp_flags, crp->crp_buf, 1021 enccrd->crd_inject, ivsize, iv); 1022 } 1023 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); 1024 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; 1025 re->re_flags |= SAFE_QFLAGS_COPYOUTIV; 1026 } else { 1027 cmd0 |= SAFE_SA_CMD0_INBOUND; 1028 1029 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { 1030 bcopy(enccrd->crd_iv, 1031 re->re_sastate.sa_saved_iv, ivsize); 1032 } else { 1033 crypto_copydata(crp->crp_flags, crp->crp_buf, 1034 enccrd->crd_inject, ivsize, 1035 (caddr_t)re->re_sastate.sa_saved_iv); 1036 } 1037 cmd0 |= SAFE_SA_CMD0_IVLD_STATE; 1038 } 1039 /* 1040 * For basic encryption use the zero pad algorithm. 1041 * This pads results to an 8-byte boundary and 1042 * suppresses padding verification for inbound (i.e. 1043 * decrypt) operations. 1044 * 1045 * NB: Not sure if the 8-byte pad boundary is a problem. 1046 */ 1047 cmd0 |= SAFE_SA_CMD0_PAD_ZERO; 1048 1049 /* XXX assert key bufs have the same size */ 1050 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); 1051 } 1052 1053 if (maccrd) { 1054 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1055 safe_setup_mackey(ses, maccrd->crd_alg, 1056 maccrd->crd_key, maccrd->crd_klen / 8); 1057 } 1058 1059 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { 1060 cmd0 |= SAFE_SA_CMD0_MD5; 1061 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1062 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { 1063 cmd0 |= SAFE_SA_CMD0_SHA1; 1064 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ 1065 } else { 1066 cmd0 |= SAFE_SA_CMD0_HASH_NULL; 1067 } 1068 /* 1069 * Digest data is loaded from the SA and the hash 1070 * result is saved to the state block where we 1071 * retrieve it for return to the caller. 1072 */ 1073 /* XXX assert digest bufs have the same size */ 1074 bcopy(ses->ses_hminner, sa->sa_indigest, 1075 sizeof(sa->sa_indigest)); 1076 bcopy(ses->ses_hmouter, sa->sa_outdigest, 1077 sizeof(sa->sa_outdigest)); 1078 1079 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; 1080 re->re_flags |= SAFE_QFLAGS_COPYOUTICV; 1081 } 1082 1083 if (enccrd && maccrd) { 1084 /* 1085 * The offset from hash data to the start of 1086 * crypt data is the difference in the skips. 1087 */ 1088 bypass = maccrd->crd_skip; 1089 coffset = enccrd->crd_skip - maccrd->crd_skip; 1090 if (coffset < 0) { 1091 DPRINTF(("%s: hash does not precede crypt; " 1092 "mac skip %u enc skip %u\n", 1093 __func__, maccrd->crd_skip, enccrd->crd_skip)); 1094 safestats.st_skipmismatch++; 1095 err = EINVAL; 1096 goto errout; 1097 } 1098 oplen = enccrd->crd_skip + enccrd->crd_len; 1099 if (maccrd->crd_skip + maccrd->crd_len != oplen) { 1100 DPRINTF(("%s: hash amount %u != crypt amount %u\n", 1101 __func__, maccrd->crd_skip + maccrd->crd_len, 1102 oplen)); 1103 safestats.st_lenmismatch++; 1104 err = EINVAL; 1105 goto errout; 1106 } 1107 #ifdef SAFE_DEBUG 1108 if (safe_debug) { 1109 printf("mac: skip %d, len %d, inject %d\n", 1110 maccrd->crd_skip, maccrd->crd_len, 1111 maccrd->crd_inject); 1112 printf("enc: skip %d, len %d, inject %d\n", 1113 enccrd->crd_skip, enccrd->crd_len, 1114 enccrd->crd_inject); 1115 printf("bypass %d coffset %d oplen %d\n", 1116 bypass, coffset, oplen); 1117 } 1118 #endif 1119 if (coffset & 3) { /* offset must be 32-bit aligned */ 1120 DPRINTF(("%s: coffset %u misaligned\n", 1121 __func__, coffset)); 1122 safestats.st_coffmisaligned++; 1123 err = EINVAL; 1124 goto errout; 1125 } 1126 coffset >>= 2; 1127 if (coffset > 255) { /* offset must be <256 dwords */ 1128 DPRINTF(("%s: coffset %u too big\n", 1129 __func__, coffset)); 1130 safestats.st_cofftoobig++; 1131 err = EINVAL; 1132 goto errout; 1133 } 1134 /* 1135 * Tell the hardware to copy the header to the output. 1136 * The header is defined as the data from the end of 1137 * the bypass to the start of data to be encrypted. 1138 * Typically this is the inline IV. Note that you need 1139 * to do this even if src+dst are the same; it appears 1140 * that w/o this bit the crypted data is written 1141 * immediately after the bypass data. 1142 */ 1143 cmd1 |= SAFE_SA_CMD1_HDRCOPY; 1144 /* 1145 * Disable IP header mutable bit handling. This is 1146 * needed to get correct HMAC calculations. 1147 */ 1148 cmd1 |= SAFE_SA_CMD1_MUTABLE; 1149 } else { 1150 if (enccrd) { 1151 bypass = enccrd->crd_skip; 1152 oplen = bypass + enccrd->crd_len; 1153 } else { 1154 bypass = maccrd->crd_skip; 1155 oplen = bypass + maccrd->crd_len; 1156 } 1157 coffset = 0; 1158 } 1159 /* XXX verify multiple of 4 when using s/g */ 1160 if (bypass > 96) { /* bypass offset must be <= 96 bytes */ 1161 DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); 1162 safestats.st_bypasstoobig++; 1163 err = EINVAL; 1164 goto errout; 1165 } 1166 1167 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) { 1168 safestats.st_nomap++; 1169 err = ENOMEM; 1170 goto errout; 1171 } 1172 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1173 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map, 1174 re->re_src_m, safe_op_cb, 1175 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1176 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1177 re->re_src_map = NULL; 1178 safestats.st_noload++; 1179 err = ENOMEM; 1180 goto errout; 1181 } 1182 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1183 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map, 1184 re->re_src_io, safe_op_cb, 1185 &re->re_src, BUS_DMA_NOWAIT) != 0) { 1186 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1187 re->re_src_map = NULL; 1188 safestats.st_noload++; 1189 err = ENOMEM; 1190 goto errout; 1191 } 1192 } 1193 nicealign = safe_dmamap_aligned(&re->re_src); 1194 uniform = safe_dmamap_uniform(&re->re_src); 1195 1196 DPRINTF(("src nicealign %u uniform %u nsegs %u\n", 1197 nicealign, uniform, re->re_src.nsegs)); 1198 if (re->re_src.nsegs > 1) { 1199 re->re_desc.d_src = sc->sc_spalloc.dma_paddr + 1200 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); 1201 for (i = 0; i < re->re_src_nsegs; i++) { 1202 /* NB: no need to check if there's space */ 1203 pd = sc->sc_spfree; 1204 if (++(sc->sc_spfree) == sc->sc_springtop) 1205 sc->sc_spfree = sc->sc_spring; 1206 1207 KASSERT((pd->pd_flags&3) == 0 || 1208 (pd->pd_flags&3) == SAFE_PD_DONE, 1209 ("bogus source particle descriptor; flags %x", 1210 pd->pd_flags)); 1211 pd->pd_addr = re->re_src_segs[i].ds_addr; 1212 pd->pd_size = re->re_src_segs[i].ds_len; 1213 pd->pd_flags = SAFE_PD_READY; 1214 } 1215 cmd0 |= SAFE_SA_CMD0_IGATHER; 1216 } else { 1217 /* 1218 * No need for gather, reference the operand directly. 1219 */ 1220 re->re_desc.d_src = re->re_src_segs[0].ds_addr; 1221 } 1222 1223 if (enccrd == NULL && maccrd != NULL) { 1224 /* 1225 * Hash op; no destination needed. 1226 */ 1227 } else { 1228 if (crp->crp_flags & CRYPTO_F_IOV) { 1229 if (!nicealign) { 1230 safestats.st_iovmisaligned++; 1231 err = EINVAL; 1232 goto errout; 1233 } 1234 if (uniform != 1) { 1235 /* 1236 * Source is not suitable for direct use as 1237 * the destination. Create a new scatter/gather 1238 * list based on the destination requirements 1239 * and check if that's ok. 1240 */ 1241 if (bus_dmamap_create(sc->sc_dstdmat, 1242 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1243 safestats.st_nomap++; 1244 err = ENOMEM; 1245 goto errout; 1246 } 1247 if (bus_dmamap_load_uio(sc->sc_dstdmat, 1248 re->re_dst_map, re->re_dst_io, 1249 safe_op_cb, &re->re_dst, 1250 BUS_DMA_NOWAIT) != 0) { 1251 bus_dmamap_destroy(sc->sc_dstdmat, 1252 re->re_dst_map); 1253 re->re_dst_map = NULL; 1254 safestats.st_noload++; 1255 err = ENOMEM; 1256 goto errout; 1257 } 1258 uniform = safe_dmamap_uniform(&re->re_dst); 1259 if (!uniform) { 1260 /* 1261 * There's no way to handle the DMA 1262 * requirements with this uio. We 1263 * could create a separate DMA area for 1264 * the result and then copy it back, 1265 * but for now we just bail and return 1266 * an error. Note that uio requests 1267 * > SAFE_MAX_DSIZE are handled because 1268 * the DMA map and segment list for the 1269 * destination wil result in a 1270 * destination particle list that does 1271 * the necessary scatter DMA. 1272 */ 1273 safestats.st_iovnotuniform++; 1274 err = EINVAL; 1275 goto errout; 1276 } 1277 } else 1278 re->re_dst = re->re_src; 1279 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1280 if (nicealign && uniform == 1) { 1281 /* 1282 * Source layout is suitable for direct 1283 * sharing of the DMA map and segment list. 1284 */ 1285 re->re_dst = re->re_src; 1286 } else if (nicealign && uniform == 2) { 1287 /* 1288 * The source is properly aligned but requires a 1289 * different particle list to handle DMA of the 1290 * result. Create a new map and do the load to 1291 * create the segment list. The particle 1292 * descriptor setup code below will handle the 1293 * rest. 1294 */ 1295 if (bus_dmamap_create(sc->sc_dstdmat, 1296 BUS_DMA_NOWAIT, &re->re_dst_map)) { 1297 safestats.st_nomap++; 1298 err = ENOMEM; 1299 goto errout; 1300 } 1301 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1302 re->re_dst_map, re->re_dst_m, 1303 safe_op_cb, &re->re_dst, 1304 BUS_DMA_NOWAIT) != 0) { 1305 bus_dmamap_destroy(sc->sc_dstdmat, 1306 re->re_dst_map); 1307 re->re_dst_map = NULL; 1308 safestats.st_noload++; 1309 err = ENOMEM; 1310 goto errout; 1311 } 1312 } else { /* !(aligned and/or uniform) */ 1313 int totlen, len; 1314 struct mbuf *m, *top, **mp; 1315 1316 /* 1317 * DMA constraints require that we allocate a 1318 * new mbuf chain for the destination. We 1319 * allocate an entire new set of mbufs of 1320 * optimal/required size and then tell the 1321 * hardware to copy any bits that are not 1322 * created as a byproduct of the operation. 1323 */ 1324 if (!nicealign) 1325 safestats.st_unaligned++; 1326 if (!uniform) 1327 safestats.st_notuniform++; 1328 totlen = re->re_src_mapsize; 1329 if (re->re_src_m->m_flags & M_PKTHDR) { 1330 len = MHLEN; 1331 MGETHDR(m, M_DONTWAIT, MT_DATA); 1332 if (m && !m_dup_pkthdr(m, re->re_src_m, 1333 M_DONTWAIT)) { 1334 m_free(m); 1335 m = NULL; 1336 } 1337 } else { 1338 len = MLEN; 1339 MGET(m, M_DONTWAIT, MT_DATA); 1340 } 1341 if (m == NULL) { 1342 safestats.st_nombuf++; 1343 err = sc->sc_nqchip ? ERESTART : ENOMEM; 1344 goto errout; 1345 } 1346 if (totlen >= MINCLSIZE) { 1347 MCLGET(m, M_DONTWAIT); 1348 if ((m->m_flags & M_EXT) == 0) { 1349 m_free(m); 1350 safestats.st_nomcl++; 1351 err = sc->sc_nqchip ? 1352 ERESTART : ENOMEM; 1353 goto errout; 1354 } 1355 len = MCLBYTES; 1356 } 1357 m->m_len = len; 1358 top = NULL; 1359 mp = ⊤ 1360 1361 while (totlen > 0) { 1362 if (top) { 1363 MGET(m, M_DONTWAIT, MT_DATA); 1364 if (m == NULL) { 1365 m_freem(top); 1366 safestats.st_nombuf++; 1367 err = sc->sc_nqchip ? 1368 ERESTART : ENOMEM; 1369 goto errout; 1370 } 1371 len = MLEN; 1372 } 1373 if (top && totlen >= MINCLSIZE) { 1374 MCLGET(m, M_DONTWAIT); 1375 if ((m->m_flags & M_EXT) == 0) { 1376 *mp = m; 1377 m_freem(top); 1378 safestats.st_nomcl++; 1379 err = sc->sc_nqchip ? 1380 ERESTART : ENOMEM; 1381 goto errout; 1382 } 1383 len = MCLBYTES; 1384 } 1385 m->m_len = len = min(totlen, len); 1386 totlen -= len; 1387 *mp = m; 1388 mp = &m->m_next; 1389 } 1390 re->re_dst_m = top; 1391 if (bus_dmamap_create(sc->sc_dstdmat, 1392 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) { 1393 safestats.st_nomap++; 1394 err = ENOMEM; 1395 goto errout; 1396 } 1397 if (bus_dmamap_load_mbuf(sc->sc_dstdmat, 1398 re->re_dst_map, re->re_dst_m, 1399 safe_op_cb, &re->re_dst, 1400 BUS_DMA_NOWAIT) != 0) { 1401 bus_dmamap_destroy(sc->sc_dstdmat, 1402 re->re_dst_map); 1403 re->re_dst_map = NULL; 1404 safestats.st_noload++; 1405 err = ENOMEM; 1406 goto errout; 1407 } 1408 if (re->re_src.mapsize > oplen) { 1409 /* 1410 * There's data following what the 1411 * hardware will copy for us. If this 1412 * isn't just the ICV (that's going to 1413 * be written on completion), copy it 1414 * to the new mbufs 1415 */ 1416 if (!(maccrd && 1417 (re->re_src.mapsize-oplen) == 12 && 1418 maccrd->crd_inject == oplen)) 1419 safe_mcopy(re->re_src_m, 1420 re->re_dst_m, 1421 oplen); 1422 else 1423 safestats.st_noicvcopy++; 1424 } 1425 } 1426 } else { 1427 safestats.st_badflags++; 1428 err = EINVAL; 1429 goto errout; 1430 } 1431 1432 if (re->re_dst.nsegs > 1) { 1433 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + 1434 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); 1435 for (i = 0; i < re->re_dst_nsegs; i++) { 1436 pd = sc->sc_dpfree; 1437 KASSERT((pd->pd_flags&3) == 0 || 1438 (pd->pd_flags&3) == SAFE_PD_DONE, 1439 ("bogus dest particle descriptor; flags %x", 1440 pd->pd_flags)); 1441 if (++(sc->sc_dpfree) == sc->sc_dpringtop) 1442 sc->sc_dpfree = sc->sc_dpring; 1443 pd->pd_addr = re->re_dst_segs[i].ds_addr; 1444 pd->pd_flags = SAFE_PD_READY; 1445 } 1446 cmd0 |= SAFE_SA_CMD0_OSCATTER; 1447 } else { 1448 /* 1449 * No need for scatter, reference the operand directly. 1450 */ 1451 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; 1452 } 1453 } 1454 1455 /* 1456 * All done with setup; fillin the SA command words 1457 * and the packet engine descriptor. The operation 1458 * is now ready for submission to the hardware. 1459 */ 1460 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; 1461 sa->sa_cmd1 = cmd1 1462 | (coffset << SAFE_SA_CMD1_OFFSET_S) 1463 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ 1464 | SAFE_SA_CMD1_SRPCI 1465 ; 1466 /* 1467 * NB: the order of writes is important here. In case the 1468 * chip is scanning the ring because of an outstanding request 1469 * it might nab this one too. In that case we need to make 1470 * sure the setup is complete before we write the length 1471 * field of the descriptor as it signals the descriptor is 1472 * ready for processing. 1473 */ 1474 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; 1475 if (maccrd) 1476 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; 1477 re->re_desc.d_len = oplen 1478 | SAFE_PE_LEN_READY 1479 | (bypass << SAFE_PE_LEN_BYPASS_S) 1480 ; 1481 1482 safestats.st_ipackets++; 1483 safestats.st_ibytes += oplen; 1484 1485 if (++(sc->sc_front) == sc->sc_ringtop) 1486 sc->sc_front = sc->sc_ring; 1487 1488 /* XXX honor batching */ 1489 safe_feed(sc, re); 1490 mtx_unlock(&sc->sc_ringmtx); 1491 return (0); 1492 1493 errout: 1494 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 1495 m_freem(re->re_dst_m); 1496 1497 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1498 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1499 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1500 } 1501 if (re->re_src_map != NULL) { 1502 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1503 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1504 } 1505 mtx_unlock(&sc->sc_ringmtx); 1506 if (err != ERESTART) { 1507 crp->crp_etype = err; 1508 crypto_done(crp); 1509 } else { 1510 sc->sc_needwakeup |= CRYPTO_SYMQ; 1511 } 1512 return (err); 1513 } 1514 1515 static void 1516 safe_callback(struct safe_softc *sc, struct safe_ringentry *re) 1517 { 1518 struct cryptop *crp = (struct cryptop *)re->re_crp; 1519 struct cryptodesc *crd; 1520 1521 safestats.st_opackets++; 1522 safestats.st_obytes += re->re_dst.mapsize; 1523 1524 safe_dma_sync(&sc->sc_ringalloc, 1525 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1526 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { 1527 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", 1528 re->re_desc.d_csr, 1529 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); 1530 safestats.st_peoperr++; 1531 crp->crp_etype = EIO; /* something more meaningful? */ 1532 } 1533 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) { 1534 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map, 1535 BUS_DMASYNC_POSTREAD); 1536 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map); 1537 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map); 1538 } 1539 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE); 1540 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map); 1541 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map); 1542 1543 /* 1544 * If result was written to a differet mbuf chain, swap 1545 * it in as the return value and reclaim the original. 1546 */ 1547 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) { 1548 m_freem(re->re_src_m); 1549 crp->crp_buf = (caddr_t)re->re_dst_m; 1550 } 1551 1552 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { 1553 /* copy out IV for future use */ 1554 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1555 int ivsize; 1556 1557 if (crd->crd_alg == CRYPTO_DES_CBC || 1558 crd->crd_alg == CRYPTO_3DES_CBC) { 1559 ivsize = 2*sizeof(u_int32_t); 1560 } else if (crd->crd_alg == CRYPTO_AES_CBC) { 1561 ivsize = 4*sizeof(u_int32_t); 1562 } else 1563 continue; 1564 crypto_copydata(crp->crp_flags, crp->crp_buf, 1565 crd->crd_skip + crd->crd_len - ivsize, ivsize, 1566 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); 1567 break; 1568 } 1569 } 1570 1571 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { 1572 /* copy out ICV result */ 1573 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1574 if (!(crd->crd_alg == CRYPTO_MD5_HMAC || 1575 crd->crd_alg == CRYPTO_SHA1_HMAC || 1576 crd->crd_alg == CRYPTO_NULL_HMAC)) 1577 continue; 1578 if (crd->crd_alg == CRYPTO_SHA1_HMAC) { 1579 /* 1580 * SHA-1 ICV's are byte-swapped; fix 'em up 1581 * before copy them to their destination. 1582 */ 1583 bswap32(re->re_sastate.sa_saved_indigest[0]); 1584 bswap32(re->re_sastate.sa_saved_indigest[1]); 1585 bswap32(re->re_sastate.sa_saved_indigest[2]); 1586 } 1587 crypto_copyback(crp->crp_flags, crp->crp_buf, 1588 crd->crd_inject, 1589 sc->sc_sessions[re->re_sesn].ses_mlen, 1590 (caddr_t)re->re_sastate.sa_saved_indigest); 1591 break; 1592 } 1593 } 1594 crypto_done(crp); 1595 } 1596 1597 /* 1598 * Copy all data past offset from srcm to dstm. 1599 */ 1600 static void 1601 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset) 1602 { 1603 u_int j, dlen, slen; 1604 caddr_t dptr, sptr; 1605 1606 /* 1607 * Advance src and dst to offset. 1608 */ 1609 j = offset; 1610 while (j >= 0) { 1611 if (srcm->m_len > j) 1612 break; 1613 j -= srcm->m_len; 1614 srcm = srcm->m_next; 1615 if (srcm == NULL) 1616 return; 1617 } 1618 sptr = mtod(srcm, caddr_t) + j; 1619 slen = srcm->m_len - j; 1620 1621 j = offset; 1622 while (j >= 0) { 1623 if (dstm->m_len > j) 1624 break; 1625 j -= dstm->m_len; 1626 dstm = dstm->m_next; 1627 if (dstm == NULL) 1628 return; 1629 } 1630 dptr = mtod(dstm, caddr_t) + j; 1631 dlen = dstm->m_len - j; 1632 1633 /* 1634 * Copy everything that remains. 1635 */ 1636 for (;;) { 1637 j = min(slen, dlen); 1638 bcopy(sptr, dptr, j); 1639 if (slen == j) { 1640 srcm = srcm->m_next; 1641 if (srcm == NULL) 1642 return; 1643 sptr = srcm->m_data; 1644 slen = srcm->m_len; 1645 } else 1646 sptr += j, slen -= j; 1647 if (dlen == j) { 1648 dstm = dstm->m_next; 1649 if (dstm == NULL) 1650 return; 1651 dptr = dstm->m_data; 1652 dlen = dstm->m_len; 1653 } else 1654 dptr += j, dlen -= j; 1655 } 1656 } 1657 1658 #ifndef SAFE_NO_RNG 1659 #define SAFE_RNG_MAXWAIT 1000 1660 1661 static void 1662 safe_rng_init(struct safe_softc *sc) 1663 { 1664 u_int32_t w, v; 1665 int i; 1666 1667 WRITE_REG(sc, SAFE_RNG_CTRL, 0); 1668 /* use default value according to the manual */ 1669 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ 1670 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1671 1672 /* 1673 * There is a bug in rev 1.0 of the 1140 that when the RNG 1674 * is brought out of reset the ready status flag does not 1675 * work until the RNG has finished its internal initialization. 1676 * 1677 * So in order to determine the device is through its 1678 * initialization we must read the data register, using the 1679 * status reg in the read in case it is initialized. Then read 1680 * the data register until it changes from the first read. 1681 * Once it changes read the data register until it changes 1682 * again. At this time the RNG is considered initialized. 1683 * This could take between 750ms - 1000ms in time. 1684 */ 1685 i = 0; 1686 w = READ_REG(sc, SAFE_RNG_OUT); 1687 do { 1688 v = READ_REG(sc, SAFE_RNG_OUT); 1689 if (v != w) { 1690 w = v; 1691 break; 1692 } 1693 DELAY(10); 1694 } while (++i < SAFE_RNG_MAXWAIT); 1695 1696 /* Wait Until data changes again */ 1697 i = 0; 1698 do { 1699 v = READ_REG(sc, SAFE_RNG_OUT); 1700 if (v != w) 1701 break; 1702 DELAY(10); 1703 } while (++i < SAFE_RNG_MAXWAIT); 1704 } 1705 1706 static __inline void 1707 safe_rng_disable_short_cycle(struct safe_softc *sc) 1708 { 1709 WRITE_REG(sc, SAFE_RNG_CTRL, 1710 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); 1711 } 1712 1713 static __inline void 1714 safe_rng_enable_short_cycle(struct safe_softc *sc) 1715 { 1716 WRITE_REG(sc, SAFE_RNG_CTRL, 1717 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); 1718 } 1719 1720 static __inline u_int32_t 1721 safe_rng_read(struct safe_softc *sc) 1722 { 1723 int i; 1724 1725 i = 0; 1726 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) 1727 ; 1728 return READ_REG(sc, SAFE_RNG_OUT); 1729 } 1730 1731 static void 1732 safe_rng(void *arg) 1733 { 1734 struct safe_softc *sc = arg; 1735 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */ 1736 u_int maxwords; 1737 int i; 1738 1739 safestats.st_rng++; 1740 /* 1741 * Fetch the next block of data. 1742 */ 1743 maxwords = safe_rngbufsize; 1744 if (maxwords > SAFE_RNG_MAXBUFSIZ) 1745 maxwords = SAFE_RNG_MAXBUFSIZ; 1746 retry: 1747 for (i = 0; i < maxwords; i++) 1748 buf[i] = safe_rng_read(sc); 1749 /* 1750 * Check the comparator alarm count and reset the h/w if 1751 * it exceeds our threshold. This guards against the 1752 * hardware oscillators resonating with external signals. 1753 */ 1754 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { 1755 u_int32_t freq_inc, w; 1756 1757 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, 1758 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); 1759 safestats.st_rngalarm++; 1760 safe_rng_enable_short_cycle(sc); 1761 freq_inc = 18; 1762 for (i = 0; i < 64; i++) { 1763 w = READ_REG(sc, SAFE_RNG_CNFG); 1764 freq_inc = ((w + freq_inc) & 0x3fL); 1765 w = ((w & ~0x3fL) | freq_inc); 1766 WRITE_REG(sc, SAFE_RNG_CNFG, w); 1767 1768 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1769 1770 (void) safe_rng_read(sc); 1771 DELAY(25); 1772 1773 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { 1774 safe_rng_disable_short_cycle(sc); 1775 goto retry; 1776 } 1777 freq_inc = 1; 1778 } 1779 safe_rng_disable_short_cycle(sc); 1780 } else 1781 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); 1782 1783 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t)); 1784 callout_reset(&sc->sc_rngto, 1785 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc); 1786 } 1787 #endif /* SAFE_NO_RNG */ 1788 1789 static void 1790 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1791 { 1792 bus_addr_t *paddr = (bus_addr_t*) arg; 1793 *paddr = segs->ds_addr; 1794 } 1795 1796 static int 1797 safe_dma_malloc( 1798 struct safe_softc *sc, 1799 bus_size_t size, 1800 struct safe_dma_alloc *dma, 1801 int mapflags 1802 ) 1803 { 1804 int r; 1805 1806 r = bus_dma_tag_create(NULL, /* parent */ 1807 sizeof(u_int32_t), 0, /* alignment, bounds */ 1808 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1809 BUS_SPACE_MAXADDR, /* highaddr */ 1810 NULL, NULL, /* filter, filterarg */ 1811 size, /* maxsize */ 1812 1, /* nsegments */ 1813 size, /* maxsegsize */ 1814 BUS_DMA_ALLOCNOW, /* flags */ 1815 NULL, NULL, /* locking */ 1816 &dma->dma_tag); 1817 if (r != 0) { 1818 device_printf(sc->sc_dev, "safe_dma_malloc: " 1819 "bus_dma_tag_create failed; error %u\n", r); 1820 goto fail_0; 1821 } 1822 1823 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1824 if (r != 0) { 1825 device_printf(sc->sc_dev, "safe_dma_malloc: " 1826 "bus_dmamap_create failed; error %u\n", r); 1827 goto fail_1; 1828 } 1829 1830 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1831 BUS_DMA_NOWAIT, &dma->dma_map); 1832 if (r != 0) { 1833 device_printf(sc->sc_dev, "safe_dma_malloc: " 1834 "bus_dmammem_alloc failed; size %zu, error %u\n", 1835 size, r); 1836 goto fail_2; 1837 } 1838 1839 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1840 size, 1841 safe_dmamap_cb, 1842 &dma->dma_paddr, 1843 mapflags | BUS_DMA_NOWAIT); 1844 if (r != 0) { 1845 device_printf(sc->sc_dev, "safe_dma_malloc: " 1846 "bus_dmamap_load failed; error %u\n", r); 1847 goto fail_3; 1848 } 1849 1850 dma->dma_size = size; 1851 return (0); 1852 1853 fail_3: 1854 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1855 fail_2: 1856 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1857 fail_1: 1858 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1859 bus_dma_tag_destroy(dma->dma_tag); 1860 fail_0: 1861 dma->dma_map = NULL; 1862 dma->dma_tag = NULL; 1863 return (r); 1864 } 1865 1866 static void 1867 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma) 1868 { 1869 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1870 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1871 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1872 bus_dma_tag_destroy(dma->dma_tag); 1873 } 1874 1875 /* 1876 * Resets the board. Values in the regesters are left as is 1877 * from the reset (i.e. initial values are assigned elsewhere). 1878 */ 1879 static void 1880 safe_reset_board(struct safe_softc *sc) 1881 { 1882 u_int32_t v; 1883 /* 1884 * Reset the device. The manual says no delay 1885 * is needed between marking and clearing reset. 1886 */ 1887 v = READ_REG(sc, SAFE_PE_DMACFG) &~ 1888 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | 1889 SAFE_PE_DMACFG_SGRESET); 1890 WRITE_REG(sc, SAFE_PE_DMACFG, v 1891 | SAFE_PE_DMACFG_PERESET 1892 | SAFE_PE_DMACFG_PDRRESET 1893 | SAFE_PE_DMACFG_SGRESET); 1894 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1895 } 1896 1897 /* 1898 * Initialize registers we need to touch only once. 1899 */ 1900 static void 1901 safe_init_board(struct safe_softc *sc) 1902 { 1903 u_int32_t v, dwords; 1904 1905 v = READ_REG(sc, SAFE_PE_DMACFG);; 1906 v &=~ SAFE_PE_DMACFG_PEMODE; 1907 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ 1908 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ 1909 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ 1910 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ 1911 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ 1912 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ 1913 ; 1914 WRITE_REG(sc, SAFE_PE_DMACFG, v); 1915 #if 0 1916 /* XXX select byte swap based on host byte order */ 1917 WRITE_REG(sc, SAFE_ENDIAN, 0x1b); 1918 #endif 1919 if (sc->sc_chiprev == SAFE_REV(1,0)) { 1920 /* 1921 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where 1922 * "target mode transfers" done while the chip is DMA'ing 1923 * >1020 bytes cause the hardware to lockup. To avoid this 1924 * we reduce the max PCI transfer size and use small source 1925 * particle descriptors (<= 256 bytes). 1926 */ 1927 WRITE_REG(sc, SAFE_DMA_CFG, 256); 1928 device_printf(sc->sc_dev, 1929 "Reduce max DMA size to %u words for rev %u.%u WAR\n", 1930 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff, 1931 SAFE_REV_MAJ(sc->sc_chiprev), 1932 SAFE_REV_MIN(sc->sc_chiprev)); 1933 } 1934 1935 /* NB: operands+results are overlaid */ 1936 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); 1937 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); 1938 /* 1939 * Configure ring entry size and number of items in the ring. 1940 */ 1941 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, 1942 ("PE ring entry not 32-bit aligned!")); 1943 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); 1944 WRITE_REG(sc, SAFE_PE_RINGCFG, 1945 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); 1946 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ 1947 1948 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); 1949 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); 1950 WRITE_REG(sc, SAFE_PE_PARTSIZE, 1951 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); 1952 /* 1953 * NB: destination particles are fixed size. We use 1954 * an mbuf cluster and require all results go to 1955 * clusters or smaller. 1956 */ 1957 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE); 1958 1959 /* it's now safe to enable PE mode, do it */ 1960 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); 1961 1962 /* 1963 * Configure hardware to use level-triggered interrupts and 1964 * to interrupt after each descriptor is processed. 1965 */ 1966 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); 1967 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); 1968 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); 1969 } 1970 1971 /* 1972 * Init PCI registers 1973 */ 1974 static void 1975 safe_init_pciregs(device_t dev) 1976 { 1977 } 1978 1979 /* 1980 * Clean up after a chip crash. 1981 * It is assumed that the caller in splimp() 1982 */ 1983 static void 1984 safe_cleanchip(struct safe_softc *sc) 1985 { 1986 1987 if (sc->sc_nqchip != 0) { 1988 struct safe_ringentry *re = sc->sc_back; 1989 1990 while (re != sc->sc_front) { 1991 if (re->re_desc.d_csr != 0) 1992 safe_free_entry(sc, re); 1993 if (++re == sc->sc_ringtop) 1994 re = sc->sc_ring; 1995 } 1996 sc->sc_back = re; 1997 sc->sc_nqchip = 0; 1998 } 1999 } 2000 2001 /* 2002 * free a safe_q 2003 * It is assumed that the caller is within splimp(). 2004 */ 2005 static int 2006 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) 2007 { 2008 struct cryptop *crp; 2009 2010 /* 2011 * Free header MCR 2012 */ 2013 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m)) 2014 m_freem(re->re_dst_m); 2015 2016 crp = (struct cryptop *)re->re_crp; 2017 2018 re->re_desc.d_csr = 0; 2019 2020 crp->crp_etype = EFAULT; 2021 crypto_done(crp); 2022 return(0); 2023 } 2024 2025 /* 2026 * Routine to reset the chip and clean up. 2027 * It is assumed that the caller is in splimp() 2028 */ 2029 static void 2030 safe_totalreset(struct safe_softc *sc) 2031 { 2032 safe_reset_board(sc); 2033 safe_init_board(sc); 2034 safe_cleanchip(sc); 2035 } 2036 2037 /* 2038 * Is the operand suitable aligned for direct DMA. Each 2039 * segment must be aligned on a 32-bit boundary and all 2040 * but the last segment must be a multiple of 4 bytes. 2041 */ 2042 static int 2043 safe_dmamap_aligned(const struct safe_operand *op) 2044 { 2045 int i; 2046 2047 for (i = 0; i < op->nsegs; i++) { 2048 if (op->segs[i].ds_addr & 3) 2049 return (0); 2050 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) 2051 return (0); 2052 } 2053 return (1); 2054 } 2055 2056 /* 2057 * Is the operand suitable for direct DMA as the destination 2058 * of an operation. The hardware requires that each ``particle'' 2059 * but the last in an operation result have the same size. We 2060 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns 2061 * 0 if some segment is not a multiple of of this size, 1 if all 2062 * segments are exactly this size, or 2 if segments are at worst 2063 * a multple of this size. 2064 */ 2065 static int 2066 safe_dmamap_uniform(const struct safe_operand *op) 2067 { 2068 int result = 1; 2069 2070 if (op->nsegs > 0) { 2071 int i; 2072 2073 for (i = 0; i < op->nsegs-1; i++) { 2074 if (op->segs[i].ds_len % SAFE_MAX_DSIZE) 2075 return (0); 2076 if (op->segs[i].ds_len != SAFE_MAX_DSIZE) 2077 result = 2; 2078 } 2079 } 2080 return (result); 2081 } 2082 2083 #ifdef SAFE_DEBUG 2084 static void 2085 safe_dump_dmastatus(struct safe_softc *sc, const char *tag) 2086 { 2087 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" 2088 , tag 2089 , READ_REG(sc, SAFE_DMA_ENDIAN) 2090 , READ_REG(sc, SAFE_DMA_SRCADDR) 2091 , READ_REG(sc, SAFE_DMA_DSTADDR) 2092 , READ_REG(sc, SAFE_DMA_STAT) 2093 ); 2094 } 2095 2096 static void 2097 safe_dump_intrstate(struct safe_softc *sc, const char *tag) 2098 { 2099 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" 2100 , tag 2101 , READ_REG(sc, SAFE_HI_CFG) 2102 , READ_REG(sc, SAFE_HI_MASK) 2103 , READ_REG(sc, SAFE_HI_DESC_CNT) 2104 , READ_REG(sc, SAFE_HU_STAT) 2105 , READ_REG(sc, SAFE_HM_STAT) 2106 ); 2107 } 2108 2109 static void 2110 safe_dump_ringstate(struct safe_softc *sc, const char *tag) 2111 { 2112 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); 2113 2114 /* NB: assume caller has lock on ring */ 2115 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", 2116 tag, 2117 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), 2118 (unsigned long)(sc->sc_back - sc->sc_ring), 2119 (unsigned long)(sc->sc_front - sc->sc_ring)); 2120 } 2121 2122 static void 2123 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) 2124 { 2125 int ix, nsegs; 2126 2127 ix = re - sc->sc_ring; 2128 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" 2129 , tag 2130 , re, ix 2131 , re->re_desc.d_csr 2132 , re->re_desc.d_src 2133 , re->re_desc.d_dst 2134 , re->re_desc.d_sa 2135 , re->re_desc.d_len 2136 ); 2137 if (re->re_src.nsegs > 1) { 2138 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / 2139 sizeof(struct safe_pdesc); 2140 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { 2141 printf(" spd[%u] %p: %p size %u flags %x" 2142 , ix, &sc->sc_spring[ix] 2143 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr 2144 , sc->sc_spring[ix].pd_size 2145 , sc->sc_spring[ix].pd_flags 2146 ); 2147 if (sc->sc_spring[ix].pd_size == 0) 2148 printf(" (zero!)"); 2149 printf("\n"); 2150 if (++ix == SAFE_TOTAL_SPART) 2151 ix = 0; 2152 } 2153 } 2154 if (re->re_dst.nsegs > 1) { 2155 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / 2156 sizeof(struct safe_pdesc); 2157 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { 2158 printf(" dpd[%u] %p: %p flags %x\n" 2159 , ix, &sc->sc_dpring[ix] 2160 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr 2161 , sc->sc_dpring[ix].pd_flags 2162 ); 2163 if (++ix == SAFE_TOTAL_DPART) 2164 ix = 0; 2165 } 2166 } 2167 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", 2168 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); 2169 printf("sa: key %x %x %x %x %x %x %x %x\n" 2170 , re->re_sa.sa_key[0] 2171 , re->re_sa.sa_key[1] 2172 , re->re_sa.sa_key[2] 2173 , re->re_sa.sa_key[3] 2174 , re->re_sa.sa_key[4] 2175 , re->re_sa.sa_key[5] 2176 , re->re_sa.sa_key[6] 2177 , re->re_sa.sa_key[7] 2178 ); 2179 printf("sa: indigest %x %x %x %x %x\n" 2180 , re->re_sa.sa_indigest[0] 2181 , re->re_sa.sa_indigest[1] 2182 , re->re_sa.sa_indigest[2] 2183 , re->re_sa.sa_indigest[3] 2184 , re->re_sa.sa_indigest[4] 2185 ); 2186 printf("sa: outdigest %x %x %x %x %x\n" 2187 , re->re_sa.sa_outdigest[0] 2188 , re->re_sa.sa_outdigest[1] 2189 , re->re_sa.sa_outdigest[2] 2190 , re->re_sa.sa_outdigest[3] 2191 , re->re_sa.sa_outdigest[4] 2192 ); 2193 printf("sr: iv %x %x %x %x\n" 2194 , re->re_sastate.sa_saved_iv[0] 2195 , re->re_sastate.sa_saved_iv[1] 2196 , re->re_sastate.sa_saved_iv[2] 2197 , re->re_sastate.sa_saved_iv[3] 2198 ); 2199 printf("sr: hashbc %u indigest %x %x %x %x %x\n" 2200 , re->re_sastate.sa_saved_hashbc 2201 , re->re_sastate.sa_saved_indigest[0] 2202 , re->re_sastate.sa_saved_indigest[1] 2203 , re->re_sastate.sa_saved_indigest[2] 2204 , re->re_sastate.sa_saved_indigest[3] 2205 , re->re_sastate.sa_saved_indigest[4] 2206 ); 2207 } 2208 2209 static void 2210 safe_dump_ring(struct safe_softc *sc, const char *tag) 2211 { 2212 mtx_lock(&sc->sc_ringmtx); 2213 printf("\nSafeNet Ring State:\n"); 2214 safe_dump_intrstate(sc, tag); 2215 safe_dump_dmastatus(sc, tag); 2216 safe_dump_ringstate(sc, tag); 2217 if (sc->sc_nqchip) { 2218 struct safe_ringentry *re = sc->sc_back; 2219 do { 2220 safe_dump_request(sc, tag, re); 2221 if (++re == sc->sc_ringtop) 2222 re = sc->sc_ring; 2223 } while (re != sc->sc_front); 2224 } 2225 mtx_unlock(&sc->sc_ringmtx); 2226 } 2227 2228 static int 2229 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS) 2230 { 2231 char dmode[64]; 2232 int error; 2233 2234 strncpy(dmode, "", sizeof(dmode) - 1); 2235 dmode[sizeof(dmode) - 1] = '\0'; 2236 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req); 2237 2238 if (error == 0 && req->newptr != NULL) { 2239 struct safe_softc *sc = safec; 2240 2241 if (!sc) 2242 return EINVAL; 2243 if (strncmp(dmode, "dma", 3) == 0) 2244 safe_dump_dmastatus(sc, "safe0"); 2245 else if (strncmp(dmode, "int", 3) == 0) 2246 safe_dump_intrstate(sc, "safe0"); 2247 else if (strncmp(dmode, "ring", 4) == 0) 2248 safe_dump_ring(sc, "safe0"); 2249 else 2250 return EINVAL; 2251 } 2252 return error; 2253 } 2254 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW, 2255 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state"); 2256 #endif /* SAFE_DEBUG */ 2257