1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 32 #include <sys/param.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 46 #include <net/if.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/rtwn/if_rtwnreg.h> 54 #include <dev/rtwn/if_rtwnvar.h> 55 56 #include <dev/rtwn/if_rtwn_debug.h> 57 58 #include <dev/rtwn/rtl8812a/r12a_var.h> 59 60 #include <dev/rtwn/rtl8821a/r21a.h> 61 #include <dev/rtwn/rtl8821a/r21a_priv.h> 62 #include <dev/rtwn/rtl8821a/r21a_reg.h> 63 64 65 int 66 r21a_power_on(struct rtwn_softc *sc) 67 { 68 #define RTWN_CHK(res) do { \ 69 if (res != 0) \ 70 return (EIO); \ 71 } while(0) 72 int ntries; 73 74 /* Clear suspend and power down bits.*/ 75 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 76 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_APDM_HPDN, 0, 1)); 77 78 /* Disable GPIO9 as EXT WAKEUP. */ 79 RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0x01, 0)); 80 81 /* Enable WL suspend. */ 82 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 83 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1)); 84 85 /* Enable LDOA12 MACRO block for all interfaces. */ 86 RTWN_CHK(rtwn_setbits_1(sc, R92C_LDOA15_CTRL, 0, R92C_LDOA15_CTRL_EN)); 87 88 /* Disable BT_GPS_SEL pins. */ 89 RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0x10, 0)); 90 91 /* 1 ms delay. */ 92 rtwn_delay(sc, 1000); 93 94 /* Release analog Ips to digital isolation. */ 95 RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL, 96 R92C_SYS_ISO_CTRL_IP2MAC, 0)); 97 98 /* Disable SW LPS and WL suspend. */ 99 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 100 R92C_APS_FSMCO_APFM_RSM | 101 R92C_APS_FSMCO_AFSM_HSUS | 102 R92C_APS_FSMCO_AFSM_PCIE, 0, 1)); 103 104 /* Wait for power ready bit. */ 105 for (ntries = 0; ntries < 5000; ntries++) { 106 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 107 break; 108 rtwn_delay(sc, 10); 109 } 110 if (ntries == 5000) { 111 device_printf(sc->sc_dev, 112 "timeout waiting for chip power up\n"); 113 return (ETIMEDOUT); 114 } 115 116 /* Release WLON reset. */ 117 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 118 R92C_APS_FSMCO_RDY_MACON, 2)); 119 120 /* Disable HWPDN. */ 121 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 122 R92C_APS_FSMCO_APDM_HPDN, 0, 1)); 123 124 /* Disable WL suspend. */ 125 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 126 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1)); 127 128 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 129 R92C_APS_FSMCO_APFM_ONMAC, 1)); 130 for (ntries = 0; ntries < 5000; ntries++) { 131 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 132 R92C_APS_FSMCO_APFM_ONMAC)) 133 break; 134 rtwn_delay(sc, 10); 135 } 136 if (ntries == 5000) 137 return (ETIMEDOUT); 138 139 /* Switch DPDT_SEL_P output from WL BB. */ 140 RTWN_CHK(rtwn_setbits_1(sc, R92C_LEDCFG3, 0, 0x01)); 141 142 /* switch for PAPE_G/PAPE_A from WL BB; switch LNAON from WL BB. */ 143 RTWN_CHK(rtwn_setbits_1(sc, 0x067, 0, 0x30)); 144 145 RTWN_CHK(rtwn_setbits_1(sc, 0x025, 0x40, 0)); 146 147 /* Enable falling edge triggering interrupt. */ 148 RTWN_CHK(rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0, 0x02)); 149 150 /* Enable GPIO9 interrupt mode. */ 151 RTWN_CHK(rtwn_setbits_1(sc, 0x063, 0, 0x02)); 152 153 /* Enable GPIO9 input mode. */ 154 RTWN_CHK(rtwn_setbits_1(sc, 0x062, 0x02, 0)); 155 156 /* Enable HSISR GPIO interrupt. */ 157 RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR, 0, 0x01)); 158 159 /* Enable HSISR GPIO9 interrupt. */ 160 RTWN_CHK(rtwn_setbits_1(sc, R92C_HSIMR + 2, 0, 0x02)); 161 162 /* XTAL trim. */ 163 RTWN_CHK(rtwn_setbits_1(sc, R92C_APE_PLL_CTRL_EXT + 2, 0xFF, 0x82)); 164 165 RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_MISC, 0, 0x40)); 166 167 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 168 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000)); 169 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0, 170 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | 171 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | 172 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | 173 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | 174 R92C_CR_CALTMR_EN)); 175 176 if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN) 177 RTWN_CHK(rtwn_setbits_1(sc, R92C_LDO_SWR_CTRL, 0, 0x40)); 178 179 return (0); 180 #undef RTWN_CHK 181 } 182 183 void 184 r21a_power_off(struct rtwn_softc *sc) 185 { 186 struct r12a_softc *rs = sc->sc_priv; 187 int error, ntries; 188 189 /* Stop Rx. */ 190 error = rtwn_write_1(sc, R92C_CR, 0); 191 if (error == ENXIO) /* hardware gone */ 192 return; 193 194 /* Move card to Low Power state. */ 195 /* Block all Tx queues. */ 196 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 197 198 for (ntries = 0; ntries < 10; ntries++) { 199 /* Should be zero if no packet is transmitting. */ 200 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 201 break; 202 203 rtwn_delay(sc, 5000); 204 } 205 if (ntries == 10) { 206 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 207 __func__); 208 return; 209 } 210 211 /* CCK and OFDM are disabled, and clock are gated. */ 212 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0); 213 214 rtwn_delay(sc, 1); 215 216 /* Reset whole BB. */ 217 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 218 219 /* Reset MAC TRX. */ 220 rtwn_write_1(sc, R92C_CR, 221 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN); 222 223 /* check if removed later. (?) */ 224 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1); 225 226 /* Respond TxOK to scheduler */ 227 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK); 228 229 /* If firmware in ram code, do reset. */ 230 #ifndef RTWN_WITHOUT_UCODE 231 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 232 r21a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN); 233 #endif 234 235 /* Reset MCU. */ 236 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 237 0, 1); 238 rtwn_write_1(sc, R92C_MCUFWDL, 0); 239 240 /* Move card to Disabled state. */ 241 /* Turn off RF. */ 242 rtwn_write_1(sc, R92C_RF_CTRL, 0); 243 244 rtwn_setbits_1(sc, R92C_LEDCFG3, 0x01, 0); 245 246 /* Enable rising edge triggering interrupt. */ 247 rtwn_setbits_1(sc, R92C_GPIO_INTM + 1, 0x02, 0); 248 249 /* Release WLON reset. */ 250 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 251 R92C_APS_FSMCO_RDY_MACON, 2); 252 253 /* Turn off MAC by HW state machine */ 254 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF, 255 1); 256 for (ntries = 0; ntries < 10; ntries++) { 257 /* Wait until it will be disabled. */ 258 if ((rtwn_read_2(sc, R92C_APS_FSMCO) & 259 R92C_APS_FSMCO_APFM_OFF) == 0) 260 break; 261 262 rtwn_delay(sc, 5000); 263 } 264 if (ntries == 10) { 265 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 266 __func__); 267 return; 268 } 269 270 /* Analog Ips to digital isolation. */ 271 rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL, 0, R92C_SYS_ISO_CTRL_IP2MAC); 272 273 /* Disable LDOA12 MACRO block. */ 274 rtwn_setbits_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_EN, 0); 275 276 /* Enable WL suspend. */ 277 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE, 278 R92C_APS_FSMCO_AFSM_HSUS, 1); 279 280 /* Enable GPIO9 as EXT WAKEUP. */ 281 rtwn_setbits_1(sc, R92C_GPIO_INTM + 2, 0, 0x01); 282 283 rs->rs_flags &= ~(R12A_IQK_RUNNING | R12A_RADAR_ENABLED); 284 } 285 286 int 287 r21a_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 288 { 289 struct r12a_softc *rs = sc->sc_priv; 290 uint8_t mask; 291 int i; 292 293 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 294 "%s: condition byte 0: %02X; ext 5ghz pa/lna %d/%d\n", 295 __func__, cond[0], rs->ext_pa_5g, rs->ext_lna_5g); 296 297 if (cond[0] == 0) 298 return (1); 299 300 mask = 0; 301 if (rs->ext_pa_5g) 302 mask |= R21A_COND_EXT_PA_5G; 303 if (rs->ext_lna_5g) 304 mask |= R21A_COND_EXT_LNA_5G; 305 if (rs->bt_coex) 306 mask |= R21A_COND_BT; 307 if (!rs->ext_pa_2g && !rs->ext_lna_2g && 308 !rs->ext_pa_5g && !rs->ext_lna_5g && !rs->bt_coex) 309 mask = R21A_COND_BOARD_DEF; 310 311 if (mask == 0) 312 return (0); 313 314 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 315 if (cond[i] == mask) 316 return (1); 317 318 return (0); 319 } 320 321 void 322 r21a_crystalcap_write(struct rtwn_softc *sc) 323 { 324 struct r12a_softc *rs = sc->sc_priv; 325 uint32_t reg; 326 uint8_t val; 327 328 val = rs->crystalcap & 0x3f; 329 reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL); 330 reg = RW(reg, R21A_MAC_PHY_CRYSTALCAP, val | (val << 6)); 331 rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg); 332 } 333 334 int 335 r21a_init_bcnq1_boundary(struct rtwn_softc *sc) 336 { 337 #define RTWN_CHK(res) do { \ 338 if (res != 0) \ 339 return (EIO); \ 340 } while(0) 341 RTWN_CHK(rtwn_write_1(sc, R88E_TXPKTBUF_BCNQ1_BDNY, 342 R21A_BCNQ0_BOUNDARY)); 343 RTWN_CHK(rtwn_write_1(sc, R21A_DWBCN1_CTRL + 1, 344 R21A_BCNQ0_BOUNDARY)); 345 RTWN_CHK(rtwn_setbits_1_shift(sc, R21A_DWBCN1_CTRL, 0, 346 R21A_DWBCN1_CTRL_SEL_EN, 2)); 347 348 return (0); 349 #undef RTWN_CHK 350 } 351 352 void 353 r21a_init_ampdu_fwhw(struct rtwn_softc *sc) 354 { 355 rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 356 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 357 rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x03087777); 358 } 359