1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 56 #include <dev/rtwn/rtl8192c/r92c.h> 57 58 #include <dev/rtwn/rtl8812a/r12a.h> 59 #include <dev/rtwn/rtl8812a/r12a_priv.h> 60 #include <dev/rtwn/rtl8812a/r12a_reg.h> 61 #include <dev/rtwn/rtl8812a/r12a_var.h> 62 63 int 64 r12a_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 65 { 66 struct r12a_softc *rs = sc->sc_priv; 67 uint8_t mask[4]; 68 int i, j, nmasks; 69 70 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 71 "%s: condition byte 0: %02X; ext PA/LNA: %d/%d (2 GHz), " 72 "%d/%d (5 GHz)\n", __func__, cond[0], rs->ext_pa_2g, 73 rs->ext_lna_2g, rs->ext_pa_5g, rs->ext_lna_5g); 74 75 if (cond[0] == 0) 76 return (1); 77 78 if (!rs->ext_pa_2g && !rs->ext_lna_2g && 79 !rs->ext_pa_5g && !rs->ext_lna_5g) 80 return (0); 81 82 nmasks = 0; 83 if (rs->ext_pa_2g) { 84 mask[nmasks] = R12A_COND_GPA; 85 mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_2g); 86 nmasks++; 87 } 88 if (rs->ext_pa_5g) { 89 mask[nmasks] = R12A_COND_APA; 90 mask[nmasks] |= R12A_COND_TYPE(rs->type_pa_5g); 91 nmasks++; 92 } 93 if (rs->ext_lna_2g) { 94 mask[nmasks] = R12A_COND_GLNA; 95 mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_2g); 96 nmasks++; 97 } 98 if (rs->ext_lna_5g) { 99 mask[nmasks] = R12A_COND_ALNA; 100 mask[nmasks] |= R12A_COND_TYPE(rs->type_lna_5g); 101 nmasks++; 102 } 103 104 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 105 for (j = 0; j < nmasks; j++) 106 if ((cond[i] & mask[j]) == mask[j]) 107 return (1); 108 109 return (0); 110 } 111 112 int 113 r12a_set_page_size(struct rtwn_softc *sc) 114 { 115 return (rtwn_setbits_1(sc, R92C_PBP, R92C_PBP_PSTX_M, 116 R92C_PBP_512 << R92C_PBP_PSTX_S) == 0); 117 } 118 119 void 120 r12a_init_edca(struct rtwn_softc *sc) 121 { 122 r92c_init_edca(sc); 123 124 /* 80 MHz clock */ 125 rtwn_write_1(sc, R92C_USTIME_TSF, 0x50); 126 rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50); 127 } 128 129 void 130 r12a_init_bb(struct rtwn_softc *sc) 131 { 132 int i, j; 133 134 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_USBA); 135 136 /* Enable BB and RF. */ 137 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, 138 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST); 139 140 /* PathA RF Power On. */ 141 rtwn_write_1(sc, R92C_RF_CTRL, 142 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 143 144 /* PathB RF Power On. */ 145 rtwn_write_1(sc, R12A_RF_B_CTRL, 146 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 147 148 /* Write BB initialization values. */ 149 for (i = 0; i < sc->bb_size; i++) { 150 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 151 152 while (!rtwn_check_condition(sc, bb_prog->cond)) { 153 KASSERT(bb_prog->next != NULL, 154 ("%s: wrong condition value (i %d)\n", 155 __func__, i)); 156 bb_prog = bb_prog->next; 157 } 158 159 for (j = 0; j < bb_prog->count; j++) { 160 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 161 "BB: reg 0x%03x, val 0x%08x\n", 162 bb_prog->reg[j], bb_prog->val[j]); 163 164 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 165 rtwn_delay(sc, 1); 166 } 167 } 168 169 /* XXX meshpoint mode? */ 170 171 /* Write AGC values. */ 172 for (i = 0; i < sc->agc_size; i++) { 173 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 174 175 while (!rtwn_check_condition(sc, agc_prog->cond)) { 176 KASSERT(agc_prog->next != NULL, 177 ("%s: wrong condition value (2) (i %d)\n", 178 __func__, i)); 179 agc_prog = agc_prog->next; 180 } 181 182 for (j = 0; j < agc_prog->count; j++) { 183 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 184 "AGC: val 0x%08x\n", agc_prog->val[j]); 185 186 rtwn_bb_write(sc, 0x81c, agc_prog->val[j]); 187 rtwn_delay(sc, 1); 188 } 189 } 190 191 for (i = 0; i < sc->nrxchains; i++) { 192 rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x22); 193 rtwn_delay(sc, 1); 194 rtwn_bb_write(sc, R12A_INITIAL_GAIN(i), 0x20); 195 rtwn_delay(sc, 1); 196 } 197 198 rtwn_r12a_crystalcap_write(sc); 199 200 if (rtwn_bb_read(sc, R12A_CCK_RPT_FORMAT) & R12A_CCK_RPT_FORMAT_HIPWR) 201 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 202 } 203 204 void 205 r12a_init_rf(struct rtwn_softc *sc) 206 { 207 int chain, i; 208 209 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 210 /* Write RF initialization values for this chain. */ 211 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 212 } 213 } 214 215 void 216 r12a_crystalcap_write(struct rtwn_softc *sc) 217 { 218 struct r12a_softc *rs = sc->sc_priv; 219 uint32_t reg; 220 uint8_t val; 221 222 val = rs->crystalcap & 0x3f; 223 reg = rtwn_bb_read(sc, R92C_MAC_PHY_CTRL); 224 reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6)); 225 rtwn_bb_write(sc, R92C_MAC_PHY_CTRL, reg); 226 } 227 228 static void 229 r12a_rf_init_workaround(struct rtwn_softc *sc) 230 { 231 232 rtwn_write_1(sc, R92C_RF_CTRL, 233 R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB); 234 rtwn_write_1(sc, R92C_RF_CTRL, 235 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | 236 R92C_RF_CTRL_SDMRSTB); 237 rtwn_write_1(sc, R12A_RF_B_CTRL, 238 R92C_RF_CTRL_EN | R92C_RF_CTRL_SDMRSTB); 239 rtwn_write_1(sc, R12A_RF_B_CTRL, 240 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | 241 R92C_RF_CTRL_SDMRSTB); 242 } 243 244 int 245 r12a_power_on(struct rtwn_softc *sc) 246 { 247 #define RTWN_CHK(res) do { \ 248 if (res != 0) \ 249 return (EIO); \ 250 } while(0) 251 int ntries; 252 253 r12a_rf_init_workaround(sc); 254 255 /* Force PWM mode. */ 256 RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01)); 257 258 /* Turn off ZCD. */ 259 RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0)); 260 261 /* Enable LDO normal mode. */ 262 RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 263 0)); 264 265 /* GPIO 0...7 input mode. */ 266 RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0)); 267 268 /* GPIO 11...8 input mode. */ 269 RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0)); 270 271 /* Enable WL suspend. */ 272 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 273 R92C_APS_FSMCO_AFSM_HSUS, 0, 1)); 274 275 /* Enable 8051. */ 276 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 277 0, R92C_SYS_FUNC_EN_CPUEN, 1)); 278 279 /* Disable SW LPS. */ 280 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 281 R92C_APS_FSMCO_APFM_RSM, 0, 1)); 282 283 /* Wait for power ready bit. */ 284 for (ntries = 0; ntries < 5000; ntries++) { 285 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 286 break; 287 rtwn_delay(sc, 10); 288 } 289 if (ntries == 5000) { 290 device_printf(sc->sc_dev, 291 "timeout waiting for chip power up\n"); 292 return (ETIMEDOUT); 293 } 294 295 /* Disable WL suspend. */ 296 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 297 R92C_APS_FSMCO_AFSM_HSUS, 0, 1)); 298 299 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 300 R92C_APS_FSMCO_APFM_ONMAC, 1)); 301 for (ntries = 0; ntries < 5000; ntries++) { 302 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 303 R92C_APS_FSMCO_APFM_ONMAC)) 304 break; 305 rtwn_delay(sc, 10); 306 } 307 if (ntries == 5000) 308 return (ETIMEDOUT); 309 310 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 311 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000)); 312 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0, 313 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | 314 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | 315 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | 316 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | 317 R92C_CR_CALTMR_EN)); 318 319 return (0); 320 } 321 322 void 323 r12a_power_off(struct rtwn_softc *sc) 324 { 325 struct r12a_softc *rs = sc->sc_priv; 326 int error, ntries; 327 328 /* Stop Rx. */ 329 error = rtwn_write_1(sc, R92C_CR, 0); 330 if (error == ENXIO) /* hardware gone */ 331 return; 332 333 /* Move card to Low Power state. */ 334 /* Block all Tx queues. */ 335 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 336 337 for (ntries = 0; ntries < 10; ntries++) { 338 /* Should be zero if no packet is transmitting. */ 339 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 340 break; 341 342 rtwn_delay(sc, 5000); 343 } 344 if (ntries == 10) { 345 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 346 __func__); 347 return; 348 } 349 350 /* Turn off 3-wire. */ 351 rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04); 352 rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04); 353 354 /* CCK and OFDM are disabled, and clock are gated. */ 355 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0); 356 357 rtwn_delay(sc, 1); 358 359 /* Reset whole BB. */ 360 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 361 362 /* Reset MAC TRX. */ 363 rtwn_write_1(sc, R92C_CR, 364 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN); 365 366 /* check if removed later. (?) */ 367 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1); 368 369 /* Respond TxOK to scheduler */ 370 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK); 371 372 /* If firmware in ram code, do reset. */ 373 #ifndef RTWN_WITHOUT_UCODE 374 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 375 r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN); 376 #endif 377 378 /* Reset MCU. */ 379 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 380 0, 1); 381 rtwn_write_1(sc, R92C_MCUFWDL, 0); 382 383 /* Move card to Disabled state. */ 384 /* Turn off 3-wire. */ 385 rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04); 386 rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04); 387 388 /* Reset BB, close RF. */ 389 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 390 391 rtwn_delay(sc, 1); 392 393 /* SPS PWM mode. */ 394 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 395 R92C_APS_FSMCO_SOP_RCK | R92C_APS_FSMCO_SOP_ABG, 3); 396 397 /* ANA clock = 500k. */ 398 rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0); 399 400 /* Turn off MAC by HW state machine */ 401 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF, 402 1); 403 for (ntries = 0; ntries < 10; ntries++) { 404 /* Wait until it will be disabled. */ 405 if ((rtwn_read_2(sc, R92C_APS_FSMCO) & 406 R92C_APS_FSMCO_APFM_OFF) == 0) 407 break; 408 409 rtwn_delay(sc, 5000); 410 } 411 if (ntries == 10) { 412 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 413 __func__); 414 return; 415 } 416 417 /* Reset 8051. */ 418 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN, 419 0, 1); 420 421 /* Fill the default value of host_CPU handshake field. */ 422 rtwn_write_1(sc, R92C_MCUFWDL, 423 R92C_MCUFWDL_EN | R92C_MCUFWDL_CHKSUM_RPT); 424 425 rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0); 426 427 /* GPIO 11 input mode, 10...8 output mode. */ 428 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07); 429 430 /* GPIO 7...0, output = input */ 431 rtwn_write_1(sc, R92C_GPIO_OUT, 0); 432 433 /* GPIO 7...0 output mode. */ 434 rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 435 436 rtwn_write_1(sc, R92C_GPIO_MOD, 0); 437 438 /* Turn on ZCD. */ 439 rtwn_setbits_2(sc, 0x014, 0, 0x0180); 440 441 /* Force PFM mode. */ 442 rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0); 443 444 /* LDO sleep mode. */ 445 rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP); 446 447 /* ANA clock = 500k. */ 448 rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0); 449 450 /* SOP option to disable BG/MB. */ 451 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 452 R92C_APS_FSMCO_SOP_RCK, 3); 453 454 /* Disable RFC_0. */ 455 rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0); 456 457 /* Disable RFC_1. */ 458 rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0); 459 460 /* Enable WL suspend. */ 461 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS, 462 1); 463 464 rs->rs_flags &= ~R12A_IQK_RUNNING; 465 } 466 467 void 468 r12a_init_intr(struct rtwn_softc *sc) 469 { 470 rtwn_write_4(sc, R88E_HIMR, 0); 471 rtwn_write_4(sc, R88E_HIMRE, 0); 472 } 473 474 void 475 r12a_init_antsel(struct rtwn_softc *sc) 476 { 477 uint32_t reg; 478 479 rtwn_write_1(sc, R92C_LEDCFG2, 0x82); 480 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); 481 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 482 sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); 483 } 484