1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 32 #include <sys/param.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 46 #include <net/if.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/rtwn/if_rtwnreg.h> 54 #include <dev/rtwn/if_rtwnvar.h> 55 56 #include <dev/rtwn/if_rtwn_debug.h> 57 #include <dev/rtwn/if_rtwn_ridx.h> 58 #include <dev/rtwn/if_rtwn_rx.h> 59 60 #include <dev/rtwn/rtl8812a/r12a.h> 61 #include <dev/rtwn/rtl8812a/r12a_reg.h> 62 #include <dev/rtwn/rtl8812a/r12a_var.h> 63 64 65 static void 66 r12a_write_txpower(struct rtwn_softc *sc, int chain, 67 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 68 { 69 70 if (IEEE80211_IS_CHAN_2GHZ(c)) { 71 /* Write per-CCK rate Tx power. */ 72 rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain), 73 SM(R12A_TXAGC_CCK1, power[RTWN_RIDX_CCK1]) | 74 SM(R12A_TXAGC_CCK2, power[RTWN_RIDX_CCK2]) | 75 SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) | 76 SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11])); 77 } 78 79 /* Write per-OFDM rate Tx power. */ 80 rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain), 81 SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) | 82 SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) | 83 SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) | 84 SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18])); 85 rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain), 86 SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) | 87 SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) | 88 SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) | 89 SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54])); 90 /* Write per-MCS Tx power. */ 91 rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain), 92 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_MCS(0)]) | 93 SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_MCS(1)]) | 94 SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_MCS(2)]) | 95 SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_MCS(3)])); 96 rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain), 97 SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_MCS(4)]) | 98 SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_MCS(5)]) | 99 SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_MCS(6)]) | 100 SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_MCS(7)])); 101 if (sc->ntxchains >= 2) { 102 rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain), 103 SM(R12A_TXAGC_MCS8, power[RTWN_RIDX_MCS(8)]) | 104 SM(R12A_TXAGC_MCS9, power[RTWN_RIDX_MCS(9)]) | 105 SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_MCS(10)]) | 106 SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_MCS(11)])); 107 rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain), 108 SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_MCS(12)]) | 109 SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_MCS(13)]) | 110 SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_MCS(14)]) | 111 SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_MCS(15)])); 112 } 113 114 /* TODO: VHT rates */ 115 } 116 117 static int 118 r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 119 { 120 uint8_t chan; 121 int group; 122 123 chan = rtwn_chan2centieee(c); 124 if (IEEE80211_IS_CHAN_2GHZ(c)) { 125 if (chan <= 2) group = 0; 126 else if (chan <= 5) group = 1; 127 else if (chan <= 8) group = 2; 128 else if (chan <= 11) group = 3; 129 else if (chan <= 14) group = 4; 130 else { 131 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 132 return (-1); 133 } 134 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 135 if (chan < 36) 136 return (-1); 137 138 if (chan <= 42) group = 0; 139 else if (chan <= 48) group = 1; 140 else if (chan <= 58) group = 2; 141 else if (chan <= 64) group = 3; 142 else if (chan <= 106) group = 4; 143 else if (chan <= 114) group = 5; 144 else if (chan <= 122) group = 6; 145 else if (chan <= 130) group = 7; 146 else if (chan <= 138) group = 8; 147 else if (chan <= 144) group = 9; 148 else if (chan <= 155) group = 10; 149 else if (chan <= 161) group = 11; 150 else if (chan <= 171) group = 12; 151 else if (chan <= 177) group = 13; 152 else { 153 KASSERT(0, ("wrong 5GHz channel %d!\n", chan)); 154 return (-1); 155 } 156 } else { 157 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 158 return (-1); 159 } 160 161 return (group); 162 } 163 164 static void 165 r12a_get_txpower(struct rtwn_softc *sc, int chain, 166 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 167 { 168 struct r12a_softc *rs = sc->sc_priv; 169 int i, ridx, group, max_mcs; 170 171 /* Determine channel group. */ 172 group = r12a_get_power_group(sc, c); 173 if (group == -1) { /* shouldn't happen */ 174 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 175 return; 176 } 177 178 /* TODO: VHT rates. */ 179 max_mcs = RTWN_RIDX_MCS(sc->ntxchains * 8 - 1); 180 181 /* XXX regulatory */ 182 /* XXX net80211 regulatory */ 183 184 if (IEEE80211_IS_CHAN_2GHZ(c)) { 185 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 186 power[ridx] = rs->cck_tx_pwr[chain][group]; 187 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 188 power[ridx] = rs->ht40_tx_pwr_2g[chain][group]; 189 190 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 191 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0]; 192 193 for (i = 0; i < sc->ntxchains; i++) { 194 uint8_t min_mcs; 195 uint8_t pwr_diff; 196 197 #ifdef notyet 198 if (IEEE80211_IS_CHAN_HT80(c)) { 199 /* Vendor driver uses HT40 values here. */ 200 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 201 } else 202 #endif 203 if (IEEE80211_IS_CHAN_HT40(c)) 204 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 205 else 206 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i]; 207 208 min_mcs = RTWN_RIDX_MCS(i * 8); 209 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 210 power[ridx] += pwr_diff; 211 } 212 } else { /* 5GHz */ 213 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 214 power[ridx] = rs->ht40_tx_pwr_5g[chain][group]; 215 216 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 217 power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0]; 218 219 for (i = 0; i < sc->ntxchains; i++) { 220 uint8_t min_mcs; 221 uint8_t pwr_diff; 222 223 #ifdef notyet 224 if (IEEE80211_IS_CHAN_HT80(c)) { 225 /* TODO: calculate base value. */ 226 pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i]; 227 } else 228 #endif 229 if (IEEE80211_IS_CHAN_HT40(c)) 230 pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i]; 231 else 232 pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i]; 233 234 min_mcs = RTWN_RIDX_MCS(i * 8); 235 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 236 power[ridx] += pwr_diff; 237 } 238 } 239 240 /* Apply max limit. */ 241 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 242 if (power[ridx] > R92C_MAX_TX_PWR) 243 power[ridx] = R92C_MAX_TX_PWR; 244 } 245 246 #ifdef RTWN_DEBUG 247 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 248 /* Dump per-rate Tx power values. */ 249 printf("Tx power for chain %d:\n", chain); 250 for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++) 251 printf("Rate %d = %u\n", ridx, power[ridx]); 252 } 253 #endif 254 } 255 256 static void 257 r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 258 { 259 uint8_t power[RTWN_RIDX_COUNT]; 260 int i; 261 262 for (i = 0; i < sc->ntxchains; i++) { 263 memset(power, 0, sizeof(power)); 264 /* Compute per-rate Tx power values. */ 265 r12a_get_txpower(sc, i, c, power); 266 /* Write per-rate Tx power values to hardware. */ 267 r12a_write_txpower(sc, i, c, power); 268 } 269 } 270 271 void 272 r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c) 273 { 274 struct r12a_softc *rs = sc->sc_priv; 275 uint16_t chan = rtwn_chan2centieee(c); 276 277 if (rs->chip & R12A_CHIP_C_CUT) { 278 if (IEEE80211_IS_CHAN_HT40(c) && chan == 11) { 279 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00); 280 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); 281 } else { 282 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800); 283 284 if (!IEEE80211_IS_CHAN_HT40(c) && /* 20 MHz */ 285 (chan == 13 || chan == 14)) { 286 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 287 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 288 0, 0x40000000); 289 } else { /* !80 Mhz */ 290 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 291 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 292 0x40000000, 0); 293 } 294 } 295 } else { 296 /* Set ADC clock to 160M to resolve 2480 MHz spur. */ 297 if (!IEEE80211_IS_CHAN_HT40(c) && /* 20 MHz */ 298 (chan == 13 || chan == 14)) 299 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 300 else if (IEEE80211_IS_CHAN_2GHZ(c)) 301 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 302 } 303 } 304 305 static void 306 r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c) 307 { 308 struct ieee80211com *ic = &sc->sc_ic; 309 struct r12a_softc *rs = sc->sc_priv; 310 uint32_t basicrates; 311 uint8_t swing; 312 int i; 313 314 /* Check if band was changed. */ 315 if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) != 316 RTWN_STARTED && IEEE80211_IS_CHAN_5GHZ(c) ^ 317 !(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ)) 318 return; 319 320 rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates, 321 NULL, 1); 322 if (IEEE80211_IS_CHAN_2GHZ(c)) { 323 rtwn_r12a_set_band_2ghz(sc, basicrates); 324 swing = rs->tx_bbswing_2g; 325 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 326 rtwn_r12a_set_band_5ghz(sc, basicrates); 327 swing = rs->tx_bbswing_5g; 328 } else { 329 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags)); 330 return; 331 } 332 333 /* XXX PATH_B is set by vendor driver. */ 334 for (i = 0; i < 2; i++) { 335 uint16_t val = 0; 336 337 switch ((swing >> i * 2) & 0x3) { 338 case 0: 339 val = 0x200; /* 0 dB */ 340 break; 341 case 1: 342 val = 0x16a; /* -3 dB */ 343 break; 344 case 2: 345 val = 0x101; /* -6 dB */ 346 break; 347 case 3: 348 val = 0xb6; /* -9 dB */ 349 break; 350 } 351 352 rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M, 353 val << R12A_TX_SCALE_SWING_S); 354 } 355 } 356 357 void 358 r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 359 { 360 uint32_t val; 361 uint16_t chan; 362 int i; 363 364 r12a_set_band(sc, c); 365 366 chan = rtwn_chan2centieee(c); 367 if (36 <= chan && chan <= 48) 368 val = 0x09280000; 369 else if (50 <= chan && chan <= 64) 370 val = 0x08a60000; 371 else if (100 <= chan && chan <= 116) 372 val = 0x08a40000; 373 else if (118 <= chan) 374 val = 0x08240000; 375 else 376 val = 0x12d40000; 377 378 rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val); 379 380 for (i = 0; i < sc->nrxchains; i++) { 381 if (36 <= chan && chan <= 64) 382 val = 0x10100; 383 else if (100 <= chan && chan <= 140) 384 val = 0x30100; 385 else if (140 < chan) 386 val = 0x50100; 387 else 388 val = 0x00000; 389 390 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val); 391 392 /* RTL8812AU-specific */ 393 rtwn_r12a_fix_spur(sc, c); 394 395 KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan)); 396 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan); 397 } 398 399 #ifdef notyet 400 if (IEEE80211_IS_CHAN_HT80(c)) { /* 80 MHz */ 401 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x80, 0x100); 402 403 /* TODO */ 404 405 val = 0x0; 406 } else 407 #endif 408 if (IEEE80211_IS_CHAN_HT40(c)) { /* 40 MHz */ 409 uint8_t ext_chan; 410 411 if (IEEE80211_IS_CHAN_HT40U(c)) 412 ext_chan = R12A_DATA_SEC_PRIM_DOWN_20; 413 else 414 ext_chan = R12A_DATA_SEC_PRIM_UP_20; 415 416 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80); 417 rtwn_write_1(sc, R12A_DATA_SEC, ext_chan); 418 419 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201); 420 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 421 422 /* discard high 4 bits */ 423 val = rtwn_bb_read(sc, R12A_RFMOD); 424 val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan); 425 rtwn_bb_write(sc, R12A_RFMOD, val); 426 427 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC); 428 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan); 429 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val); 430 431 if (rtwn_read_1(sc, 0x837) & 0x04) 432 val = 0x01800000; 433 else if (sc->nrxchains == 2 && sc->ntxchains == 2) 434 val = 0x01c00000; 435 else 436 val = 0x02000000; 437 438 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 439 440 if (IEEE80211_IS_CHAN_HT40U(c)) 441 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0); 442 else 443 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10); 444 445 val = 0x400; 446 } else { /* 20 MHz */ 447 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0); 448 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT); 449 450 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200); 451 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 452 453 if (sc->nrxchains == 2 && sc->ntxchains == 2) 454 val = 0x01c00000; 455 else 456 val = 0x02000000; 457 458 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 459 460 val = 0xc00; 461 } 462 463 /* RTL8812AU-specific */ 464 rtwn_r12a_fix_spur(sc, c); 465 466 for (i = 0; i < sc->nrxchains; i++) 467 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val); 468 469 /* Set Tx power for this new channel. */ 470 r12a_set_txpower(sc, c); 471 } 472 473 void 474 r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates) 475 { 476 struct r12a_softc *rs = sc->sc_priv; 477 478 /* Enable CCK / OFDM. */ 479 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, 480 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); 481 482 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01); 483 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000); 484 485 /* Select AGC table. */ 486 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0); 487 488 switch (rs->rfe_type) { 489 case 0: 490 case 1: 491 case 2: 492 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 493 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 494 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 495 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 496 break; 497 case 3: 498 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770); 499 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770); 500 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 501 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 502 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 503 break; 504 case 4: 505 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 506 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 507 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000); 508 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000); 509 break; 510 case 5: 511 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77); 512 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 513 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0); 514 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 515 break; 516 default: 517 break; 518 } 519 520 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10); 521 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000); 522 523 /* Write basic rates. */ 524 rtwn_set_basicrates(sc, basicrates); 525 526 rtwn_write_1(sc, R12A_CCK_CHECK, 0); 527 } 528 529 void 530 r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates) 531 { 532 struct r12a_softc *rs = sc->sc_priv; 533 int ntries; 534 535 rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ); 536 537 for (ntries = 0; ntries < 100; ntries++) { 538 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30) 539 break; 540 541 rtwn_delay(sc, 25); 542 } 543 if (ntries == 100) { 544 device_printf(sc->sc_dev, 545 "%s: TXPKT_EMPTY check failed (%04X)\n", 546 __func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY)); 547 } 548 549 /* Enable OFDM. */ 550 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK, 551 R12A_OFDMCCK_EN_OFDM); 552 553 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02); 554 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000); 555 556 /* Select AGC table. */ 557 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01); 558 559 switch (rs->rfe_type) { 560 case 0: 561 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 562 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 563 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 564 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 565 break; 566 case 1: 567 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 568 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 569 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 570 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 571 break; 572 case 2: 573 case 4: 574 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777); 575 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 576 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 577 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 578 break; 579 case 3: 580 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717); 581 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717); 582 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 583 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 584 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 585 break; 586 case 5: 587 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33); 588 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 589 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01); 590 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 591 break; 592 default: 593 break; 594 } 595 596 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0); 597 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000); 598 599 /* Write basic rates. */ 600 rtwn_set_basicrates(sc, basicrates); 601 } 602