1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 #include <dev/rtwn/if_rtwn_ridx.h> 56 #include <dev/rtwn/if_rtwn_rx.h> 57 58 #include <dev/rtwn/rtl8812a/r12a.h> 59 #include <dev/rtwn/rtl8812a/r12a_reg.h> 60 #include <dev/rtwn/rtl8812a/r12a_var.h> 61 62 static void 63 r12a_write_txpower_ht(struct rtwn_softc *sc, int chain, 64 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 65 { 66 67 /* Write per-MCS Tx power. */ 68 rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain), 69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) | 70 SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_HT_MCS(1)]) | 71 SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_HT_MCS(2)]) | 72 SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_HT_MCS(3)])); 73 rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain), 74 SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_HT_MCS(4)]) | 75 SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_HT_MCS(5)]) | 76 SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_HT_MCS(6)]) | 77 SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_HT_MCS(7)])); 78 if (sc->ntxchains >= 2) { 79 rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain), 80 SM(R12A_TXAGC_MCS8, power[RTWN_RIDX_HT_MCS(8)]) | 81 SM(R12A_TXAGC_MCS9, power[RTWN_RIDX_HT_MCS(9)]) | 82 SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) | 83 SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)])); 84 rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain), 85 SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) | 86 SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) | 87 SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) | 88 SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)])); 89 } 90 91 /* TODO: HT MCS 16 -> 31 */ 92 } 93 94 static void 95 r12a_write_txpower_vht(struct rtwn_softc *sc, int chain, 96 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 97 { 98 99 /* 1SS, MCS 0..3 */ 100 rtwn_bb_write(sc, R12A_TXAGC_NSS1IX3_1IX0(chain), 101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) | 102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) | 103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) | 104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)])); 105 106 /* 1SS, MCS 4..7 */ 107 rtwn_bb_write(sc, R12A_TXAGC_NSS1IX7_1IX4(chain), 108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) | 109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) | 110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) | 111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)])); 112 113 /* 1SS, MCS 8,9 ; 2SS MCS0, 1 */ 114 if (sc->ntxchains == 1) { 115 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX1_1IX8(chain), 116 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) | 117 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) | 118 SM(R12A_TXAGC_NSS2_MCS0, 0) | 119 SM(R12A_TXAGC_NSS2_MCS1, 0)); 120 } else { 121 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX1_1IX8(chain), 122 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) | 123 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) | 124 SM(R12A_TXAGC_NSS2_MCS0, power[RTWN_RIDX_VHT_MCS(1, 0)]) | 125 SM(R12A_TXAGC_NSS2_MCS1, power[RTWN_RIDX_VHT_MCS(1, 1)])); 126 } 127 128 /* 2SS MCS 2..5 */ 129 if (sc->ntxchains > 1) { 130 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX5_2IX2(chain), 131 SM(R12A_TXAGC_NSS2_MCS2, power[RTWN_RIDX_VHT_MCS(1, 2)]) | 132 SM(R12A_TXAGC_NSS2_MCS3, power[RTWN_RIDX_VHT_MCS(1, 3)]) | 133 SM(R12A_TXAGC_NSS2_MCS4, power[RTWN_RIDX_VHT_MCS(1, 4)]) | 134 SM(R12A_TXAGC_NSS2_MCS5, power[RTWN_RIDX_VHT_MCS(1, 5)])); 135 } 136 137 /* 2SS MCS 6..9 */ 138 if (sc->ntxchains > 1) { 139 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX9_2IX6(chain), 140 SM(R12A_TXAGC_NSS2_MCS2, power[RTWN_RIDX_VHT_MCS(1, 6)]) | 141 SM(R12A_TXAGC_NSS2_MCS3, power[RTWN_RIDX_VHT_MCS(1, 7)]) | 142 SM(R12A_TXAGC_NSS2_MCS4, power[RTWN_RIDX_VHT_MCS(1, 8)]) | 143 SM(R12A_TXAGC_NSS2_MCS5, power[RTWN_RIDX_VHT_MCS(1, 9)])); 144 } 145 146 /* TODO: 3SS, 4SS VHT rates */ 147 } 148 149 150 static void 151 r12a_write_txpower_cck(struct rtwn_softc *sc, int chain, 152 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 153 { 154 155 if (IEEE80211_IS_CHAN_2GHZ(c)) { 156 /* Write per-CCK rate Tx power. */ 157 rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain), 158 SM(R12A_TXAGC_CCK1, power[RTWN_RIDX_CCK1]) | 159 SM(R12A_TXAGC_CCK2, power[RTWN_RIDX_CCK2]) | 160 SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) | 161 SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11])); 162 } 163 } 164 165 static void 166 r12a_write_txpower_ofdm(struct rtwn_softc *sc, int chain, 167 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 168 { 169 170 /* Write per-OFDM rate Tx power. */ 171 rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain), 172 SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) | 173 SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) | 174 SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) | 175 SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18])); 176 rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain), 177 SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) | 178 SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) | 179 SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) | 180 SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54])); 181 } 182 183 static void 184 r12a_tx_power_training(struct rtwn_softc *sc, int chain, 185 const struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 186 { 187 uint32_t write_data; 188 int32_t power_level; 189 int i; 190 191 write_data = 0; 192 193 power_level = (int32_t) power[RTWN_RIDX_HT_MCS(7)]; 194 for (i = 0; i < 3; i++) { 195 if (i == 0) 196 power_level -= 10; 197 else if (i == 1) 198 power_level -= 8; 199 else 200 power_level -= 6; 201 202 /* Handle underflow and the minimum value (2) */ 203 if (power_level < 2) 204 power_level = 2; 205 206 write_data |= ((power_level & 0xff) << (i * 8)); 207 } 208 209 rtwn_bb_setbits(sc, R12A_TX_PWR_TRAINING(chain), 210 0x00ffffff, write_data); 211 } 212 213 static void 214 r12a_write_txpower(struct rtwn_softc *sc, int chain, 215 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 216 { 217 218 r12a_write_txpower_cck(sc, chain, c, power); 219 r12a_write_txpower_ofdm(sc, chain, c, power); 220 r12a_write_txpower_ht(sc, chain, c, power); 221 r12a_write_txpower_vht(sc, chain, c, power); 222 223 r12a_tx_power_training(sc, chain, c, power); 224 } 225 226 static int 227 r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 228 { 229 uint8_t chan; 230 int group; 231 232 chan = rtwn_chan2centieee(c); 233 if (IEEE80211_IS_CHAN_2GHZ(c)) { 234 if (chan <= 2) group = 0; 235 else if (chan <= 5) group = 1; 236 else if (chan <= 8) group = 2; 237 else if (chan <= 11) group = 3; 238 else if (chan <= 14) group = 4; 239 else { 240 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 241 return (-1); 242 } 243 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 244 if (chan < 36) 245 return (-1); 246 247 if (chan <= 42) group = 0; 248 else if (chan <= 48) group = 1; 249 else if (chan <= 58) group = 2; 250 else if (chan <= 64) group = 3; 251 else if (chan <= 106) group = 4; 252 else if (chan <= 114) group = 5; 253 else if (chan <= 122) group = 6; 254 else if (chan <= 130) group = 7; 255 else if (chan <= 138) group = 8; 256 else if (chan <= 144) group = 9; 257 else if (chan <= 155) group = 10; 258 else if (chan <= 161) group = 11; 259 else if (chan <= 171) group = 12; 260 else if (chan <= 177) group = 13; 261 else { 262 KASSERT(0, ("wrong 5GHz channel %d!\n", chan)); 263 return (-1); 264 } 265 } else { 266 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 267 return (-1); 268 } 269 270 return (group); 271 } 272 273 static void 274 r12a_get_txpower(struct rtwn_softc *sc, int chain, 275 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 276 { 277 struct r12a_softc *rs = sc->sc_priv; 278 int i, ridx, group, max_mcs, max_vht_mcs; 279 280 /* Determine channel group. */ 281 group = r12a_get_power_group(sc, c); 282 if (group == -1) { /* shouldn't happen */ 283 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 284 return; 285 } 286 287 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 288 max_vht_mcs = RTWN_RIDX_VHT_MCS(sc->ntxchains, 9) - 1; 289 290 /* XXX regulatory */ 291 /* XXX net80211 regulatory */ 292 293 if (IEEE80211_IS_CHAN_2GHZ(c)) { 294 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 295 power[ridx] = rs->cck_tx_pwr[chain][group]; 296 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 297 power[ridx] = rs->ht40_tx_pwr_2g[chain][group]; 298 299 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 300 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0]; 301 302 for (i = 0; i < sc->ntxchains; i++) { 303 uint8_t min_mcs; 304 uint8_t pwr_diff; 305 306 if (IEEE80211_IS_CHAN_VHT80(c)) { 307 /* Vendor driver uses HT40 values here. */ 308 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 309 } else 310 if (IEEE80211_IS_CHAN_HT40(c) || IEEE80211_IS_CHAN_VHT40(c)) 311 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 312 else 313 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i]; 314 315 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 316 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 317 power[ridx] += pwr_diff; 318 } 319 } else { /* 5GHz */ 320 /* OFDM + HT */ 321 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 322 power[ridx] = rs->ht40_tx_pwr_5g[chain][group]; 323 /* VHT */ 324 for (ridx = RTWN_RIDX_VHT_MCS_SHIFT; ridx <= max_vht_mcs; ridx++) 325 power[ridx] = rs->ht40_tx_pwr_5g[chain][group]; 326 327 /* Add power for OFDM rates */ 328 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 329 power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0]; 330 331 for (i = 0; i < sc->ntxchains; i++) { 332 uint8_t min_mcs; 333 uint8_t pwr_diff; 334 335 if (IEEE80211_IS_CHAN_VHT80(c)) { 336 /* TODO: calculate base value. */ 337 pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i]; 338 } else 339 if (IEEE80211_IS_CHAN_HT40(c) || IEEE80211_IS_CHAN_VHT40(c)) 340 pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i]; 341 else 342 pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i]; 343 344 /* Adjust HT rates */ 345 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 346 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 347 power[ridx] += pwr_diff; 348 349 /* Adjust VHT rates */ 350 for (ridx = RTWN_RIDX_VHT_MCS(i, 0); 351 ridx <= RTWN_RIDX_VHT_MCS(i, 9); 352 ridx++) 353 power[ridx] += pwr_diff; 354 355 } 356 } 357 358 /* Apply max limit. */ 359 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 360 if (power[ridx] > R92C_MAX_TX_PWR) 361 power[ridx] = R92C_MAX_TX_PWR; 362 } 363 for (ridx = RTWN_RIDX_VHT_MCS(0, 0); 364 ridx <= RTWN_RIDX_VHT_MCS(3, 9); 365 ridx++) { 366 if (power[ridx] > R92C_MAX_TX_PWR) 367 power[ridx] = R92C_MAX_TX_PWR; 368 } 369 370 #ifdef RTWN_DEBUG 371 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 372 /* Dump per-rate Tx power values. */ 373 printf("Tx power for chain %d:\n", chain); 374 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) 375 printf("Rate %d = %u\n", ridx, power[ridx]); 376 /* TODO: dump VHT 0..9 for each spatial stream */ 377 } 378 #endif 379 } 380 381 static void 382 r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 383 { 384 uint8_t power[RTWN_RIDX_COUNT]; 385 int i; 386 387 for (i = 0; i < sc->ntxchains; i++) { 388 memset(power, 0, sizeof(power)); 389 /* Compute per-rate Tx power values. */ 390 r12a_get_txpower(sc, i, c, power); 391 /* Write per-rate Tx power values to hardware. */ 392 r12a_write_txpower(sc, i, c, power); 393 } 394 } 395 396 void 397 r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c) 398 { 399 struct r12a_softc *rs = sc->sc_priv; 400 uint16_t chan = rtwn_chan2centieee(c); 401 402 if (rs->chip & R12A_CHIP_C_CUT) { 403 if (IEEE80211_IS_CHAN_HT40(c) && chan == 11) { 404 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00); 405 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); 406 } else { 407 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800); 408 409 if ((IEEE80211_IS_CHAN_B(c) || 410 IEEE80211_IS_CHAN_ANYG(c) || 411 IEEE80211_IS_CHAN_HT20(c)) && /* 2GHz, 20 MHz */ 412 (chan == 13 || chan == 14)) { 413 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 414 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 415 0, 0x40000000); 416 } else if (IEEE80211_IS_CHAN_HT40(c) || 417 IEEE80211_IS_CHAN_VHT40(c)) { 418 /* XXX double check! */ 419 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 420 0, 0x40000000); 421 } else if (IEEE80211_IS_CHAN_VHT80(c)) { 422 /* XXX double check! */ 423 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 424 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 425 0x40000000, 0); 426 } 427 } 428 } else { 429 /* Set ADC clock to 160M to resolve 2480 MHz spur. */ 430 if ((IEEE80211_IS_CHAN_B(c) || 431 IEEE80211_IS_CHAN_ANYG(c) || 432 IEEE80211_IS_CHAN_HT20(c)) && /* 2GHz, 20 MHz */ 433 (chan == 13 || chan == 14)) 434 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 435 else if (IEEE80211_IS_CHAN_2GHZ(c)) 436 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 437 } 438 } 439 440 static void 441 r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c) 442 { 443 struct ieee80211com *ic = &sc->sc_ic; 444 struct r12a_softc *rs = sc->sc_priv; 445 uint32_t basicrates; 446 uint8_t swing; 447 int i; 448 449 /* Check if band was changed. */ 450 if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) != 451 RTWN_STARTED && IEEE80211_IS_CHAN_5GHZ(c) ^ 452 !(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ)) 453 return; 454 455 /* Note: this only fetches the basic rates, not the full rateset */ 456 rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates, 457 NULL, NULL, 1); 458 if (IEEE80211_IS_CHAN_2GHZ(c)) { 459 rtwn_r12a_set_band_2ghz(sc, basicrates); 460 swing = rs->tx_bbswing_2g; 461 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 462 rtwn_r12a_set_band_5ghz(sc, basicrates); 463 swing = rs->tx_bbswing_5g; 464 } else { 465 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags)); 466 return; 467 } 468 469 /* XXX PATH_B is set by vendor driver. */ 470 for (i = 0; i < 2; i++) { 471 uint16_t val = 0; 472 473 switch ((swing >> i * 2) & 0x3) { 474 case 0: 475 val = 0x200; /* 0 dB */ 476 break; 477 case 1: 478 val = 0x16a; /* -3 dB */ 479 break; 480 case 2: 481 val = 0x101; /* -6 dB */ 482 break; 483 case 3: 484 val = 0xb6; /* -9 dB */ 485 break; 486 } 487 488 rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M, 489 val << R12A_TX_SCALE_SWING_S); 490 } 491 } 492 493 void 494 r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 495 { 496 uint32_t val; 497 uint16_t chan; 498 int i; 499 500 r12a_set_band(sc, c); 501 502 chan = rtwn_chan2centieee(c); 503 if (36 <= chan && chan <= 48) 504 val = 0x09280000; 505 else if (50 <= chan && chan <= 64) 506 val = 0x08a60000; 507 else if (100 <= chan && chan <= 116) 508 val = 0x08a40000; 509 else if (118 <= chan) 510 val = 0x08240000; 511 else 512 val = 0x12d40000; 513 514 rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val); 515 516 for (i = 0; i < sc->nrxchains; i++) { 517 if (36 <= chan && chan <= 64) 518 val = 0x10100; 519 else if (100 <= chan && chan <= 140) 520 val = 0x30100; 521 else if (140 < chan) 522 val = 0x50100; 523 else 524 val = 0x00000; 525 526 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val); 527 528 /* RTL8812AU-specific */ 529 rtwn_r12a_fix_spur(sc, c); 530 531 KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan)); 532 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan); 533 } 534 535 if (IEEE80211_IS_CHAN_VHT80(c)) { /* 80 MHz */ 536 uint8_t ext20 = 0, ext40 = 0; 537 uint8_t txsc; 538 /* calculate ext20/ext40 */ 539 if (c->ic_ieee > c->ic_vht_ch_freq1) { 540 if (c->ic_ieee - c->ic_vht_ch_freq1 == 2) { 541 ext20 = R12A_DATA_SEC_PRIM_UP_20; 542 ext40 = R12A_DATA_SEC_PRIM_UP_40; 543 } else { 544 ext20 = R12A_DATA_SEC_PRIM_UPPER_20; 545 ext40 = R12A_DATA_SEC_PRIM_UP_40; 546 } 547 } else { 548 if (c->ic_vht_ch_freq1 - c->ic_ieee == 2) { 549 ext20 = R12A_DATA_SEC_PRIM_DOWN_20; 550 ext40 = R12A_DATA_SEC_PRIM_DOWN_40; 551 } else { 552 ext20 = R12A_DATA_SEC_PRIM_LOWER_20; 553 ext40 = R12A_DATA_SEC_PRIM_DOWN_40; 554 } 555 } 556 /* Form txsc from sec20/sec40 config */ 557 txsc = SM(R12A_DATA_SEC_TXSC_20M, ext20); 558 txsc |= SM(R12A_DATA_SEC_TXSC_40M, ext40); 559 560 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0x100); 561 562 /* DATA_SEC, for ext20/ext40 */ 563 rtwn_write_1(sc, R12A_DATA_SEC, txsc); 564 565 /* ADCCLK */ 566 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300202); 567 568 /* ADC160 - Set bit 30 */ 569 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); 570 571 /* ADCCLK, ext20 */ 572 /* discard high 4 bits */ 573 val = rtwn_bb_read(sc, R12A_RFMOD); 574 val = RW(val, R12A_RFMOD_EXT_CHAN, ext20); 575 rtwn_bb_write(sc, R12A_RFMOD, val); 576 577 /* CCA2ND, ext20 */ 578 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC); 579 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext20); 580 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val); 581 582 /* PEAK_TH */ 583 if (rtwn_read_1(sc, 0x837) & 0x04) 584 val = 0x01400000; 585 else if (sc->nrxchains == 2 && sc->ntxchains == 2) 586 val = 0x01800000; 587 else 588 val = 0x01c00000; 589 590 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 591 /* BWMASK */ 592 val = 0x0; 593 594 } else if (IEEE80211_IS_CHAN_HT40(c) || 595 IEEE80211_IS_CHAN_VHT40(c)) { /* 40 MHz */ 596 uint8_t ext_chan; 597 598 if (IEEE80211_IS_CHAN_HT40U(c)) 599 ext_chan = R12A_DATA_SEC_PRIM_DOWN_20; 600 else 601 ext_chan = R12A_DATA_SEC_PRIM_UP_20; 602 603 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80); 604 rtwn_write_1(sc, R12A_DATA_SEC, ext_chan); 605 606 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201); 607 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 608 609 /* discard high 4 bits */ 610 val = rtwn_bb_read(sc, R12A_RFMOD); 611 val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan); 612 rtwn_bb_write(sc, R12A_RFMOD, val); 613 614 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC); 615 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan); 616 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val); 617 618 if (rtwn_read_1(sc, 0x837) & 0x04) 619 val = 0x01800000; 620 else if (sc->nrxchains == 2 && sc->ntxchains == 2) 621 val = 0x01c00000; 622 else 623 val = 0x02000000; 624 625 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 626 627 if (IEEE80211_IS_CHAN_HT40U(c)) 628 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0); 629 else 630 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10); 631 632 val = 0x400; 633 } else { /* 20 MHz */ 634 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0); 635 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT); 636 637 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200); 638 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 639 640 if (sc->nrxchains == 2 && sc->ntxchains == 2) 641 val = 0x01c00000; 642 else 643 val = 0x02000000; 644 645 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 646 647 val = 0xc00; 648 } 649 650 /* RTL8812AU-specific */ 651 rtwn_r12a_fix_spur(sc, c); 652 653 for (i = 0; i < sc->nrxchains; i++) 654 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val); 655 656 /* Set Tx power for this new channel. */ 657 r12a_set_txpower(sc, c); 658 } 659 660 void 661 r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates) 662 { 663 struct r12a_softc *rs = sc->sc_priv; 664 665 /* Enable CCK / OFDM. */ 666 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, 667 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); 668 669 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01); 670 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000); 671 672 /* Select AGC table. */ 673 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0); 674 675 switch (rs->rfe_type) { 676 case 0: 677 case 1: 678 case 2: 679 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 680 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 681 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 682 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 683 break; 684 case 3: 685 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770); 686 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770); 687 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 688 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 689 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 690 break; 691 case 4: 692 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 693 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 694 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000); 695 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000); 696 break; 697 case 5: 698 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77); 699 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 700 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0); 701 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 702 break; 703 default: 704 break; 705 } 706 707 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10); 708 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000); 709 710 /* Write basic rates. */ 711 rtwn_set_basicrates(sc, basicrates); 712 713 rtwn_write_1(sc, R12A_CCK_CHECK, 0); 714 } 715 716 void 717 r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates) 718 { 719 struct r12a_softc *rs = sc->sc_priv; 720 int ntries; 721 722 rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ); 723 724 for (ntries = 0; ntries < 100; ntries++) { 725 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30) 726 break; 727 728 rtwn_delay(sc, 25); 729 } 730 if (ntries == 100) { 731 device_printf(sc->sc_dev, 732 "%s: TXPKT_EMPTY check failed (%04X)\n", 733 __func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY)); 734 } 735 736 /* Enable OFDM. */ 737 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK, 738 R12A_OFDMCCK_EN_OFDM); 739 740 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02); 741 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000); 742 743 /* Select AGC table. */ 744 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01); 745 746 switch (rs->rfe_type) { 747 case 0: 748 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 749 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 750 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 751 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 752 break; 753 case 1: 754 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 755 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 756 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 757 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 758 break; 759 case 2: 760 case 4: 761 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777); 762 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 763 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 764 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 765 break; 766 case 3: 767 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717); 768 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717); 769 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 770 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 771 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 772 break; 773 case 5: 774 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33); 775 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 776 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01); 777 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 778 break; 779 default: 780 break; 781 } 782 783 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0); 784 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000); 785 786 /* Write basic rates. */ 787 rtwn_set_basicrates(sc, basicrates); 788 } 789