1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 #include <dev/rtwn/if_rtwn_ridx.h> 56 #include <dev/rtwn/if_rtwn_rx.h> 57 58 #include <dev/rtwn/rtl8812a/r12a.h> 59 #include <dev/rtwn/rtl8812a/r12a_reg.h> 60 #include <dev/rtwn/rtl8812a/r12a_var.h> 61 62 static void 63 r12a_write_txpower_ht(struct rtwn_softc *sc, int chain, 64 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 65 { 66 67 /* Write per-MCS Tx power. */ 68 rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain), 69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) | 70 SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_HT_MCS(1)]) | 71 SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_HT_MCS(2)]) | 72 SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_HT_MCS(3)])); 73 rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain), 74 SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_HT_MCS(4)]) | 75 SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_HT_MCS(5)]) | 76 SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_HT_MCS(6)]) | 77 SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_HT_MCS(7)])); 78 if (sc->ntxchains >= 2) { 79 rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain), 80 SM(R12A_TXAGC_MCS8, power[RTWN_RIDX_HT_MCS(8)]) | 81 SM(R12A_TXAGC_MCS9, power[RTWN_RIDX_HT_MCS(9)]) | 82 SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) | 83 SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)])); 84 rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain), 85 SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) | 86 SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) | 87 SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) | 88 SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)])); 89 } 90 91 /* TODO: HT MCS 16 -> 31 */ 92 } 93 94 static void 95 r12a_write_txpower_vht(struct rtwn_softc *sc, int chain, 96 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 97 { 98 99 /* 1SS, MCS 0..3 */ 100 rtwn_bb_write(sc, R12A_TXAGC_NSS1IX3_1IX0(chain), 101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) | 102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) | 103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) | 104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)])); 105 106 /* 1SS, MCS 4..7 */ 107 rtwn_bb_write(sc, R12A_TXAGC_NSS1IX7_1IX4(chain), 108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) | 109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) | 110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) | 111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)])); 112 113 /* 1SS, MCS 8,9 ; 2SS MCS0, 1 */ 114 if (sc->ntxchains == 1) { 115 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX1_1IX8(chain), 116 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) | 117 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) | 118 SM(R12A_TXAGC_NSS2_MCS0, 0) | 119 SM(R12A_TXAGC_NSS2_MCS1, 0)); 120 } else { 121 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX1_1IX8(chain), 122 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) | 123 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) | 124 SM(R12A_TXAGC_NSS2_MCS0, power[RTWN_RIDX_VHT_MCS(1, 0)]) | 125 SM(R12A_TXAGC_NSS2_MCS1, power[RTWN_RIDX_VHT_MCS(1, 1)])); 126 } 127 128 /* 2SS MCS 2..5 */ 129 if (sc->ntxchains > 1) { 130 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX5_2IX2(chain), 131 SM(R12A_TXAGC_NSS2_MCS2, power[RTWN_RIDX_VHT_MCS(1, 2)]) | 132 SM(R12A_TXAGC_NSS2_MCS3, power[RTWN_RIDX_VHT_MCS(1, 3)]) | 133 SM(R12A_TXAGC_NSS2_MCS4, power[RTWN_RIDX_VHT_MCS(1, 4)]) | 134 SM(R12A_TXAGC_NSS2_MCS5, power[RTWN_RIDX_VHT_MCS(1, 5)])); 135 } 136 137 /* 2SS MCS 6..9 */ 138 if (sc->ntxchains > 1) { 139 rtwn_bb_write(sc, R12A_TXAGC_NSS2IX9_2IX6(chain), 140 SM(R12A_TXAGC_NSS2_MCS2, power[RTWN_RIDX_VHT_MCS(1, 6)]) | 141 SM(R12A_TXAGC_NSS2_MCS3, power[RTWN_RIDX_VHT_MCS(1, 7)]) | 142 SM(R12A_TXAGC_NSS2_MCS4, power[RTWN_RIDX_VHT_MCS(1, 8)]) | 143 SM(R12A_TXAGC_NSS2_MCS5, power[RTWN_RIDX_VHT_MCS(1, 9)])); 144 } 145 146 /* TODO: 3SS, 4SS VHT rates */ 147 } 148 149 150 static void 151 r12a_write_txpower_cck(struct rtwn_softc *sc, int chain, 152 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 153 { 154 155 if (IEEE80211_IS_CHAN_2GHZ(c)) { 156 /* Write per-CCK rate Tx power. */ 157 rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain), 158 SM(R12A_TXAGC_CCK1, power[RTWN_RIDX_CCK1]) | 159 SM(R12A_TXAGC_CCK2, power[RTWN_RIDX_CCK2]) | 160 SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) | 161 SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11])); 162 } 163 } 164 165 static void 166 r12a_write_txpower_ofdm(struct rtwn_softc *sc, int chain, 167 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 168 { 169 170 /* Write per-OFDM rate Tx power. */ 171 rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain), 172 SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) | 173 SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) | 174 SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) | 175 SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18])); 176 rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain), 177 SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) | 178 SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) | 179 SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) | 180 SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54])); 181 } 182 183 static void 184 r12a_write_txpower(struct rtwn_softc *sc, int chain, 185 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 186 { 187 188 r12a_write_txpower_cck(sc, chain, c, power); 189 r12a_write_txpower_ofdm(sc, chain, c, power); 190 r12a_write_txpower_ht(sc, chain, c, power); 191 r12a_write_txpower_vht(sc, chain, c, power); 192 } 193 194 static int 195 r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 196 { 197 uint8_t chan; 198 int group; 199 200 chan = rtwn_chan2centieee(c); 201 if (IEEE80211_IS_CHAN_2GHZ(c)) { 202 if (chan <= 2) group = 0; 203 else if (chan <= 5) group = 1; 204 else if (chan <= 8) group = 2; 205 else if (chan <= 11) group = 3; 206 else if (chan <= 14) group = 4; 207 else { 208 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 209 return (-1); 210 } 211 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 212 if (chan < 36) 213 return (-1); 214 215 if (chan <= 42) group = 0; 216 else if (chan <= 48) group = 1; 217 else if (chan <= 58) group = 2; 218 else if (chan <= 64) group = 3; 219 else if (chan <= 106) group = 4; 220 else if (chan <= 114) group = 5; 221 else if (chan <= 122) group = 6; 222 else if (chan <= 130) group = 7; 223 else if (chan <= 138) group = 8; 224 else if (chan <= 144) group = 9; 225 else if (chan <= 155) group = 10; 226 else if (chan <= 161) group = 11; 227 else if (chan <= 171) group = 12; 228 else if (chan <= 177) group = 13; 229 else { 230 KASSERT(0, ("wrong 5GHz channel %d!\n", chan)); 231 return (-1); 232 } 233 } else { 234 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 235 return (-1); 236 } 237 238 return (group); 239 } 240 241 static void 242 r12a_get_txpower(struct rtwn_softc *sc, int chain, 243 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 244 { 245 struct r12a_softc *rs = sc->sc_priv; 246 int i, ridx, group, max_mcs, max_vht_mcs; 247 248 /* Determine channel group. */ 249 group = r12a_get_power_group(sc, c); 250 if (group == -1) { /* shouldn't happen */ 251 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 252 return; 253 } 254 255 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 256 max_vht_mcs = RTWN_RIDX_VHT_MCS(sc->ntxchains, 9) - 1; 257 258 /* XXX regulatory */ 259 /* XXX net80211 regulatory */ 260 261 if (IEEE80211_IS_CHAN_2GHZ(c)) { 262 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 263 power[ridx] = rs->cck_tx_pwr[chain][group]; 264 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 265 power[ridx] = rs->ht40_tx_pwr_2g[chain][group]; 266 267 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 268 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0]; 269 270 for (i = 0; i < sc->ntxchains; i++) { 271 uint8_t min_mcs; 272 uint8_t pwr_diff; 273 274 if (IEEE80211_IS_CHAN_VHT80(c)) { 275 /* Vendor driver uses HT40 values here. */ 276 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 277 } else 278 if (IEEE80211_IS_CHAN_HT40(c) || IEEE80211_IS_CHAN_VHT40(c)) 279 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 280 else 281 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i]; 282 283 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 284 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 285 power[ridx] += pwr_diff; 286 } 287 } else { /* 5GHz */ 288 /* OFDM + HT */ 289 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 290 power[ridx] = rs->ht40_tx_pwr_5g[chain][group]; 291 /* VHT */ 292 for (ridx = RTWN_RIDX_VHT_MCS_SHIFT; ridx <= max_vht_mcs; ridx++) 293 power[ridx] = rs->ht40_tx_pwr_5g[chain][group]; 294 295 /* Add power for OFDM rates */ 296 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 297 power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0]; 298 299 for (i = 0; i < sc->ntxchains; i++) { 300 uint8_t min_mcs; 301 uint8_t pwr_diff; 302 303 if (IEEE80211_IS_CHAN_VHT80(c)) { 304 /* TODO: calculate base value. */ 305 pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i]; 306 } else 307 if (IEEE80211_IS_CHAN_HT40(c) || IEEE80211_IS_CHAN_VHT40(c)) 308 pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i]; 309 else 310 pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i]; 311 312 /* Adjust HT rates */ 313 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 314 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 315 power[ridx] += pwr_diff; 316 317 /* Adjust VHT rates */ 318 for (ridx = RTWN_RIDX_VHT_MCS(i, 0); 319 ridx <= RTWN_RIDX_VHT_MCS(i, 9); 320 ridx++) 321 power[ridx] += pwr_diff; 322 323 } 324 } 325 326 /* Apply max limit. */ 327 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 328 if (power[ridx] > R92C_MAX_TX_PWR) 329 power[ridx] = R92C_MAX_TX_PWR; 330 } 331 for (ridx = RTWN_RIDX_VHT_MCS(0, 0); 332 ridx <= RTWN_RIDX_VHT_MCS(3, 9); 333 ridx++) { 334 if (power[ridx] > R92C_MAX_TX_PWR) 335 power[ridx] = R92C_MAX_TX_PWR; 336 } 337 338 #ifdef RTWN_DEBUG 339 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 340 /* Dump per-rate Tx power values. */ 341 printf("Tx power for chain %d:\n", chain); 342 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) 343 printf("Rate %d = %u\n", ridx, power[ridx]); 344 /* TODO: dump VHT 0..9 for each spatial stream */ 345 } 346 #endif 347 } 348 349 static void 350 r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 351 { 352 uint8_t power[RTWN_RIDX_COUNT]; 353 int i; 354 355 for (i = 0; i < sc->ntxchains; i++) { 356 memset(power, 0, sizeof(power)); 357 /* Compute per-rate Tx power values. */ 358 r12a_get_txpower(sc, i, c, power); 359 /* Write per-rate Tx power values to hardware. */ 360 r12a_write_txpower(sc, i, c, power); 361 } 362 } 363 364 void 365 r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c) 366 { 367 struct r12a_softc *rs = sc->sc_priv; 368 uint16_t chan = rtwn_chan2centieee(c); 369 370 if (rs->chip & R12A_CHIP_C_CUT) { 371 if (IEEE80211_IS_CHAN_HT40(c) && chan == 11) { 372 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00); 373 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); 374 } else { 375 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800); 376 377 if ((IEEE80211_IS_CHAN_B(c) || 378 IEEE80211_IS_CHAN_ANYG(c) || 379 IEEE80211_IS_CHAN_HT20(c)) && /* 2GHz, 20 MHz */ 380 (chan == 13 || chan == 14)) { 381 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 382 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 383 0, 0x40000000); 384 } else if (IEEE80211_IS_CHAN_HT40(c) || 385 IEEE80211_IS_CHAN_VHT40(c)) { 386 /* XXX double check! */ 387 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 388 0, 0x40000000); 389 } else if (IEEE80211_IS_CHAN_VHT80(c)) { 390 /* XXX double check! */ 391 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 392 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 393 0x40000000, 0); 394 } 395 } 396 } else { 397 /* Set ADC clock to 160M to resolve 2480 MHz spur. */ 398 if ((IEEE80211_IS_CHAN_B(c) || 399 IEEE80211_IS_CHAN_ANYG(c) || 400 IEEE80211_IS_CHAN_HT20(c)) && /* 2GHz, 20 MHz */ 401 (chan == 13 || chan == 14)) 402 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 403 else if (IEEE80211_IS_CHAN_2GHZ(c)) 404 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 405 } 406 } 407 408 static void 409 r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c) 410 { 411 struct ieee80211com *ic = &sc->sc_ic; 412 struct r12a_softc *rs = sc->sc_priv; 413 uint32_t basicrates; 414 uint8_t swing; 415 int i; 416 417 /* Check if band was changed. */ 418 if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) != 419 RTWN_STARTED && IEEE80211_IS_CHAN_5GHZ(c) ^ 420 !(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ)) 421 return; 422 423 rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates, 424 NULL, 1); 425 if (IEEE80211_IS_CHAN_2GHZ(c)) { 426 rtwn_r12a_set_band_2ghz(sc, basicrates); 427 swing = rs->tx_bbswing_2g; 428 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 429 rtwn_r12a_set_band_5ghz(sc, basicrates); 430 swing = rs->tx_bbswing_5g; 431 } else { 432 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags)); 433 return; 434 } 435 436 /* XXX PATH_B is set by vendor driver. */ 437 for (i = 0; i < 2; i++) { 438 uint16_t val = 0; 439 440 switch ((swing >> i * 2) & 0x3) { 441 case 0: 442 val = 0x200; /* 0 dB */ 443 break; 444 case 1: 445 val = 0x16a; /* -3 dB */ 446 break; 447 case 2: 448 val = 0x101; /* -6 dB */ 449 break; 450 case 3: 451 val = 0xb6; /* -9 dB */ 452 break; 453 } 454 455 rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M, 456 val << R12A_TX_SCALE_SWING_S); 457 } 458 } 459 460 void 461 r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 462 { 463 uint32_t val; 464 uint16_t chan; 465 int i; 466 467 r12a_set_band(sc, c); 468 469 chan = rtwn_chan2centieee(c); 470 if (36 <= chan && chan <= 48) 471 val = 0x09280000; 472 else if (50 <= chan && chan <= 64) 473 val = 0x08a60000; 474 else if (100 <= chan && chan <= 116) 475 val = 0x08a40000; 476 else if (118 <= chan) 477 val = 0x08240000; 478 else 479 val = 0x12d40000; 480 481 rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val); 482 483 for (i = 0; i < sc->nrxchains; i++) { 484 if (36 <= chan && chan <= 64) 485 val = 0x10100; 486 else if (100 <= chan && chan <= 140) 487 val = 0x30100; 488 else if (140 < chan) 489 val = 0x50100; 490 else 491 val = 0x00000; 492 493 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val); 494 495 /* RTL8812AU-specific */ 496 rtwn_r12a_fix_spur(sc, c); 497 498 KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan)); 499 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan); 500 } 501 502 if (IEEE80211_IS_CHAN_VHT80(c)) { /* 80 MHz */ 503 uint8_t ext20 = 0, ext40 = 0; 504 uint8_t txsc; 505 /* calculate ext20/ext40 */ 506 if (c->ic_ieee > c->ic_vht_ch_freq1) { 507 if (c->ic_ieee - c->ic_vht_ch_freq1 == 2) { 508 ext20 = R12A_DATA_SEC_PRIM_UP_20; 509 ext40 = R12A_DATA_SEC_PRIM_UP_40; 510 } else { 511 ext20 = R12A_DATA_SEC_PRIM_UPPER_20; 512 ext40 = R12A_DATA_SEC_PRIM_UP_40; 513 } 514 } else { 515 if (c->ic_vht_ch_freq1 - c->ic_ieee == 2) { 516 ext20 = R12A_DATA_SEC_PRIM_DOWN_20; 517 ext40 = R12A_DATA_SEC_PRIM_DOWN_40; 518 } else { 519 ext20 = R12A_DATA_SEC_PRIM_LOWER_20; 520 ext40 = R12A_DATA_SEC_PRIM_DOWN_40; 521 } 522 } 523 /* Form txsc from sec20/sec40 config */ 524 txsc = SM(R12A_DATA_SEC_TXSC_20M, ext20); 525 txsc |= SM(R12A_DATA_SEC_TXSC_40M, ext40); 526 527 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0x100); 528 529 /* DATA_SEC, for ext20/ext40 */ 530 rtwn_write_1(sc, R12A_DATA_SEC, txsc); 531 532 /* ADCCLK */ 533 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300202); 534 535 /* ADC160 - Set bit 30 */ 536 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); 537 538 /* ADCCLK, ext20 */ 539 /* discard high 4 bits */ 540 val = rtwn_bb_read(sc, R12A_RFMOD); 541 val = RW(val, R12A_RFMOD_EXT_CHAN, ext20); 542 rtwn_bb_write(sc, R12A_RFMOD, val); 543 544 /* CCA2ND, ext20 */ 545 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC); 546 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext20); 547 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val); 548 549 /* PEAK_TH */ 550 if (rtwn_read_1(sc, 0x837) & 0x04) 551 val = 0x01400000; 552 else if (sc->nrxchains == 2 && sc->ntxchains == 2) 553 val = 0x01800000; 554 else 555 val = 0x01c00000; 556 557 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 558 /* BWMASK */ 559 val = 0x0; 560 561 } else if (IEEE80211_IS_CHAN_HT40(c) || 562 IEEE80211_IS_CHAN_VHT40(c)) { /* 40 MHz */ 563 uint8_t ext_chan; 564 565 if (IEEE80211_IS_CHAN_HT40U(c)) 566 ext_chan = R12A_DATA_SEC_PRIM_DOWN_20; 567 else 568 ext_chan = R12A_DATA_SEC_PRIM_UP_20; 569 570 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80); 571 rtwn_write_1(sc, R12A_DATA_SEC, ext_chan); 572 573 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201); 574 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 575 576 /* discard high 4 bits */ 577 val = rtwn_bb_read(sc, R12A_RFMOD); 578 val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan); 579 rtwn_bb_write(sc, R12A_RFMOD, val); 580 581 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC); 582 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan); 583 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val); 584 585 if (rtwn_read_1(sc, 0x837) & 0x04) 586 val = 0x01800000; 587 else if (sc->nrxchains == 2 && sc->ntxchains == 2) 588 val = 0x01c00000; 589 else 590 val = 0x02000000; 591 592 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 593 594 if (IEEE80211_IS_CHAN_HT40U(c)) 595 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0); 596 else 597 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10); 598 599 val = 0x400; 600 } else { /* 20 MHz */ 601 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0); 602 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT); 603 604 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200); 605 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 606 607 if (sc->nrxchains == 2 && sc->ntxchains == 2) 608 val = 0x01c00000; 609 else 610 val = 0x02000000; 611 612 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 613 614 val = 0xc00; 615 } 616 617 /* RTL8812AU-specific */ 618 rtwn_r12a_fix_spur(sc, c); 619 620 for (i = 0; i < sc->nrxchains; i++) 621 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val); 622 623 /* Set Tx power for this new channel. */ 624 r12a_set_txpower(sc, c); 625 } 626 627 void 628 r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates) 629 { 630 struct r12a_softc *rs = sc->sc_priv; 631 632 /* Enable CCK / OFDM. */ 633 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, 634 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); 635 636 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01); 637 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000); 638 639 /* Select AGC table. */ 640 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0); 641 642 switch (rs->rfe_type) { 643 case 0: 644 case 1: 645 case 2: 646 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 647 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 648 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 649 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 650 break; 651 case 3: 652 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770); 653 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770); 654 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 655 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 656 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 657 break; 658 case 4: 659 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 660 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 661 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000); 662 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000); 663 break; 664 case 5: 665 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77); 666 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 667 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0); 668 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 669 break; 670 default: 671 break; 672 } 673 674 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10); 675 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000); 676 677 /* Write basic rates. */ 678 rtwn_set_basicrates(sc, basicrates); 679 680 rtwn_write_1(sc, R12A_CCK_CHECK, 0); 681 } 682 683 void 684 r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates) 685 { 686 struct r12a_softc *rs = sc->sc_priv; 687 int ntries; 688 689 rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ); 690 691 for (ntries = 0; ntries < 100; ntries++) { 692 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30) 693 break; 694 695 rtwn_delay(sc, 25); 696 } 697 if (ntries == 100) { 698 device_printf(sc->sc_dev, 699 "%s: TXPKT_EMPTY check failed (%04X)\n", 700 __func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY)); 701 } 702 703 /* Enable OFDM. */ 704 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK, 705 R12A_OFDMCCK_EN_OFDM); 706 707 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02); 708 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000); 709 710 /* Select AGC table. */ 711 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01); 712 713 switch (rs->rfe_type) { 714 case 0: 715 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 716 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 717 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 718 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 719 break; 720 case 1: 721 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 722 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 723 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 724 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 725 break; 726 case 2: 727 case 4: 728 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777); 729 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 730 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 731 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 732 break; 733 case 3: 734 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717); 735 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717); 736 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 737 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 738 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 739 break; 740 case 5: 741 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33); 742 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 743 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01); 744 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 745 break; 746 default: 747 break; 748 } 749 750 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0); 751 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000); 752 753 /* Write basic rates. */ 754 rtwn_set_basicrates(sc, basicrates); 755 } 756