1 /*- 2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 #include <dev/rtwn/if_rtwn_ridx.h> 56 #include <dev/rtwn/if_rtwn_rx.h> 57 58 #include <dev/rtwn/rtl8812a/r12a.h> 59 #include <dev/rtwn/rtl8812a/r12a_reg.h> 60 #include <dev/rtwn/rtl8812a/r12a_var.h> 61 62 static void 63 r12a_write_txpower(struct rtwn_softc *sc, int chain, 64 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 65 { 66 67 if (IEEE80211_IS_CHAN_2GHZ(c)) { 68 /* Write per-CCK rate Tx power. */ 69 rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain), 70 SM(R12A_TXAGC_CCK1, power[RTWN_RIDX_CCK1]) | 71 SM(R12A_TXAGC_CCK2, power[RTWN_RIDX_CCK2]) | 72 SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) | 73 SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11])); 74 } 75 76 /* Write per-OFDM rate Tx power. */ 77 rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain), 78 SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) | 79 SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) | 80 SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) | 81 SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18])); 82 rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain), 83 SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) | 84 SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) | 85 SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) | 86 SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54])); 87 /* Write per-MCS Tx power. */ 88 rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain), 89 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) | 90 SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_HT_MCS(1)]) | 91 SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_HT_MCS(2)]) | 92 SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_HT_MCS(3)])); 93 rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain), 94 SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_HT_MCS(4)]) | 95 SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_HT_MCS(5)]) | 96 SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_HT_MCS(6)]) | 97 SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_HT_MCS(7)])); 98 if (sc->ntxchains >= 2) { 99 rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain), 100 SM(R12A_TXAGC_MCS8, power[RTWN_RIDX_HT_MCS(8)]) | 101 SM(R12A_TXAGC_MCS9, power[RTWN_RIDX_HT_MCS(9)]) | 102 SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) | 103 SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)])); 104 rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain), 105 SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) | 106 SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) | 107 SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) | 108 SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)])); 109 } 110 111 /* TODO: VHT rates */ 112 } 113 114 static int 115 r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 116 { 117 uint8_t chan; 118 int group; 119 120 chan = rtwn_chan2centieee(c); 121 if (IEEE80211_IS_CHAN_2GHZ(c)) { 122 if (chan <= 2) group = 0; 123 else if (chan <= 5) group = 1; 124 else if (chan <= 8) group = 2; 125 else if (chan <= 11) group = 3; 126 else if (chan <= 14) group = 4; 127 else { 128 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 129 return (-1); 130 } 131 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 132 if (chan < 36) 133 return (-1); 134 135 if (chan <= 42) group = 0; 136 else if (chan <= 48) group = 1; 137 else if (chan <= 58) group = 2; 138 else if (chan <= 64) group = 3; 139 else if (chan <= 106) group = 4; 140 else if (chan <= 114) group = 5; 141 else if (chan <= 122) group = 6; 142 else if (chan <= 130) group = 7; 143 else if (chan <= 138) group = 8; 144 else if (chan <= 144) group = 9; 145 else if (chan <= 155) group = 10; 146 else if (chan <= 161) group = 11; 147 else if (chan <= 171) group = 12; 148 else if (chan <= 177) group = 13; 149 else { 150 KASSERT(0, ("wrong 5GHz channel %d!\n", chan)); 151 return (-1); 152 } 153 } else { 154 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 155 return (-1); 156 } 157 158 return (group); 159 } 160 161 static void 162 r12a_get_txpower(struct rtwn_softc *sc, int chain, 163 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 164 { 165 struct r12a_softc *rs = sc->sc_priv; 166 int i, ridx, group, max_mcs; 167 168 /* Determine channel group. */ 169 group = r12a_get_power_group(sc, c); 170 if (group == -1) { /* shouldn't happen */ 171 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 172 return; 173 } 174 175 /* TODO: VHT rates. */ 176 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 177 178 /* XXX regulatory */ 179 /* XXX net80211 regulatory */ 180 181 if (IEEE80211_IS_CHAN_2GHZ(c)) { 182 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 183 power[ridx] = rs->cck_tx_pwr[chain][group]; 184 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 185 power[ridx] = rs->ht40_tx_pwr_2g[chain][group]; 186 187 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 188 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0]; 189 190 for (i = 0; i < sc->ntxchains; i++) { 191 uint8_t min_mcs; 192 uint8_t pwr_diff; 193 194 #ifdef notyet 195 if (IEEE80211_IS_CHAN_HT80(c)) { 196 /* Vendor driver uses HT40 values here. */ 197 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 198 } else 199 #endif 200 if (IEEE80211_IS_CHAN_HT40(c)) 201 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 202 else 203 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i]; 204 205 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 206 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 207 power[ridx] += pwr_diff; 208 } 209 } else { /* 5GHz */ 210 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 211 power[ridx] = rs->ht40_tx_pwr_5g[chain][group]; 212 213 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 214 power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0]; 215 216 for (i = 0; i < sc->ntxchains; i++) { 217 uint8_t min_mcs; 218 uint8_t pwr_diff; 219 220 #ifdef notyet 221 if (IEEE80211_IS_CHAN_HT80(c)) { 222 /* TODO: calculate base value. */ 223 pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i]; 224 } else 225 #endif 226 if (IEEE80211_IS_CHAN_HT40(c)) 227 pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i]; 228 else 229 pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i]; 230 231 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 232 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 233 power[ridx] += pwr_diff; 234 } 235 } 236 237 /* Apply max limit. */ 238 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 239 if (power[ridx] > R92C_MAX_TX_PWR) 240 power[ridx] = R92C_MAX_TX_PWR; 241 } 242 243 #ifdef RTWN_DEBUG 244 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 245 /* Dump per-rate Tx power values. */ 246 printf("Tx power for chain %d:\n", chain); 247 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) 248 printf("Rate %d = %u\n", ridx, power[ridx]); 249 } 250 #endif 251 } 252 253 static void 254 r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 255 { 256 uint8_t power[RTWN_RIDX_COUNT]; 257 int i; 258 259 for (i = 0; i < sc->ntxchains; i++) { 260 memset(power, 0, sizeof(power)); 261 /* Compute per-rate Tx power values. */ 262 r12a_get_txpower(sc, i, c, power); 263 /* Write per-rate Tx power values to hardware. */ 264 r12a_write_txpower(sc, i, c, power); 265 } 266 } 267 268 void 269 r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c) 270 { 271 struct r12a_softc *rs = sc->sc_priv; 272 uint16_t chan = rtwn_chan2centieee(c); 273 274 if (rs->chip & R12A_CHIP_C_CUT) { 275 if (IEEE80211_IS_CHAN_HT40(c) && chan == 11) { 276 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00); 277 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000); 278 } else { 279 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800); 280 281 if (!IEEE80211_IS_CHAN_HT40(c) && /* 20 MHz */ 282 (chan == 13 || chan == 14)) { 283 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 284 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 285 0, 0x40000000); 286 } else { /* !80 Mhz */ 287 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 288 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 289 0x40000000, 0); 290 } 291 } 292 } else { 293 /* Set ADC clock to 160M to resolve 2480 MHz spur. */ 294 if (!IEEE80211_IS_CHAN_HT40(c) && /* 20 MHz */ 295 (chan == 13 || chan == 14)) 296 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300); 297 else if (IEEE80211_IS_CHAN_2GHZ(c)) 298 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200); 299 } 300 } 301 302 static void 303 r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c) 304 { 305 struct ieee80211com *ic = &sc->sc_ic; 306 struct r12a_softc *rs = sc->sc_priv; 307 uint32_t basicrates; 308 uint8_t swing; 309 int i; 310 311 /* Check if band was changed. */ 312 if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) != 313 RTWN_STARTED && IEEE80211_IS_CHAN_5GHZ(c) ^ 314 !(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ)) 315 return; 316 317 rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates, 318 NULL, 1); 319 if (IEEE80211_IS_CHAN_2GHZ(c)) { 320 rtwn_r12a_set_band_2ghz(sc, basicrates); 321 swing = rs->tx_bbswing_2g; 322 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 323 rtwn_r12a_set_band_5ghz(sc, basicrates); 324 swing = rs->tx_bbswing_5g; 325 } else { 326 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags)); 327 return; 328 } 329 330 /* XXX PATH_B is set by vendor driver. */ 331 for (i = 0; i < 2; i++) { 332 uint16_t val = 0; 333 334 switch ((swing >> i * 2) & 0x3) { 335 case 0: 336 val = 0x200; /* 0 dB */ 337 break; 338 case 1: 339 val = 0x16a; /* -3 dB */ 340 break; 341 case 2: 342 val = 0x101; /* -6 dB */ 343 break; 344 case 3: 345 val = 0xb6; /* -9 dB */ 346 break; 347 } 348 349 rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M, 350 val << R12A_TX_SCALE_SWING_S); 351 } 352 } 353 354 void 355 r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 356 { 357 uint32_t val; 358 uint16_t chan; 359 int i; 360 361 r12a_set_band(sc, c); 362 363 chan = rtwn_chan2centieee(c); 364 if (36 <= chan && chan <= 48) 365 val = 0x09280000; 366 else if (50 <= chan && chan <= 64) 367 val = 0x08a60000; 368 else if (100 <= chan && chan <= 116) 369 val = 0x08a40000; 370 else if (118 <= chan) 371 val = 0x08240000; 372 else 373 val = 0x12d40000; 374 375 rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val); 376 377 for (i = 0; i < sc->nrxchains; i++) { 378 if (36 <= chan && chan <= 64) 379 val = 0x10100; 380 else if (100 <= chan && chan <= 140) 381 val = 0x30100; 382 else if (140 < chan) 383 val = 0x50100; 384 else 385 val = 0x00000; 386 387 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val); 388 389 /* RTL8812AU-specific */ 390 rtwn_r12a_fix_spur(sc, c); 391 392 KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan)); 393 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan); 394 } 395 396 #ifdef notyet 397 if (IEEE80211_IS_CHAN_HT80(c)) { /* 80 MHz */ 398 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x80, 0x100); 399 400 /* TODO */ 401 402 val = 0x0; 403 } else 404 #endif 405 if (IEEE80211_IS_CHAN_HT40(c)) { /* 40 MHz */ 406 uint8_t ext_chan; 407 408 if (IEEE80211_IS_CHAN_HT40U(c)) 409 ext_chan = R12A_DATA_SEC_PRIM_DOWN_20; 410 else 411 ext_chan = R12A_DATA_SEC_PRIM_UP_20; 412 413 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80); 414 rtwn_write_1(sc, R12A_DATA_SEC, ext_chan); 415 416 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201); 417 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 418 419 /* discard high 4 bits */ 420 val = rtwn_bb_read(sc, R12A_RFMOD); 421 val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan); 422 rtwn_bb_write(sc, R12A_RFMOD, val); 423 424 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC); 425 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan); 426 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val); 427 428 if (rtwn_read_1(sc, 0x837) & 0x04) 429 val = 0x01800000; 430 else if (sc->nrxchains == 2 && sc->ntxchains == 2) 431 val = 0x01c00000; 432 else 433 val = 0x02000000; 434 435 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 436 437 if (IEEE80211_IS_CHAN_HT40U(c)) 438 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0); 439 else 440 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10); 441 442 val = 0x400; 443 } else { /* 20 MHz */ 444 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0); 445 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT); 446 447 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200); 448 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0); 449 450 if (sc->nrxchains == 2 && sc->ntxchains == 2) 451 val = 0x01c00000; 452 else 453 val = 0x02000000; 454 455 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val); 456 457 val = 0xc00; 458 } 459 460 /* RTL8812AU-specific */ 461 rtwn_r12a_fix_spur(sc, c); 462 463 for (i = 0; i < sc->nrxchains; i++) 464 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val); 465 466 /* Set Tx power for this new channel. */ 467 r12a_set_txpower(sc, c); 468 } 469 470 void 471 r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates) 472 { 473 struct r12a_softc *rs = sc->sc_priv; 474 475 /* Enable CCK / OFDM. */ 476 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, 477 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); 478 479 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01); 480 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000); 481 482 /* Select AGC table. */ 483 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0); 484 485 switch (rs->rfe_type) { 486 case 0: 487 case 1: 488 case 2: 489 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 490 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 491 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 492 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 493 break; 494 case 3: 495 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770); 496 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770); 497 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 498 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 499 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 500 break; 501 case 4: 502 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777); 503 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 504 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000); 505 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000); 506 break; 507 case 5: 508 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77); 509 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777); 510 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0); 511 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 512 break; 513 default: 514 break; 515 } 516 517 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10); 518 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000); 519 520 /* Write basic rates. */ 521 rtwn_set_basicrates(sc, basicrates); 522 523 rtwn_write_1(sc, R12A_CCK_CHECK, 0); 524 } 525 526 void 527 r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates) 528 { 529 struct r12a_softc *rs = sc->sc_priv; 530 int ntries; 531 532 rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ); 533 534 for (ntries = 0; ntries < 100; ntries++) { 535 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30) 536 break; 537 538 rtwn_delay(sc, 25); 539 } 540 if (ntries == 100) { 541 device_printf(sc->sc_dev, 542 "%s: TXPKT_EMPTY check failed (%04X)\n", 543 __func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY)); 544 } 545 546 /* Enable OFDM. */ 547 rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK, 548 R12A_OFDMCCK_EN_OFDM); 549 550 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02); 551 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000); 552 553 /* Select AGC table. */ 554 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01); 555 556 switch (rs->rfe_type) { 557 case 0: 558 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 559 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 560 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 561 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 562 break; 563 case 1: 564 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717); 565 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717); 566 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0); 567 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0); 568 break; 569 case 2: 570 case 4: 571 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777); 572 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 573 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 574 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 575 break; 576 case 3: 577 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717); 578 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717); 579 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000); 580 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 581 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01); 582 break; 583 case 5: 584 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33); 585 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777); 586 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01); 587 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000); 588 break; 589 default: 590 break; 591 } 592 593 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0); 594 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000); 595 596 /* Write basic rates. */ 597 rtwn_set_basicrates(sc, basicrates); 598 } 599