1*551b7c5eSAhmad Khalifa /* 2*551b7c5eSAhmad Khalifa * Copyright (c) 2026 Ahmad Khalifa <vexeduxr@FreeBSD.org> 3*551b7c5eSAhmad Khalifa * 4*551b7c5eSAhmad Khalifa * SPDX-License-Identifier: BSD-2-Clause 5*551b7c5eSAhmad Khalifa */ 6*551b7c5eSAhmad Khalifa 7*551b7c5eSAhmad Khalifa #ifndef R23B_REG_H 8*551b7c5eSAhmad Khalifa #define R23B_REG_H 9*551b7c5eSAhmad Khalifa 10*551b7c5eSAhmad Khalifa #define R23B_BTCOEX_TABLE(i) (0x6c0 + (i) * 4) 11*551b7c5eSAhmad Khalifa #define R23B_GNT_BT 0x764 12*551b7c5eSAhmad Khalifa #define R23B_ANT_SEL 0x948 13*551b7c5eSAhmad Khalifa 14*551b7c5eSAhmad Khalifa /* Bits for R92C_EFUSE_TEST. */ 15*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_SEL_M 0x300 16*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_SEL_S 8 17*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_SEL_WIFI 0 18*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_SEL_BT0 1 19*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_SEL_BT1 2 20*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_SEL_BT2 3 21*551b7c5eSAhmad Khalifa #define R23B_EFUSE_TEST_PGMEN 0x800 22*551b7c5eSAhmad Khalifa 23*551b7c5eSAhmad Khalifa /* Bits for R92C_PWR_DATA. */ 24*551b7c5eSAhmad Khalifa #define R23B_PWR_DATA_RFE_CTRL_EN 0x800 25*551b7c5eSAhmad Khalifa 26*551b7c5eSAhmad Khalifa /* Bits for R92C_LEDCFG0. */ 27*551b7c5eSAhmad Khalifa #define R23B_LEDCFG0_DPDT_SEL_EN 0x800000 28*551b7c5eSAhmad Khalifa 29*551b7c5eSAhmad Khalifa /* Bits for R92C_LEDCFG2. */ 30*551b7c5eSAhmad Khalifa #define R23B_LEDCFG2_LED_SW_CTRL 0x20 31*551b7c5eSAhmad Khalifa #define R23B_LEDCFG2_LED_DISABLE 0x04 32*551b7c5eSAhmad Khalifa #define R23B_LEDCFG2_LED_M 0x7f 33*551b7c5eSAhmad Khalifa 34*551b7c5eSAhmad Khalifa /* Bits for R88E_BB_PAD_CTRL. */ 35*551b7c5eSAhmad Khalifa #define R23B_BB_PAD_CTRL_DPDT_SEL_DATA 0x1 36*551b7c5eSAhmad Khalifa 37*551b7c5eSAhmad Khalifa /* Bits for R92C_RXDMA_AGG_PG_TH. */ 38*551b7c5eSAhmad Khalifa #define R23B_RXDMA_AGG_PG_TH_EN 0x80000000 39*551b7c5eSAhmad Khalifa #define R23B_RXDMA_AGG_PG_TH_SIZE_M 0xf 40*551b7c5eSAhmad Khalifa #define R23B_RXDMA_AGG_PG_TH_SIZE_S 0 41*551b7c5eSAhmad Khalifa #define R23B_RXDMA_AGG_PG_TH_TIME_M 0xff00 42*551b7c5eSAhmad Khalifa #define R23B_RXDMA_AGG_PG_TH_TIME_S 8 43*551b7c5eSAhmad Khalifa 44*551b7c5eSAhmad Khalifa /* Bits for R92C_FWHW_TXQ_CTRL. */ 45*551b7c5eSAhmad Khalifa #define R23B_FWHW_TXQ_CTRL_ACK_MGNT 0x1000 46*551b7c5eSAhmad Khalifa 47*551b7c5eSAhmad Khalifa /* Bits for R92C_WMAC_TRXPTCL_CTL. */ 48*551b7c5eSAhmad Khalifa #define R23B_WMAC_TRXPTCL_CTL_HT40 0x80 49*551b7c5eSAhmad Khalifa #define R23B_WMAC_TRXPTCL_CTL_VHT80 0x100 50*551b7c5eSAhmad Khalifa 51*551b7c5eSAhmad Khalifa /* Bits for R23B_ANT_SEL. */ 52*551b7c5eSAhmad Khalifa #define R23B_ANT_SEL_S0 0x000 53*551b7c5eSAhmad Khalifa #define R23B_ANT_SEL_S1 0x280 54*551b7c5eSAhmad Khalifa 55*551b7c5eSAhmad Khalifa /* 56*551b7c5eSAhmad Khalifa * RF (6052) registers. 57*551b7c5eSAhmad Khalifa */ 58*551b7c5eSAhmad Khalifa #define R23B_RF_S0S1 0xb0 59*551b7c5eSAhmad Khalifa 60*551b7c5eSAhmad Khalifa /* Bits for R92C_RF_CHNLBW. */ 61*551b7c5eSAhmad Khalifa #define R23B_RF_CHNLBW_BW40 0x00400 62*551b7c5eSAhmad Khalifa 63*551b7c5eSAhmad Khalifa #endif 64