1 /*- 2 * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 32 #include <sys/param.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 46 #include <net/if.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/rtwn/if_rtwnreg.h> 54 #include <dev/rtwn/if_rtwnvar.h> 55 56 #include <dev/rtwn/if_rtwn_debug.h> 57 58 #include <dev/rtwn/rtl8192c/r92c.h> 59 60 #include <dev/rtwn/rtl8192e/r92e.h> 61 #include <dev/rtwn/rtl8192e/r92e_reg.h> 62 #include <dev/rtwn/rtl8192e/r92e_priv.h> 63 #include <dev/rtwn/rtl8192e/r92e_var.h> 64 65 int 66 r92e_llt_init(struct rtwn_softc *sc) 67 { 68 int ntries, error; 69 70 error = rtwn_setbits_4(sc, R92C_AUTO_LLT, 0, R92C_AUTO_LLT_INIT); 71 if (error != 0) 72 return (error); 73 for (ntries = 0; ntries < 1000; ntries++) { 74 if (!(rtwn_read_4(sc, R92C_AUTO_LLT) & R92C_AUTO_LLT_INIT)) 75 return (0); 76 rtwn_delay(sc, 1); 77 } 78 return (ETIMEDOUT); 79 } 80 81 static void 82 r92e_crystalcap_write(struct rtwn_softc *sc) 83 { 84 struct r92e_softc *rs = sc->sc_priv; 85 uint32_t reg; 86 uint8_t val; 87 88 val = rs->crystalcap & 0x3f; 89 reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL); 90 rtwn_bb_write(sc, R92E_AFE_XTAL_CTRL, 91 RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6)); 92 rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 93 } 94 95 void 96 r92e_init_bb(struct rtwn_softc *sc) 97 { 98 int i, j; 99 100 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0, 101 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD); 102 103 /* Enable BB and RF. */ 104 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0, 105 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 106 R92C_SYS_FUNC_EN_DIO_RF); 107 108 /* PathA RF Power On. */ 109 rtwn_write_1(sc, R92C_RF_CTRL, 110 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 111 112 /* Write BB initialization values. */ 113 for (i = 0; i < sc->bb_size; i++) { 114 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 115 116 while (!rtwn_check_condition(sc, bb_prog->cond)) { 117 KASSERT(bb_prog->next != NULL, 118 ("%s: wrong condition value (i %d)\n", 119 __func__, i)); 120 bb_prog = bb_prog->next; 121 } 122 123 for (j = 0; j < bb_prog->count; j++) { 124 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 125 "BB: reg 0x%03x, val 0x%08x\n", 126 bb_prog->reg[j], bb_prog->val[j]); 127 128 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 129 rtwn_delay(sc, 1); 130 } 131 } 132 133 /* Write AGC values. */ 134 for (i = 0; i < sc->agc_size; i++) { 135 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 136 137 while (!rtwn_check_condition(sc, agc_prog->cond)) { 138 KASSERT(agc_prog->next != NULL, 139 ("%s: wrong condition value (2) (i %d)\n", 140 __func__, i)); 141 agc_prog = agc_prog->next; 142 } 143 144 for (j = 0; j < agc_prog->count; j++) { 145 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 146 "AGC: val 0x%08x\n", agc_prog->val[j]); 147 148 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 149 agc_prog->val[j]); 150 rtwn_delay(sc, 1); 151 } 152 } 153 154 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 155 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 156 157 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 158 rtwn_delay(sc, 1); 159 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 160 rtwn_delay(sc, 1); 161 162 r92e_crystalcap_write(sc); 163 } 164 165 void 166 r92e_init_rf(struct rtwn_softc *sc) 167 { 168 struct r92e_softc *rs = sc->sc_priv; 169 uint32_t reg, type; 170 int i, chain, idx, off; 171 172 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 173 /* Save RF_ENV control type. */ 174 idx = chain / 2; 175 off = (chain % 2) * 16; 176 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 177 type = (reg >> off) & 0x10; 178 179 /* Set RF_ENV enable. */ 180 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 181 0, 0x100000); 182 rtwn_delay(sc, 1); 183 /* Set RF_ENV output high. */ 184 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 185 0, 0x10); 186 rtwn_delay(sc, 1); 187 /* Set address and data lengths of RF registers. */ 188 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 189 R92C_HSSI_PARAM2_ADDR_LENGTH, 0); 190 rtwn_delay(sc, 1); 191 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 192 R92C_HSSI_PARAM2_DATA_LENGTH, 0); 193 rtwn_delay(sc, 1); 194 195 /* Write RF initialization values for this chain. */ 196 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 197 198 /* Restore RF_ENV control type. */ 199 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 200 reg &= ~(0x10 << off) | (type << off); 201 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 202 203 /* Cache RF register CHNLBW. */ 204 rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, R92C_RF_CHNLBW); 205 } 206 207 /* Turn CCK and OFDM blocks on. */ 208 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN); 209 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN); 210 } 211 212 static void 213 r92e_adj_crystal(struct rtwn_softc *sc) 214 { 215 216 rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, R92C_AFE_PLL_CTRL_FREF_SEL, 0); 217 rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00000380, 0); 218 rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, 0x40, 0); 219 rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00200000, 0); 220 } 221 222 int 223 r92e_power_on(struct rtwn_softc *sc) 224 { 225 #define RTWN_CHK(res) do { \ 226 if (res != 0) \ 227 return (EIO); \ 228 } while(0) 229 int ntries; 230 231 if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN) 232 RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0xc3)); 233 else { 234 RTWN_CHK(rtwn_setbits_4(sc, R92E_LDOV12_CTRL, 0x00100000, 235 0x00500000)); 236 RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0x83)); 237 } 238 239 r92e_adj_crystal(sc); 240 241 /* Enable WL suspend. */ 242 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 243 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1)); 244 245 /* Disable HWPDN, SW LPS and WL suspend. */ 246 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 247 R92C_APS_FSMCO_APFM_RSM | R92C_APS_FSMCO_AFSM_HSUS | 248 R92C_APS_FSMCO_AFSM_PCIE | R92C_APS_FSMCO_APDM_HPDN, 0, 1)); 249 250 /* Wait for power ready bit. */ 251 for (ntries = 0; ntries < 5000; ntries++) { 252 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 253 break; 254 rtwn_delay(sc, 10); 255 } 256 if (ntries == 5000) { 257 device_printf(sc->sc_dev, 258 "timeout waiting for chip power up\n"); 259 return (ETIMEDOUT); 260 } 261 262 /* Release WLON reset. */ 263 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 264 R92C_APS_FSMCO_RDY_MACON, 2)); 265 266 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 267 R92C_APS_FSMCO_APFM_ONMAC, 1)); 268 for (ntries = 0; ntries < 5000; ntries++) { 269 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 270 R92C_APS_FSMCO_APFM_ONMAC)) 271 break; 272 rtwn_delay(sc, 10); 273 } 274 if (ntries == 5000) 275 return (ETIMEDOUT); 276 277 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 278 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0)); 279 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0, 280 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN | 281 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN | 282 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN | 283 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) | 284 R92C_CR_CALTMR_EN)); 285 286 return (0); 287 } 288 289 void 290 r92e_power_off(struct rtwn_softc *sc) 291 { 292 int error, ntries; 293 294 /* Stop Rx. */ 295 error = rtwn_write_1(sc, R92C_CR, 0); 296 if (error == ENXIO) /* hardware gone */ 297 return; 298 299 /* Move card to Low Power state. */ 300 /* Block all Tx queues. */ 301 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 302 303 for (ntries = 0; ntries < 5000; ntries++) { 304 /* Should be zero if no packet is transmitting. */ 305 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 306 break; 307 308 rtwn_delay(sc, 10); 309 } 310 if (ntries == 5000) { 311 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 312 __func__); 313 return; 314 } 315 316 /* CCK and OFDM are disabled, and clock are gated. */ 317 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0); 318 319 rtwn_delay(sc, 1); 320 321 /* Reset whole BB. */ 322 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 323 324 /* Reset MAC TRX. */ 325 rtwn_write_1(sc, R92C_CR, 326 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN); 327 328 /* Check if removed later. */ 329 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1); 330 331 /* Respond TxOK to scheduler */ 332 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK); 333 334 /* Reset MCU. */ 335 rtwn_write_1(sc, R92C_MCUFWDL, 0); 336 337 #ifndef RTWN_WITHOUT_UCODE 338 /* Reset MCU IO wrapper. */ 339 rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0); 340 341 rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 342 R92C_SYS_FUNC_EN_CPUEN, 0, 1); 343 344 /* Enable MCU IO wrapper. */ 345 rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01); 346 #endif 347 348 /* Move card to Disabled state. */ 349 /* Turn off RF. */ 350 rtwn_write_1(sc, R92C_RF_CTRL, 0); 351 352 /* Switch DPDT_SEL_P output. */ 353 rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0); 354 355 /* Turn off MAC by HW state machine */ 356 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF, 357 1); 358 359 for (ntries = 0; ntries < 5000; ntries++) { 360 /* Wait until it will be disabled. */ 361 if ((rtwn_read_2(sc, R92C_APS_FSMCO) & 362 R92C_APS_FSMCO_APFM_OFF) == 0) 363 break; 364 365 rtwn_delay(sc, 10); 366 } 367 if (ntries == 5000) { 368 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 369 __func__); 370 return; 371 } 372 373 /* SOP option to disable BG/MB. */ 374 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff, 375 R92C_APS_FSMCO_SOP_RCK, 3); 376 377 /* Unlock small LDO Register. */ 378 rtwn_setbits_1(sc, 0xcc, 0, 0x4); 379 380 /* Disable small LDO. */ 381 rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0); 382 383 /* Enable WL suspend. */ 384 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE, 385 R92C_APS_FSMCO_AFSM_HSUS, 1); 386 387 /* Enable SW LPS. */ 388 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, 389 R92C_APS_FSMCO_APFM_RSM, 1); 390 } 391