1 /*- 2 * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/queue.h> 39 #include <sys/taskqueue.h> 40 #include <sys/bus.h> 41 #include <sys/endian.h> 42 #include <sys/linker.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 54 #include <dev/rtwn/if_rtwn_debug.h> 55 #include <dev/rtwn/if_rtwn_ridx.h> 56 #include <dev/rtwn/if_rtwn_rx.h> 57 58 #include <dev/rtwn/rtl8192c/r92c.h> 59 60 #include <dev/rtwn/rtl8192e/r92e.h> 61 #include <dev/rtwn/rtl8192e/r92e_reg.h> 62 #include <dev/rtwn/rtl8192e/r92e_var.h> 63 64 static int 65 r92e_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 66 { 67 uint8_t chan; 68 int group; 69 70 chan = rtwn_chan2centieee(c); 71 if (IEEE80211_IS_CHAN_2GHZ(c)) { 72 if (chan <= 2) group = 0; 73 else if (chan <= 5) group = 1; 74 else if (chan <= 8) group = 2; 75 else if (chan <= 11) group = 3; 76 else if (chan <= 14) group = 4; 77 else { 78 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 79 return (-1); 80 } 81 } else { 82 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 83 return (-1); 84 } 85 86 return (group); 87 } 88 89 static void 90 r92e_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c, 91 uint8_t power[RTWN_RIDX_COUNT]) 92 { 93 const struct ieee80211com *ic = &sc->sc_ic; 94 struct r92e_softc *rs = sc->sc_priv; 95 int i, ridx, group, max_mcs; 96 97 /* Determine channel group. */ 98 group = r92e_get_power_group(sc, c); 99 if (group == -1) { /* shouldn't happen */ 100 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 101 return; 102 } 103 104 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 105 106 /* XXX regulatory */ 107 108 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 109 power[ridx] = rs->cck_tx_pwr[chain][group]; 110 if (power[ridx] > ic->ic_txpowlimit) 111 power[ridx] = ic->ic_txpowlimit; 112 } 113 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) { 114 power[ridx] = rs->ht40_tx_pwr_2g[chain][group]; 115 if (power[ridx] > ic->ic_txpowlimit) 116 power[ridx] = ic->ic_txpowlimit; 117 } 118 119 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 120 /* Ensure we don't underflow if the power delta is -ve */ 121 int8_t pwr; 122 123 pwr = power[ridx] + rs->ofdm_tx_pwr_diff_2g[chain][0]; 124 if (pwr < 0) 125 pwr = 0; 126 127 power[ridx] = pwr; 128 } 129 130 for (i = 0; i < sc->ntxchains; i++) { 131 uint8_t min_mcs; 132 int8_t pwr_diff, pwr; 133 134 if (IEEE80211_IS_CHAN_HT40(c)) 135 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 136 else 137 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i]; 138 139 min_mcs = RTWN_RIDX_HT_MCS(i * 8); 140 for (ridx = min_mcs; ridx <= max_mcs; ridx++) { 141 /* Ensure we don't underflow */ 142 pwr = power[ridx] + pwr_diff; 143 if (pwr < 0) 144 pwr = 0; 145 power[ridx] = pwr; 146 } 147 } 148 149 /* Apply max limit. */ 150 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 151 if (power[ridx] > R92C_MAX_TX_PWR) 152 power[ridx] = R92C_MAX_TX_PWR; 153 } 154 } 155 156 static void 157 r92e_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 158 { 159 uint8_t power[RTWN_RIDX_COUNT]; 160 int i; 161 162 for (i = 0; i < sc->ntxchains; i++) { 163 memset(power, 0, sizeof(power)); 164 /* Compute per-rate Tx power values. */ 165 r92e_get_txpower(sc, i, c, power); 166 /* Optionally print out the power table */ 167 r92c_dump_txpower(sc, i, power); 168 /* Write per-rate Tx power values to hardware. */ 169 r92c_write_txpower(sc, i, power); 170 } 171 } 172 173 int 174 r92e_set_tx_power(struct rtwn_softc *sc, struct ieee80211vap *vap) 175 { 176 177 if (vap->iv_bss == NULL) 178 return (EINVAL); 179 if (vap->iv_bss->ni_chan == IEEE80211_CHAN_ANYC) 180 return (EINVAL); 181 182 r92e_set_txpower(sc, vap->iv_bss->ni_chan); 183 return (0); 184 } 185 186 static void 187 r92e_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo) 188 { 189 int i; 190 191 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80); 192 rtwn_write_1(sc, R12A_DATA_SEC, 193 prichlo ? R12A_DATA_SEC_PRIM_DOWN_20 : R12A_DATA_SEC_PRIM_UP_20); 194 195 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ); 196 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ); 197 198 /* Select 40MHz bandwidth. */ 199 for (i = 0; i < sc->nrxchains; i++) 200 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 201 R88E_RF_CHNLBW_BW20, 0x400); 202 203 /* Set CCK side band. */ 204 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 205 R92C_CCK0_SYSTEM_CCK_SIDEBAND, (prichlo ? 0 : 1) << 4); 206 207 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10); 208 209 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 210 R92C_FPGA0_ANAPARAM2_CBW20, 0); 211 212 rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26); 213 } 214 215 static void 216 r92e_set_bw20(struct rtwn_softc *sc, uint8_t chan) 217 { 218 int i; 219 220 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0); 221 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT); 222 223 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); 224 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); 225 226 /* Select 20MHz bandwidth. */ 227 for (i = 0; i < sc->nrxchains; i++) 228 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 229 R88E_RF_CHNLBW_BW20, 0xc00); 230 231 rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0); 232 } 233 234 void 235 r92e_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 236 { 237 struct r92e_softc *rs = sc->sc_priv; 238 u_int chan; 239 int i; 240 241 chan = rtwn_chan2centieee(c); 242 243 for (i = 0; i < sc->nrxchains; i++) { 244 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 245 RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan)); 246 } 247 248 if (IEEE80211_IS_CHAN_HT40(c)) 249 r92e_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c)); 250 else 251 r92e_set_bw20(sc, chan); 252 253 /* Set Tx power for this new channel. */ 254 r92e_set_txpower(sc, c); 255 } 256