1 /*- 2 * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 32 #include <sys/param.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/queue.h> 41 #include <sys/taskqueue.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/linker.h> 45 46 #include <net/if.h> 47 #include <net/ethernet.h> 48 #include <net/if_media.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/rtwn/if_rtwnreg.h> 54 #include <dev/rtwn/if_rtwnvar.h> 55 56 #include <dev/rtwn/if_rtwn_debug.h> 57 #include <dev/rtwn/if_rtwn_ridx.h> 58 #include <dev/rtwn/if_rtwn_rx.h> 59 60 #include <dev/rtwn/rtl8192e/r92e.h> 61 #include <dev/rtwn/rtl8192e/r92e_reg.h> 62 #include <dev/rtwn/rtl8192e/r92e_var.h> 63 64 static int 65 r92e_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 66 { 67 uint8_t chan; 68 int group; 69 70 chan = rtwn_chan2centieee(c); 71 if (IEEE80211_IS_CHAN_2GHZ(c)) { 72 if (chan <= 2) group = 0; 73 else if (chan <= 5) group = 1; 74 else if (chan <= 8) group = 2; 75 else if (chan <= 11) group = 3; 76 else if (chan <= 14) group = 4; 77 else { 78 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 79 return (-1); 80 } 81 } else { 82 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 83 return (-1); 84 } 85 86 return (group); 87 } 88 89 static void 90 r92e_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c, 91 uint8_t power[RTWN_RIDX_COUNT]) 92 { 93 struct r92e_softc *rs = sc->sc_priv; 94 int i, ridx, group, max_mcs; 95 96 /* Determine channel group. */ 97 group = r92e_get_power_group(sc, c); 98 if (group == -1) { /* shouldn't happen */ 99 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 100 return; 101 } 102 103 max_mcs = RTWN_RIDX_MCS(sc->ntxchains * 8 - 1); 104 105 /* XXX regulatory */ 106 /* XXX net80211 regulatory */ 107 108 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 109 power[ridx] = rs->cck_tx_pwr[chain][group]; 110 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) 111 power[ridx] = rs->ht40_tx_pwr_2g[chain][group]; 112 113 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 114 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0]; 115 116 for (i = 0; i < sc->ntxchains; i++) { 117 uint8_t min_mcs; 118 uint8_t pwr_diff; 119 120 if (IEEE80211_IS_CHAN_HT40(c)) 121 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i]; 122 else 123 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i]; 124 125 min_mcs = RTWN_RIDX_MCS(i * 8); 126 for (ridx = min_mcs; ridx <= max_mcs; ridx++) 127 power[ridx] += pwr_diff; 128 129 } 130 131 /* Apply max limit. */ 132 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 133 if (power[ridx] > R92C_MAX_TX_PWR) 134 power[ridx] = R92C_MAX_TX_PWR; 135 } 136 137 #ifdef RTWN_DEBUG 138 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 139 /* Dump per-rate Tx power values. */ 140 printf("Tx power for chain %d:\n", chain); 141 for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++) 142 printf("Rate %d = %u\n", ridx, power[ridx]); 143 } 144 #endif 145 } 146 147 148 static void 149 r92e_write_txpower(struct rtwn_softc *sc, int chain, 150 uint8_t power[RTWN_RIDX_COUNT]) 151 { 152 uint32_t reg; 153 154 /* Write per-CCK rate Tx power. */ 155 if (chain == 0) { 156 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 157 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]); 158 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 159 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 160 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]); 161 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]); 162 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]); 163 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 164 } else { 165 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 166 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]); 167 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]); 168 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]); 169 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 170 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 171 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]); 172 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 173 } 174 /* Write per-OFDM rate Tx power. */ 175 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 176 SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) | 177 SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) | 178 SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) | 179 SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18])); 180 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 181 SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) | 182 SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) | 183 SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) | 184 SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54])); 185 /* Write per-MCS Tx power. */ 186 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 187 SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_MCS(0)]) | 188 SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_MCS(1)]) | 189 SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_MCS(2)]) | 190 SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_MCS(3)])); 191 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 192 SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_MCS(4)]) | 193 SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_MCS(5)]) | 194 SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_MCS(6)]) | 195 SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_MCS(7)])); 196 if (sc->ntxchains >= 2) { 197 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 198 SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_MCS(8)]) | 199 SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_MCS(9)]) | 200 SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_MCS(10)]) | 201 SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_MCS(11)])); 202 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 203 SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_MCS(12)]) | 204 SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_MCS(13)]) | 205 SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_MCS(14)]) | 206 SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_MCS(15)])); 207 } 208 } 209 210 static void 211 r92e_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 212 { 213 uint8_t power[RTWN_RIDX_COUNT]; 214 int i; 215 216 for (i = 0; i < sc->ntxchains; i++) { 217 memset(power, 0, sizeof(power)); 218 /* Compute per-rate Tx power values. */ 219 r92e_get_txpower(sc, i, c, power); 220 /* Write per-rate Tx power values to hardware. */ 221 r92e_write_txpower(sc, i, power); 222 } 223 } 224 225 static void 226 r92e_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo) 227 { 228 int i; 229 230 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80); 231 rtwn_write_1(sc, R12A_DATA_SEC, 232 prichlo ? R12A_DATA_SEC_PRIM_DOWN_20 : R12A_DATA_SEC_PRIM_UP_20); 233 234 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ); 235 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ); 236 237 /* Select 40MHz bandwidth. */ 238 for (i = 0; i < sc->nrxchains; i++) 239 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 240 R88E_RF_CHNLBW_BW20, 0x400); 241 242 /* Set CCK side band. */ 243 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 244 R92C_CCK0_SYSTEM_CCK_SIDEBAND, (prichlo ? 0 : 1) << 4); 245 246 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10); 247 248 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 249 R92C_FPGA0_ANAPARAM2_CBW20, 0); 250 251 rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26); 252 } 253 254 static void 255 r92e_set_bw20(struct rtwn_softc *sc, uint8_t chan) 256 { 257 int i; 258 259 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0); 260 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT); 261 262 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); 263 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); 264 265 /* Select 20MHz bandwidth. */ 266 for (i = 0; i < sc->nrxchains; i++) 267 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 268 R88E_RF_CHNLBW_BW20, 0xc00); 269 270 rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0); 271 } 272 273 void 274 r92e_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 275 { 276 struct r92e_softc *rs = sc->sc_priv; 277 u_int chan; 278 int i; 279 280 chan = rtwn_chan2centieee(c); 281 282 for (i = 0; i < sc->nrxchains; i++) { 283 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 284 RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan)); 285 } 286 287 if (IEEE80211_IS_CHAN_HT40(c)) 288 r92e_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c)); 289 else 290 r92e_set_bw20(sc, chan); 291 292 /* Set Tx power for this new channel. */ 293 r92e_set_txpower(sc, c); 294 } 295