1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 4 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 19 * $FreeBSD$ 20 */ 21 22 #ifndef R92C_REG_H 23 #define R92C_REG_H 24 25 /* 26 * MAC registers. 27 */ 28 /* System Configuration. */ 29 #define R92C_SYS_ISO_CTRL 0x000 30 #define R92C_SYS_FUNC_EN 0x002 31 #define R92C_APS_FSMCO 0x004 32 #define R92C_SYS_CLKR 0x008 33 #define R92C_AFE_MISC 0x010 34 #define R92C_SPS0_CTRL 0x011 35 #define R92C_SPS_OCP_CFG 0x018 36 #define R92C_RSV_CTRL 0x01c 37 #define R92C_RF_CTRL 0x01f 38 #define R92C_LDOA15_CTRL 0x020 39 #define R92C_LDOV12D_CTRL 0x021 40 #define R92C_LDOHCI12_CTRL 0x022 41 #define R92C_LPLDO_CTRL 0x023 42 #define R92C_AFE_XTAL_CTRL 0x024 43 #define R92C_AFE_PLL_CTRL 0x028 44 #define R92C_APE_PLL_CTRL_EXT 0x02c 45 #define R92C_MAC_PHY_CTRL R92C_APE_PLL_CTRL_EXT 46 #define R92C_EFUSE_CTRL 0x030 47 #define R92C_EFUSE_TEST 0x034 48 #define R92C_PWR_DATA 0x038 49 #define R92C_CAL_TIMER 0x03c 50 #define R92C_ACLK_MON 0x03e 51 #define R92C_GPIO_MUXCFG 0x040 52 #define R92C_GPIO_IO_SEL 0x042 53 #define R92C_MAC_PINMUX_CFG 0x043 54 #define R92C_GPIO_PIN_CTRL 0x044 55 #define R92C_GPIO_IN 0x044 56 #define R92C_GPIO_OUT 0x045 57 #define R92C_GPIO_IOSEL 0x046 58 #define R92C_GPIO_MOD 0x047 59 #define R92C_GPIO_INTM 0x048 60 #define R92C_LEDCFG0 0x04c 61 #define R92C_LEDCFG1 0x04d 62 #define R92C_LEDCFG2 0x04e 63 #define R92C_LEDCFG3 0x04f 64 #define R92C_FSIMR 0x050 65 #define R92C_FSISR 0x054 66 #define R92C_HSIMR 0x058 67 #define R92C_HSISR 0x05c 68 #define R92C_MULTI_FUNC_CTRL 0x068 69 #define R92C_AFE_XTAL_CTRL_EXT 0x078 70 #define R92C_LDO_SWR_CTRL 0x07c 71 #define R92C_MCUFWDL 0x080 72 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 73 #define R92C_EFUSE_ACCESS 0x0cf 74 #define R92C_BIST_SCAN 0x0d0 75 #define R92C_BIST_RPT 0x0d4 76 #define R92C_BIST_ROM_RPT 0x0d8 77 #define R92C_HPON_FSM 0x0ec 78 #define R92C_SYS_CFG 0x0f0 79 #define R92C_TYPE_ID 0x0fc 80 /* MAC General Configuration. */ 81 #define R92C_CR 0x100 82 #define R92C_MSR 0x102 83 #define R92C_PBP 0x104 84 #define R92C_TRXDMA_CTRL 0x10c 85 #define R92C_TRXFF_BNDY 0x114 86 #define R92C_TRXFF_STATUS 0x118 87 #define R92C_RXFF_PTR 0x11c 88 #define R92C_HIMR 0x120 89 #define R92C_HISR 0x124 90 #define R92C_HIMRE 0x128 91 #define R92C_HISRE 0x12c 92 #define R92C_CPWM 0x12f 93 #define R92C_FWIMR 0x130 94 #define R92C_FWISR 0x134 95 #define R92C_PKTBUF_DBG_CTRL 0x140 96 #define R92C_PKTBUF_DBG_DATA_L 0x144 97 #define R92C_PKTBUF_DBG_DATA_H 0x148 98 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 99 #define R92C_TCUNIT_BASE 0x164 100 #define R92C_MBIST_START 0x174 101 #define R92C_MBIST_DONE 0x178 102 #define R92C_MBIST_FAIL 0x17c 103 #define R92C_C2H_EVT_MSG 0x1a0 104 #define R92C_C2H_EVT_CLEAR 0x1af 105 #define R92C_C2H_EVT_MSG_TEST 0x1b8 106 #define R92C_MCUTST_1 0x1c0 107 #define R92C_FMETHR 0x1c8 108 #define R92C_HMETFR 0x1cc 109 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 110 #define R92C_LLT_INIT 0x1e0 111 #define R92C_BB_ACCESS_CTRL 0x1e8 112 #define R92C_BB_ACCESS_DATA 0x1ec 113 /* Tx DMA Configuration. */ 114 #define R92C_RQPN 0x200 115 #define R92C_FIFOPAGE 0x204 116 #define R92C_TDECTRL 0x208 117 #define R92C_TXDMA_OFFSET_CHK 0x20c 118 #define R92C_TXDMA_STATUS 0x210 119 #define R92C_RQPN_NPQ 0x214 120 #define R92C_AUTO_LLT 0x224 121 /* Rx DMA Configuration. */ 122 #define R92C_RXDMA_AGG_PG_TH 0x280 123 #define R92C_RXPKT_NUM 0x284 124 #define R92C_RXDMA_STATUS 0x288 125 /* Protocol Configuration. */ 126 #define R92C_VOQ_INFORMATION 0x400 127 #define R92C_VIQ_INFORMATION 0x404 128 #define R92C_BEQ_INFORMATION 0x408 129 #define R92C_BKQ_INFORMATION 0x40c 130 #define R92C_MGQ_INFORMATION 0x410 131 #define R92C_HGQ_INFORMATION 0x414 132 #define R92C_BCNQ_INFORMATION 0x418 133 #define R92C_CPU_MGQ_INFORMATION 0x41c 134 #define R92C_FWHW_TXQ_CTRL 0x420 135 #define R92C_HWSEQ_CTRL 0x423 136 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 137 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 138 #define R92C_SPEC_SIFS 0x428 139 #define R92C_RL 0x42a 140 #define R92C_DARFRC 0x430 141 #define R92C_RARFRC 0x438 142 #define R92C_RRSR 0x440 143 #define R92C_ARFR(i) (0x444 + (i) * 4) 144 #define R92C_AGGLEN_LMT 0x458 145 #define R92C_AMPDU_MIN_SPACE 0x45c 146 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 147 #define R92C_FAST_EDCA_CTRL 0x460 148 #define R92C_RD_RESP_PKT_TH 0x463 149 #define R92C_INIRTS_RATE_SEL 0x480 150 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 151 #define R92C_POWER_STATUS 0x4a4 152 #define R92C_QUEUE_CTRL 0x4c6 153 #define R92C_MAX_AGGR_NUM 0x4ca 154 #define R92C_BAR_MODE_CTRL 0x4cc 155 /* EDCA Configuration. */ 156 #define R92C_EDCA_VO_PARAM 0x500 157 #define R92C_EDCA_VI_PARAM 0x504 158 #define R92C_EDCA_BE_PARAM 0x508 159 #define R92C_EDCA_BK_PARAM 0x50c 160 #define R92C_BCNTCFG 0x510 161 #define R92C_PIFS 0x512 162 #define R92C_RDG_PIFS 0x513 163 #define R92C_SIFS_CCK 0x514 164 #define R92C_SIFS_OFDM 0x516 165 #define R92C_AGGR_BREAK_TIME 0x51a 166 #define R92C_SLOT 0x51b 167 #define R92C_TX_PTCL_CTRL 0x520 168 #define R92C_TXPAUSE 0x522 169 #define R92C_DIS_TXREQ_CLR 0x523 170 #define R92C_RD_CTRL 0x524 171 #define R92C_TBTT_PROHIBIT 0x540 172 #define R92C_RD_NAV_NXT 0x544 173 #define R92C_NAV_PROT_LEN 0x546 174 #define R92C_BCN_CTRL(id) ((id) + 0x550) 175 /* WARNING: R92C_USTIME_TSF == 0x55c, not 0x551 */ 176 #define R92C_MBID_NUM 0x552 177 #define R92C_DUAL_TSF_RST 0x553 178 #define R92C_BCN_INTERVAL(id) (0x554 + (id) * 2) 179 #define R92C_DRVERLYINT 0x558 180 #define R92C_BCNDMATIM 0x559 181 #define R92C_ATIMWND 0x55a 182 #define R92C_USTIME_TSF 0x55c 183 #define R92C_BCN_MAX_ERR 0x55d 184 #define R92C_RXTSF_OFFSET_CCK 0x55e 185 #define R92C_RXTSF_OFFSET_OFDM 0x55f 186 #define R92C_TSFTR(i) (0x560 + (i) * 8) 187 #define R92C_PSTIMER 0x580 188 #define R92C_TIMER0 0x584 189 #define R92C_TIMER1 0x588 190 #define R92C_ACMHWCTRL 0x5c0 191 #define R92C_ACMRSTCTRL 0x5c1 192 #define R92C_ACMAVG 0x5c2 193 #define R92C_VO_ADMTIME 0x5c4 194 #define R92C_VI_ADMTIME 0x5c6 195 #define R92C_BE_ADMTIME 0x5c8 196 #define R92C_EDCA_RANDOM_GEN 0x5cc 197 #define R92C_SCH_TXCMD 0x5d0 198 /* WMAC Configuration. */ 199 #define R92C_APSD_CTRL 0x600 200 #define R92C_BWOPMODE 0x603 201 #define R92C_TCR 0x604 202 #define R92C_RCR 0x608 203 #define R92C_RX_PKT_LIMIT 0x60c 204 #define R92C_RX_DRVINFO_SZ 0x60f 205 #define R92C_MACID0 0x610 206 #define R92C_BSSID0 0x618 207 #define R92C_MAR 0x620 208 #define R92C_USTIME_EDCA 0x638 209 #define R92C_MAC_SPEC_SIFS 0x63a 210 #define R92C_R2T_SIFS 0x63c 211 #define R92C_T2T_SIFS 0x63e 212 #define R92C_ACKTO 0x640 213 #define R92C_NAV_UPPER 0x652 214 #define R92C_WMAC_TRXPTCL_CTL 0x668 215 #define R92C_CAMCMD 0x670 216 #define R92C_CAMWRITE 0x674 217 #define R92C_CAMREAD 0x678 218 #define R92C_CAMDBG 0x67c 219 #define R92C_SECCFG 0x680 220 #define R92C_RXFLTMAP0 0x6a0 221 #define R92C_RXFLTMAP1 0x6a2 222 #define R92C_RXFLTMAP2 0x6a4 223 #define R92C_BCN_PSR_RPT 0x6a8 224 #define R92C_MACID1 0x700 225 #define R92C_BSSID1 0x708 226 227 228 #define R92C_MACID(id) ((id) == 0 ? R92C_MACID0 : R92C_MACID1) 229 #define R92C_BSSID(id) ((id) == 0 ? R92C_BSSID0 : R92C_BSSID1) 230 231 /* Bits for R92C_SYS_ISO_CTRL. */ 232 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 233 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 234 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 235 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 236 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 237 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 238 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 239 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 240 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 241 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 242 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 243 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 244 245 /* Bits for R92C_SYS_FUNC_EN. */ 246 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 247 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 248 #define R92C_SYS_FUNC_EN_USBA 0x0004 249 #define R92C_SYS_FUNC_EN_UPLL 0x0008 250 #define R92C_SYS_FUNC_EN_USBD 0x0010 251 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 252 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 253 #define R92C_SYS_FUNC_EN_PPLL 0x0080 254 #define R92C_SYS_FUNC_EN_PCIED 0x0100 255 #define R92C_SYS_FUNC_EN_DIOE 0x0200 256 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 257 #define R92C_SYS_FUNC_EN_DCORE 0x0800 258 #define R92C_SYS_FUNC_EN_ELDR 0x1000 259 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 260 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 261 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 262 263 /* Bits for R92C_APS_FSMCO. */ 264 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 265 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 266 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 267 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 268 #define R92C_APS_FSMCO_PDN_EN 0x00000010 269 #define R92C_APS_FSMCO_PDN_PL 0x00000020 270 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 271 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 272 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 273 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 274 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 275 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 276 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 277 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 278 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 279 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 280 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 281 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 282 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 283 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 284 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 285 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 286 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 287 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 288 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 289 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 290 291 /* Bits for R92C_SYS_CLKR. */ 292 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 293 #define R92C_SYS_CLKR_ANA8M 0x00000002 294 #define R92C_SYS_CLKR_MACSLP 0x00000010 295 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 296 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 297 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 298 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 299 #define R92C_SYS_CLKR_SEC_EN 0x00000400 300 #define R92C_SYS_CLKR_MAC_EN 0x00000800 301 #define R92C_SYS_CLKR_SYS_EN 0x00001000 302 #define R92C_SYS_CLKR_RING_EN 0x00002000 303 304 /* Bits for R92C_RSV_CTRL. */ 305 #define R92C_RSV_CTRL_WLOCK_ALL 0x01 306 #define R92C_RSV_CTRL_WLOCK_00 0x02 307 #define R92C_RSV_CTRL_WLOCK_04 0x04 308 #define R92C_RSV_CTRL_WLOCK_08 0x08 309 #define R92C_RSV_CTRL_WLOCK_40 0x10 310 #define R92C_RSV_CTRL_R_DIS_PRST_0 0x20 311 #define R92C_RSV_CTRL_R_DIS_PRST_1 0x40 312 #define R92C_RSV_CTRL_LOCK_ALL_EN 0x80 313 314 /* Bits for R92C_RF_CTRL. */ 315 #define R92C_RF_CTRL_EN 0x01 316 #define R92C_RF_CTRL_RSTB 0x02 317 #define R92C_RF_CTRL_SDMRSTB 0x04 318 319 /* Bits for R92C_LDOA15_CTRL. */ 320 #define R92C_LDOA15_CTRL_EN 0x01 321 #define R92C_LDOA15_CTRL_STBY 0x02 322 #define R92C_LDOA15_CTRL_OBUF 0x04 323 #define R92C_LDOA15_CTRL_REG_VOS 0x08 324 325 /* Bits for R92C_LDOV12D_CTRL. */ 326 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 327 328 /* Bits for R92C_LPLDO_CTRL. */ 329 #define R92C_LPLDO_CTRL_SLEEP 0x10 330 331 /* Bits for R92C_AFE_XTAL_CTRL. */ 332 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800 333 #define R92C_AFE_XTAL_CTRL_ADDR_S 11 334 335 /* Bits for R92C_AFE_PLL_CTRL. */ 336 #define R92C_AFE_PLL_CTRL_EN 0x0001 337 #define R92C_AFE_PLL_CTRL_320_EN 0x0002 338 #define R92C_AFE_PLL_CTRL_FREF_SEL 0x0004 339 #define R92C_AFE_PLL_CTRL_EDGE_SEL 0x0008 340 #define R92C_AFE_PLL_CTRL_WDOGB 0x0010 341 #define R92C_AFE_PLL_CTRL_LPFEN 0x0020 342 343 /* Bits for R92C_EFUSE_CTRL. */ 344 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 345 #define R92C_EFUSE_CTRL_DATA_S 0 346 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 347 #define R92C_EFUSE_CTRL_ADDR_S 8 348 #define R92C_EFUSE_CTRL_VALID 0x80000000 349 350 /* Bits for R92C_GPIO_MUXCFG. */ 351 #define R92C_GPIO_MUXCFG_ENBT 0x0020 352 #define R92C_GPIO_MUXCFG_ENSIC 0x1000 353 354 /* Bits for R92C_LEDCFG0. */ 355 #define R92C_LEDCFG0_DIS 0x08 356 357 /* Bits for R92C_LEDCFG1. */ 358 #define R92C_LEDCFG1_DIS 0x80 359 360 /* Bits for R92C_MULTI_FUNC_CTRL. */ 361 #define R92C_MULTI_BT_FUNC_EN 0x00040000 362 363 /* Bits for R92C_MCUFWDL. */ 364 #define R92C_MCUFWDL_EN 0x00000001 365 #define R92C_MCUFWDL_RDY 0x00000002 366 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 367 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 368 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 369 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 370 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 371 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 372 #define R92C_MCUFWDL_PAGE_M 0x00070000 373 #define R92C_MCUFWDL_PAGE_S 16 374 #define R92C_MCUFWDL_ROM_DLEN 0x00080000 375 #define R92C_MCUFWDL_CPRST 0x00800000 376 377 /* Bits for R92C_EFUSE_ACCESS. */ 378 #define R92C_EFUSE_ACCESS_OFF 0x00 379 #define R92C_EFUSE_ACCESS_ON 0x69 380 381 /* Bits for R92C_HPON_FSM. */ 382 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 383 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 384 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 385 386 /* Bits for R92C_SYS_CFG. */ 387 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 388 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 389 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 390 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 391 #define R92C_SYS_CFG_PCIRSTB 0x00000010 392 #define R92C_SYS_CFG_V15_VLD 0x00000020 393 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 394 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 395 #define R92C_SYS_CFG_BD_MAC2 0x00000200 396 #define R92C_SYS_CFG_BD_MAC1 0x00000400 397 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 398 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 399 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 400 #define R92C_SYS_CFG_BT_FUNC 0x00010000 401 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 402 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 403 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 404 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 405 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 406 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 407 #define R92C_SYS_CFG_TYPE_92C 0x08000000 408 409 /* Bits for R92C_CR. */ 410 #define R92C_CR_HCI_TXDMA_EN 0x0001 411 #define R92C_CR_HCI_RXDMA_EN 0x0002 412 #define R92C_CR_TXDMA_EN 0x0004 413 #define R92C_CR_RXDMA_EN 0x0008 414 #define R92C_CR_PROTOCOL_EN 0x0010 415 #define R92C_CR_SCHEDULE_EN 0x0020 416 #define R92C_CR_MACTXEN 0x0040 417 #define R92C_CR_MACRXEN 0x0080 418 #define R92C_CR_ENSWBCN 0x0100 419 #define R92C_CR_ENSEC 0x0200 420 #define R92C_CR_CALTMR_EN 0x0400 421 422 /* Bits for R92C_MSR. */ 423 #define R92C_MSR_NOLINK 0x00 424 #define R92C_MSR_ADHOC 0x01 425 #define R92C_MSR_INFRA 0x02 426 #define R92C_MSR_AP 0x03 427 #define R92C_MSR_MASK (R92C_MSR_AP) 428 429 /* Bits for R92C_PBP. */ 430 #define R92C_PBP_PSRX_M 0x0f 431 #define R92C_PBP_PSRX_S 0 432 #define R92C_PBP_PSTX_M 0xf0 433 #define R92C_PBP_PSTX_S 4 434 #define R92C_PBP_64 0 435 #define R92C_PBP_128 1 436 #define R92C_PBP_256 2 437 #define R92C_PBP_512 3 438 #define R92C_PBP_1024 4 439 440 /* Bits for R92C_TRXDMA_CTRL. */ 441 #define R92C_TRXDMA_CTRL_RX_SHIFT_EN 0x0002 442 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 443 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 444 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 445 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 446 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 447 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 448 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 449 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 450 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 451 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 452 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 453 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 454 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 455 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 456 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 457 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 458 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 459 /* Shortcuts. */ 460 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 461 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 462 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 463 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 464 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 465 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 466 467 /* Bits for R92C_C2H_EVT_CLEAR. */ 468 #define R92C_C2H_EVT_HOST_CLOSE 0x00 469 #define R92C_C2H_EVT_FW_CLOSE 0xff 470 471 /* Bits for R92C_LLT_INIT. */ 472 #define R92C_LLT_INIT_DATA_M 0x000000ff 473 #define R92C_LLT_INIT_DATA_S 0 474 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 475 #define R92C_LLT_INIT_ADDR_S 8 476 #define R92C_LLT_INIT_OP_M 0xc0000000 477 #define R92C_LLT_INIT_OP_S 30 478 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 479 #define R92C_LLT_INIT_OP_WRITE 1 480 481 /* Bits for R92C_RQPN. */ 482 #define R92C_RQPN_HPQ_M 0x000000ff 483 #define R92C_RQPN_HPQ_S 0 484 #define R92C_RQPN_LPQ_M 0x0000ff00 485 #define R92C_RQPN_LPQ_S 8 486 #define R92C_RQPN_PUBQ_M 0x00ff0000 487 #define R92C_RQPN_PUBQ_S 16 488 #define R92C_RQPN_LD 0x80000000 489 490 /* Bits for R92C_TDECTRL. */ 491 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0 492 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 493 #define R92C_TDECTRL_BCN_VALID 0x00010000 494 495 /* Bits for R92C_TXDMA_OFFSET_CHK. */ 496 #define R92C_TXDMA_OFFSET_DROP_DATA_EN 0x00000200 497 498 /* Bits for R92C_AUTO_LLT. */ 499 #define R92C_AUTO_LLT_INIT 0x00010000 500 501 /* Bits for R92C_FWHW_TXQ_CTRL. */ 502 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 503 #define R92C_FWHW_TXQ_CTRL_REAL_BEACON 0x400000 504 505 /* Bits for R92C_SPEC_SIFS. */ 506 #define R92C_SPEC_SIFS_CCK_M 0x00ff 507 #define R92C_SPEC_SIFS_CCK_S 0 508 #define R92C_SPEC_SIFS_OFDM_M 0xff00 509 #define R92C_SPEC_SIFS_OFDM_S 8 510 511 /* Bits for R92C_RL. */ 512 #define R92C_RL_LRL_M 0x003f 513 #define R92C_RL_LRL_S 0 514 #define R92C_RL_SRL_M 0x3f00 515 #define R92C_RL_SRL_S 8 516 517 /* Size of R92C_DARFRC. */ 518 #define R92C_DARFRC_SIZE 8 519 520 /* Bits for R92C_RRSR. */ 521 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 522 #define R92C_RRSR_RATE_BITMAP_S 0 523 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 524 #define R92C_RRSR_RATE_ALL 0xfffff 525 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 526 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 527 #define R92C_RRSR_SHORT 0x00800000 528 529 /* Bits for R92C_EDCA_XX_PARAM. */ 530 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 531 #define R92C_EDCA_PARAM_AIFS_S 0 532 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 533 #define R92C_EDCA_PARAM_ECWMIN_S 8 534 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 535 #define R92C_EDCA_PARAM_ECWMAX_S 12 536 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 537 #define R92C_EDCA_PARAM_TXOP_S 16 538 539 /* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */ 540 #define R92C_TX_QUEUE_VO 0x01 541 #define R92C_TX_QUEUE_VI 0x02 542 #define R92C_TX_QUEUE_BE 0x04 543 #define R92C_TX_QUEUE_BK 0x08 544 #define R92C_TX_QUEUE_MGT 0x10 545 #define R92C_TX_QUEUE_HIGH 0x20 546 #define R92C_TX_QUEUE_BCN 0x40 547 548 /* Shortcuts. */ 549 #define R92C_TX_QUEUE_AC \ 550 (R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI | \ 551 R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK) 552 553 #define R92C_TX_QUEUE_ALL \ 554 (R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | \ 555 R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80) /* XXX */ 556 557 /* Bits for R92C_BCN_CTRL. */ 558 #define R92C_BCN_CTRL_EN_MBSSID 0x02 559 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 560 #define R92C_BCN_CTRL_EN_BCN 0x08 561 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 562 563 /* Bits for R92C_DUAL_TSF_RST. */ 564 #define R92C_DUAL_TSF_RESET(id) (0x01 << (id)) 565 #define R92C_DUAL_TSF_RST_TXOK 0x20 566 567 /* Bits for R92C_ACMHWCTRL. */ 568 #define R92C_ACMHWCTRL_EN 0x01 569 #define R92C_ACMHWCTRL_BE 0x02 570 #define R92C_ACMHWCTRL_VI 0x04 571 #define R92C_ACMHWCTRL_VO 0x08 572 #define R92C_ACMHWCTRL_ACM_MASK 0x0f 573 574 /* Bits for R92C_APSD_CTRL. */ 575 #define R92C_APSD_CTRL_OFF 0x40 576 #define R92C_APSD_CTRL_OFF_STATUS 0x80 577 578 /* Bits for R92C_BWOPMODE. */ 579 #define R92C_BWOPMODE_11J 0x01 580 #define R92C_BWOPMODE_5G 0x02 581 #define R92C_BWOPMODE_20MHZ 0x04 582 583 /* Bits for R92C_TCR. */ 584 #define R92C_TCR_TSFRST 0x00000001 585 #define R92C_TCR_DIS_GCLK 0x00000002 586 #define R92C_TCR_PAD_SEL 0x00000004 587 #define R92C_TCR_PWR_ST 0x00000040 588 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 589 #define R92C_TCR_ACRC 0x00000100 590 #define R92C_TCR_CFENDFORM 0x00000200 591 #define R92C_TCR_ICV 0x00000400 592 593 /* Bits for R92C_RCR. */ 594 #define R92C_RCR_AAP 0x00000001 595 #define R92C_RCR_APM 0x00000002 596 #define R92C_RCR_AM 0x00000004 597 #define R92C_RCR_AB 0x00000008 598 #define R92C_RCR_ADD3 0x00000010 599 #define R92C_RCR_APWRMGT 0x00000020 600 #define R92C_RCR_CBSSID_DATA 0x00000040 601 #define R92C_RCR_CBSSID_BCN 0x00000080 602 #define R92C_RCR_ACRC32 0x00000100 603 #define R92C_RCR_AICV 0x00000200 604 #define R92C_RCR_ADF 0x00000800 605 #define R92C_RCR_ACF 0x00001000 606 #define R92C_RCR_AMF 0x00002000 607 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 608 #define R92C_RCR_MFBEN 0x00400000 609 #define R92C_RCR_LSIGEN 0x00800000 610 #define R92C_RCR_ENMBID 0x01000000 611 #define R92C_RCR_APP_BA_SSN 0x08000000 612 #define R92C_RCR_APP_PHYSTS 0x10000000 613 #define R92C_RCR_APP_ICV 0x20000000 614 #define R92C_RCR_APP_MIC 0x40000000 615 #define R92C_RCR_APPFCS 0x80000000 616 617 /* Bits for R92C_RX_DRVINFO_SZ. */ 618 /* XXX other values will not work */ 619 #define R92C_RX_DRVINFO_SZ_DEF ((RTWN_PHY_STATUS_SIZE) / 8) 620 621 /* Bits for R92C_WMAC_TRXPTCL_CTL. */ 622 #define R92C_WMAC_TRXPTCL_SHPRE 0x00020000 623 624 /* Bits for R92C_CAMCMD. */ 625 #define R92C_CAMCMD_ADDR_M 0x0000ffff 626 #define R92C_CAMCMD_ADDR_S 0 627 #define R92C_CAMCMD_WRITE 0x00010000 628 #define R92C_CAMCMD_CLR 0x40000000 629 #define R92C_CAMCMD_POLLING 0x80000000 630 631 632 /* 633 * CAM entries. 634 */ 635 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 636 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 637 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 638 #define R92C_CAM_CTL6(entry) ((entry) * 8 + 6) 639 #define R92C_CAM_CTL7(entry) ((entry) * 8 + 7) 640 641 /* Bits for R92C_CAM_CTL0(i). */ 642 #define R92C_CAM_KEYID_M 0x00000003 643 #define R92C_CAM_KEYID_S 0 644 #define R92C_CAM_ALGO_M 0x0000001c 645 #define R92C_CAM_ALGO_S 2 646 #define R92C_CAM_ALGO_NONE 0 647 #define R92C_CAM_ALGO_WEP40 1 648 #define R92C_CAM_ALGO_TKIP 2 649 #define R92C_CAM_ALGO_AES 4 650 #define R92C_CAM_ALGO_WEP104 5 651 #define R92C_CAM_VALID 0x00008000 652 #define R92C_CAM_MACLO_M 0xffff0000 653 #define R92C_CAM_MACLO_S 16 654 655 /* Bits for R92C_SECCFG. */ 656 #define R92C_SECCFG_TXUCKEY_DEF 0x0001 657 #define R92C_SECCFG_RXUCKEY_DEF 0x0002 658 #define R92C_SECCFG_TXENC_ENA 0x0004 659 #define R92C_SECCFG_RXDEC_ENA 0x0008 660 #define R92C_SECCFG_CMP_A2 0x0010 661 #define R92C_SECCFG_MC_SRCH_DIS 0x0020 662 #define R92C_SECCFG_TXBCKEY_DEF 0x0040 663 #define R92C_SECCFG_RXBCKEY_DEF 0x0080 664 665 /* Bits for R92C_RXFLTMAP*. */ 666 #define R92C_RXFLTMAP_SUBTYPE(subtype) \ 667 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 668 669 670 /* 671 * Baseband registers. 672 */ 673 #define R92C_FPGA0_RFMOD 0x800 674 #define R92C_FPGA0_TXINFO 0x804 675 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 676 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 677 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 678 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 679 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 680 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 681 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 682 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 683 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 684 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 685 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 686 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 687 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 688 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 689 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 690 #define R92C_FPGA0_ANAPARAM2 0x884 691 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 692 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 693 #define R92C_FPGA1_RFMOD 0x900 694 #define R92C_FPGA1_TXINFO 0x90c 695 #define R92C_CCK0_SYSTEM 0xa00 696 #define R92C_CCK0_AFESETTING 0xa04 697 #define R92C_CONFIG_ANT(chain) (0xb68 + (chain) * 4) 698 #define R92C_OFDM0_TRXPATHENA 0xc04 699 #define R92C_OFDM0_TRMUXPAR 0xc08 700 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 701 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 702 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 703 #define R92C_OFDM0_AGCPARAM1 0xc70 704 #define R92C_OFDM0_AGCRSSITABLE 0xc78 705 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 706 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 707 #define R92C_OFDM0_RXIQEXTANTA 0xca0 708 #define R92C_OFDM0_TXPSEUDONOISEWGT 0xce4 709 #define R92C_OFDM1_LSTF 0xd00 710 #define R92C_FPGA0_IQK 0xe28 711 #define R92C_TX_IQK_TONE(chain) (0xe30 + (chain) * 32) 712 #define R92C_RX_IQK_TONE(chain) (0xe34 + (chain) * 32) 713 #define R92C_TX_IQK_PI(chain) (0xe38 + (chain) * 32) 714 #define R92C_RX_IQK_PI(chain) (0xe3c + (chain) * 32) 715 #define R92C_TX_IQK 0xe40 716 #define R92C_RX_IQK 0xe44 717 #define R92C_IQK_AGC_PTS 0xe48 718 #define R92C_IQK_AGC_RSP 0xe4c 719 #define R92C_IQK_AGC_CONT 0xe60 720 #define R92C_TX_POWER_IQK_BEFORE(chain) (0xe94 + (chain) * 32) 721 #define R92C_TX_POWER_IQK_AFTER(chain) (0xe9c + (chain) * 32) 722 #define R92C_RX_POWER_IQK_BEFORE(chain) (0xea4 + (chain) * 32) 723 #define R92C_RX_POWER_IQK_AFTER(chain) (0xeac + (chain) * 32) 724 725 /* Bits for R92C_FPGA[01]_RFMOD. */ 726 #define R92C_RFMOD_40MHZ 0x00000001 727 #define R92C_RFMOD_JAPAN 0x00000002 728 #define R92C_RFMOD_CCK_TXSC 0x00000030 729 #define R92C_RFMOD_CCK_EN 0x01000000 730 #define R92C_RFMOD_OFDM_EN 0x02000000 731 732 /* Bits for R92C_HSSI_PARAM1(i). */ 733 #define R92C_HSSI_PARAM1_PI 0x00000100 734 735 /* Bits for R92C_HSSI_PARAM2(i). */ 736 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 737 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 738 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 739 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 740 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 741 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 742 743 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 744 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 745 #define R92C_TXAGC_A_CCK1_S 8 746 747 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 748 #define R92C_TXAGC_B_CCK11_M 0x000000ff 749 #define R92C_TXAGC_B_CCK11_S 0 750 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 751 #define R92C_TXAGC_A_CCK2_S 8 752 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 753 #define R92C_TXAGC_A_CCK55_S 16 754 #define R92C_TXAGC_A_CCK11_M 0xff000000 755 #define R92C_TXAGC_A_CCK11_S 24 756 757 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 758 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 759 #define R92C_TXAGC_B_CCK1_S 8 760 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 761 #define R92C_TXAGC_B_CCK2_S 16 762 #define R92C_TXAGC_B_CCK55_M 0xff000000 763 #define R92C_TXAGC_B_CCK55_S 24 764 765 /* Bits for R92C_TXAGC_RATE18_06(x). */ 766 #define R92C_TXAGC_RATE06_M 0x000000ff 767 #define R92C_TXAGC_RATE06_S 0 768 #define R92C_TXAGC_RATE09_M 0x0000ff00 769 #define R92C_TXAGC_RATE09_S 8 770 #define R92C_TXAGC_RATE12_M 0x00ff0000 771 #define R92C_TXAGC_RATE12_S 16 772 #define R92C_TXAGC_RATE18_M 0xff000000 773 #define R92C_TXAGC_RATE18_S 24 774 775 /* Bits for R92C_TXAGC_RATE54_24(x). */ 776 #define R92C_TXAGC_RATE24_M 0x000000ff 777 #define R92C_TXAGC_RATE24_S 0 778 #define R92C_TXAGC_RATE36_M 0x0000ff00 779 #define R92C_TXAGC_RATE36_S 8 780 #define R92C_TXAGC_RATE48_M 0x00ff0000 781 #define R92C_TXAGC_RATE48_S 16 782 #define R92C_TXAGC_RATE54_M 0xff000000 783 #define R92C_TXAGC_RATE54_S 24 784 785 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 786 #define R92C_TXAGC_MCS00_M 0x000000ff 787 #define R92C_TXAGC_MCS00_S 0 788 #define R92C_TXAGC_MCS01_M 0x0000ff00 789 #define R92C_TXAGC_MCS01_S 8 790 #define R92C_TXAGC_MCS02_M 0x00ff0000 791 #define R92C_TXAGC_MCS02_S 16 792 #define R92C_TXAGC_MCS03_M 0xff000000 793 #define R92C_TXAGC_MCS03_S 24 794 795 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 796 #define R92C_TXAGC_MCS04_M 0x000000ff 797 #define R92C_TXAGC_MCS04_S 0 798 #define R92C_TXAGC_MCS05_M 0x0000ff00 799 #define R92C_TXAGC_MCS05_S 8 800 #define R92C_TXAGC_MCS06_M 0x00ff0000 801 #define R92C_TXAGC_MCS06_S 16 802 #define R92C_TXAGC_MCS07_M 0xff000000 803 #define R92C_TXAGC_MCS07_S 24 804 805 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 806 #define R92C_TXAGC_MCS08_M 0x000000ff 807 #define R92C_TXAGC_MCS08_S 0 808 #define R92C_TXAGC_MCS09_M 0x0000ff00 809 #define R92C_TXAGC_MCS09_S 8 810 #define R92C_TXAGC_MCS10_M 0x00ff0000 811 #define R92C_TXAGC_MCS10_S 16 812 #define R92C_TXAGC_MCS11_M 0xff000000 813 #define R92C_TXAGC_MCS11_S 24 814 815 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 816 #define R92C_TXAGC_MCS12_M 0x000000ff 817 #define R92C_TXAGC_MCS12_S 0 818 #define R92C_TXAGC_MCS13_M 0x0000ff00 819 #define R92C_TXAGC_MCS13_S 8 820 #define R92C_TXAGC_MCS14_M 0x00ff0000 821 #define R92C_TXAGC_MCS14_S 16 822 #define R92C_TXAGC_MCS15_M 0xff000000 823 #define R92C_TXAGC_MCS15_S 24 824 825 /* Bits for R92C_LSSI_PARAM(i). */ 826 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 827 #define R92C_LSSI_PARAM_DATA_S 0 828 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 829 #define R92C_LSSI_PARAM_ADDR_S 20 830 831 /* Bits for R92C_FPGA0_RFIFACEOE(0). */ 832 #define R92C_FPGA0_RFIFACEOE0_ANT_M 0x00000300 833 #define R92C_FPGA0_RFIFACEOE0_ANT_S 8 834 835 /* Bits for R92C_FPGA0_ANAPARAM2. */ 836 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 837 838 /* Bits for R92C_LSSI_READBACK(i). */ 839 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 840 #define R92C_LSSI_READBACK_DATA_S 0 841 842 /* Bits for R92C_CCK0_SYSTEM. */ 843 #define R92C_CCK0_SYSTEM_CCK_SIDEBAND 0x00000010 844 845 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 846 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 847 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 848 849 /* Bits for R92C_[RT]X_POWER_IQK*. */ 850 #define R92C_POWER_IQK_RESULT_S 16 851 #define R92C_POWER_IQK_RESULT_M 0x03ff0000 852 853 854 /* 855 * RF (6052) registers. 856 */ 857 #define R92C_RF_AC 0x00 858 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 859 #define R92C_RF_POW_TRSW 0x05 860 #define R92C_RF_GAIN_RX 0x06 861 #define R92C_RF_GAIN_TX 0x07 862 #define R92C_RF_TXM_IDAC 0x08 863 #define R92C_RF_BS_IQGEN 0x0f 864 #define R92C_RF_MODE1 0x10 865 #define R92C_RF_MODE2 0x11 866 #define R92C_RF_RX_AGC_HP 0x12 867 #define R92C_RF_TX_AGC 0x13 868 #define R92C_RF_BIAS 0x14 869 #define R92C_RF_IPA 0x15 870 #define R92C_RF_POW_ABILITY 0x17 871 #define R92C_RF_CHNLBW 0x18 872 #define R92C_RF_RX_G1 0x1a 873 #define R92C_RF_RX_G2 0x1b 874 #define R92C_RF_RX_BB2 0x1c 875 #define R92C_RF_RX_BB1 0x1d 876 #define R92C_RF_RCK1 0x1e 877 #define R92C_RF_RCK2 0x1f 878 #define R92C_RF_TX_G(i) (0x20 + (i)) 879 #define R92C_RF_TX_BB1 0x23 880 #define R92C_RF_T_METER 0x24 881 #define R92C_RF_SYN_G(i) (0x25 + (i)) 882 #define R92C_RF_RCK_OS 0x30 883 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 884 885 /* Bits for R92C_RF_AC. */ 886 #define R92C_RF_AC_MODE_M 0x70000 887 #define R92C_RF_AC_MODE_S 16 888 #define R92C_RF_AC_MODE_STANDBY 1 889 890 /* Bits for R92C_RF_CHNLBW. */ 891 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 892 #define R92C_RF_CHNLBW_CHNL_S 0 893 #define R92C_RF_CHNLBW_BW20 0x00400 894 #define R92C_RF_CHNLBW_LCSTART 0x08000 895 896 /* Bits for R92C_RF_T_METER. */ 897 #define R92C_RF_T_METER_START 0x60 898 #define R92C_RF_T_METER_VAL_M 0x1f 899 #define R92C_RF_T_METER_VAL_S 0 900 901 #endif /* R92C_REG_H */ 902