1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 #include "opt_wlan.h" 25 26 #include <sys/param.h> 27 #include <sys/lock.h> 28 #include <sys/mutex.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/linker.h> 39 40 #include <net/if.h> 41 #include <net/ethernet.h> 42 #include <net/if_media.h> 43 44 #include <net80211/ieee80211_var.h> 45 #include <net80211/ieee80211_radiotap.h> 46 47 #include <dev/rtwn/if_rtwnreg.h> 48 #include <dev/rtwn/if_rtwnvar.h> 49 #include <dev/rtwn/if_rtwn_debug.h> 50 51 #include <dev/rtwn/rtl8192c/r92c.h> 52 #include <dev/rtwn/rtl8192c/r92c_priv.h> 53 #include <dev/rtwn/rtl8192c/r92c_reg.h> 54 #include <dev/rtwn/rtl8192c/r92c_var.h> 55 56 57 int 58 r92c_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 59 { 60 struct r92c_softc *rs = sc->sc_priv; 61 uint8_t mask; 62 int i; 63 64 if (cond[0] == 0) 65 return (1); 66 67 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 68 "%s: condition byte 0: %02X; chip %02X, board %02X\n", 69 __func__, cond[0], rs->chip, rs->board_type); 70 71 if (!(rs->chip & R92C_CHIP_92C)) { 72 if (rs->board_type == R92C_BOARD_TYPE_HIGHPA) 73 mask = R92C_COND_RTL8188RU; 74 else if (rs->board_type == R92C_BOARD_TYPE_MINICARD) 75 mask = R92C_COND_RTL8188CE; 76 else 77 mask = R92C_COND_RTL8188CU; 78 } else { 79 if (rs->board_type == R92C_BOARD_TYPE_MINICARD) 80 mask = R92C_COND_RTL8192CE; 81 else 82 mask = R92C_COND_RTL8192CU; 83 } 84 85 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 86 if ((cond[i] & mask) == mask) 87 return (1); 88 89 return (0); 90 } 91 92 int 93 r92c_set_page_size(struct rtwn_softc *sc) 94 { 95 return (rtwn_write_1(sc, R92C_PBP, SM(R92C_PBP_PSRX, R92C_PBP_128) | 96 SM(R92C_PBP_PSTX, R92C_PBP_128)) == 0); 97 } 98 99 void 100 r92c_init_bb_common(struct rtwn_softc *sc) 101 { 102 struct r92c_softc *rs = sc->sc_priv; 103 int i, j; 104 105 /* Write BB initialization values. */ 106 for (i = 0; i < sc->bb_size; i++) { 107 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 108 109 while (!rtwn_check_condition(sc, bb_prog->cond)) { 110 KASSERT(bb_prog->next != NULL, 111 ("%s: wrong condition value (i %d)\n", 112 __func__, i)); 113 bb_prog = bb_prog->next; 114 } 115 116 for (j = 0; j < bb_prog->count; j++) { 117 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 118 "BB: reg 0x%03x, val 0x%08x\n", 119 bb_prog->reg[j], bb_prog->val[j]); 120 121 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 122 rtwn_delay(sc, 1); 123 } 124 } 125 126 if (rs->chip & R92C_CHIP_92C_1T2R) { 127 /* 8192C 1T only configuration. */ 128 rtwn_bb_setbits(sc, R92C_FPGA0_TXINFO, 0x03, 0x02); 129 rtwn_bb_setbits(sc, R92C_FPGA1_TXINFO, 0x300033, 0x200022); 130 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0xff000000, 131 0x45000000); 132 rtwn_bb_setbits(sc, R92C_OFDM0_TRXPATHENA, 0xff, 0x23); 133 rtwn_bb_setbits(sc, R92C_OFDM0_AGCPARAM1, 0x30, 0x10); 134 135 rtwn_bb_setbits(sc, 0xe74, 0x0c000000, 0x08000000); 136 rtwn_bb_setbits(sc, 0xe78, 0x0c000000, 0x08000000); 137 rtwn_bb_setbits(sc, 0xe7c, 0x0c000000, 0x08000000); 138 rtwn_bb_setbits(sc, 0xe80, 0x0c000000, 0x08000000); 139 rtwn_bb_setbits(sc, 0xe88, 0x0c000000, 0x08000000); 140 } 141 142 /* Write AGC values. */ 143 for (i = 0; i < sc->agc_size; i++) { 144 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 145 146 while (!rtwn_check_condition(sc, agc_prog->cond)) { 147 KASSERT(agc_prog->next != NULL, 148 ("%s: wrong condition value (2) (i %d)\n", 149 __func__, i)); 150 agc_prog = agc_prog->next; 151 } 152 153 for (j = 0; j < agc_prog->count; j++) { 154 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 155 "AGC: val 0x%08x\n", agc_prog->val[j]); 156 157 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 158 agc_prog->val[j]); 159 rtwn_delay(sc, 1); 160 } 161 } 162 163 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 164 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 165 } 166 167 int 168 r92c_init_rf_chain(struct rtwn_softc *sc, 169 const struct rtwn_rf_prog *rf_prog, int chain) 170 { 171 int i, j; 172 173 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, "%s: chain %d\n", 174 __func__, chain); 175 176 for (i = 0; rf_prog[i].reg != NULL; i++) { 177 const struct rtwn_rf_prog *prog = &rf_prog[i]; 178 179 while (!rtwn_check_condition(sc, prog->cond)) { 180 KASSERT(prog->next != NULL, 181 ("%s: wrong condition value (i %d)\n", 182 __func__, i)); 183 prog = prog->next; 184 } 185 186 for (j = 0; j < prog->count; j++) { 187 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 188 "RF: reg 0x%02x, val 0x%05x\n", 189 prog->reg[j], prog->val[j]); 190 191 /* 192 * These are fake RF registers offsets that 193 * indicate a delay is required. 194 */ 195 /* NB: we are using 'value' to store required delay. */ 196 if (prog->reg[j] > 0xf8) { 197 rtwn_delay(sc, prog->val[j]); 198 continue; 199 } 200 201 rtwn_rf_write(sc, chain, prog->reg[j], prog->val[j]); 202 rtwn_delay(sc, 1); 203 } 204 } 205 206 return (i); 207 } 208 209 void 210 r92c_init_rf(struct rtwn_softc *sc) 211 { 212 struct r92c_softc *rs = sc->sc_priv; 213 uint32_t reg, type; 214 int i, chain, idx, off; 215 216 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 217 /* Save RF_ENV control type. */ 218 idx = chain / 2; 219 off = (chain % 2) * 16; 220 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 221 type = (reg >> off) & 0x10; 222 223 /* Set RF_ENV enable. */ 224 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 225 0, 0x100000); 226 rtwn_delay(sc, 1); 227 /* Set RF_ENV output high. */ 228 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 229 0, 0x10); 230 rtwn_delay(sc, 1); 231 /* Set address and data lengths of RF registers. */ 232 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 233 R92C_HSSI_PARAM2_ADDR_LENGTH, 0); 234 rtwn_delay(sc, 1); 235 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 236 R92C_HSSI_PARAM2_DATA_LENGTH, 0); 237 rtwn_delay(sc, 1); 238 239 /* Write RF initialization values for this chain. */ 240 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 241 242 /* Restore RF_ENV control type. */ 243 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(idx), 244 0x10 << off, type << off); 245 246 /* Cache RF register CHNLBW. */ 247 rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, 248 R92C_RF_CHNLBW); 249 } 250 251 if ((rs->chip & (R92C_CHIP_UMC_A_CUT | R92C_CHIP_92C)) == 252 R92C_CHIP_UMC_A_CUT) { 253 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 254 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 255 } 256 257 /* Turn CCK and OFDM blocks on. */ 258 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN); 259 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN); 260 } 261 262 void 263 r92c_init_edca(struct rtwn_softc *sc) 264 { 265 /* SIFS */ 266 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 267 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 268 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 269 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 270 /* TXOP */ 271 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 272 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 273 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 274 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 275 } 276 277 void 278 r92c_init_ampdu(struct rtwn_softc *sc) 279 { 280 281 /* Setup AMPDU aggregation. */ 282 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 283 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 284 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 285 } 286 287 void 288 r92c_init_antsel(struct rtwn_softc *sc) 289 { 290 uint32_t reg; 291 292 if (sc->ntxchains != 1 || sc->nrxchains != 1) 293 return; 294 295 rtwn_setbits_1(sc, R92C_LEDCFG2, 0, 0x80); 296 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); 297 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 298 sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); /* XXX */ 299 } 300 301 void 302 r92c_pa_bias_init(struct rtwn_softc *sc) 303 { 304 struct r92c_softc *rs = sc->sc_priv; 305 int i; 306 307 for (i = 0; i < sc->nrxchains; i++) { 308 if (rs->pa_setting & (1 << i)) 309 continue; 310 r92c_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 311 r92c_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 312 r92c_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 313 r92c_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 314 } 315 if (!(rs->pa_setting & 0x10)) 316 rtwn_setbits_1(sc, 0x16, 0xf0, 0x90); 317 } 318