1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 #include "opt_wlan.h" 23 24 #include <sys/param.h> 25 #include <sys/lock.h> 26 #include <sys/mutex.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/queue.h> 33 #include <sys/taskqueue.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/linker.h> 37 38 #include <net/if.h> 39 #include <net/ethernet.h> 40 #include <net/if_media.h> 41 42 #include <net80211/ieee80211_var.h> 43 #include <net80211/ieee80211_radiotap.h> 44 45 #include <dev/rtwn/if_rtwnreg.h> 46 #include <dev/rtwn/if_rtwnvar.h> 47 #include <dev/rtwn/if_rtwn_debug.h> 48 49 #include <dev/rtwn/rtl8192c/r92c.h> 50 #include <dev/rtwn/rtl8192c/r92c_priv.h> 51 #include <dev/rtwn/rtl8192c/r92c_reg.h> 52 #include <dev/rtwn/rtl8192c/r92c_var.h> 53 54 int 55 r92c_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 56 { 57 struct r92c_softc *rs = sc->sc_priv; 58 uint8_t mask; 59 int i; 60 61 if (cond[0] == 0) 62 return (1); 63 64 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 65 "%s: condition byte 0: %02X; chip %02X, board %02X\n", 66 __func__, cond[0], rs->chip, rs->board_type); 67 68 if (!(rs->chip & R92C_CHIP_92C)) { 69 if (rs->board_type == R92C_BOARD_TYPE_HIGHPA) 70 mask = R92C_COND_RTL8188RU; 71 else if (rs->board_type == R92C_BOARD_TYPE_MINICARD) 72 mask = R92C_COND_RTL8188CE; 73 else 74 mask = R92C_COND_RTL8188CU; 75 } else { 76 if (rs->board_type == R92C_BOARD_TYPE_MINICARD) 77 mask = R92C_COND_RTL8192CE; 78 else 79 mask = R92C_COND_RTL8192CU; 80 } 81 82 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 83 if ((cond[i] & mask) == mask) 84 return (1); 85 86 return (0); 87 } 88 89 int 90 r92c_llt_init(struct rtwn_softc *sc) 91 { 92 int i, error; 93 94 /* Reserve pages [0; page_count]. */ 95 for (i = 0; i < sc->page_count; i++) { 96 if ((error = r92c_llt_write(sc, i, i + 1)) != 0) 97 return (error); 98 } 99 /* NB: 0xff indicates end-of-list. */ 100 if ((error = r92c_llt_write(sc, i, 0xff)) != 0) 101 return (error); 102 /* 103 * Use pages [page_count + 1; pktbuf_count - 1] 104 * as ring buffer. 105 */ 106 for (++i; i < sc->pktbuf_count - 1; i++) { 107 if ((error = r92c_llt_write(sc, i, i + 1)) != 0) 108 return (error); 109 } 110 /* Make the last page point to the beginning of the ring buffer. */ 111 error = r92c_llt_write(sc, i, sc->page_count + 1); 112 return (error); 113 } 114 115 int 116 r92c_set_page_size(struct rtwn_softc *sc) 117 { 118 return (rtwn_write_1(sc, R92C_PBP, SM(R92C_PBP_PSRX, R92C_PBP_128) | 119 SM(R92C_PBP_PSTX, R92C_PBP_128)) == 0); 120 } 121 122 void 123 r92c_init_bb_common(struct rtwn_softc *sc) 124 { 125 struct r92c_softc *rs = sc->sc_priv; 126 int i, j; 127 128 /* Write BB initialization values. */ 129 for (i = 0; i < sc->bb_size; i++) { 130 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 131 132 while (!rtwn_check_condition(sc, bb_prog->cond)) { 133 KASSERT(bb_prog->next != NULL, 134 ("%s: wrong condition value (i %d)\n", 135 __func__, i)); 136 bb_prog = bb_prog->next; 137 } 138 139 for (j = 0; j < bb_prog->count; j++) { 140 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 141 "BB: reg 0x%03x, val 0x%08x\n", 142 bb_prog->reg[j], bb_prog->val[j]); 143 144 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 145 rtwn_delay(sc, 1); 146 } 147 } 148 149 if (rs->chip & R92C_CHIP_92C_1T2R) { 150 /* 8192C 1T only configuration. */ 151 rtwn_bb_setbits(sc, R92C_FPGA0_TXINFO, 0x03, 0x02); 152 rtwn_bb_setbits(sc, R92C_FPGA1_TXINFO, 0x300033, 0x200022); 153 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0xff000000, 154 0x45000000); 155 rtwn_bb_setbits(sc, R92C_OFDM0_TRXPATHENA, 0xff, 0x23); 156 rtwn_bb_setbits(sc, R92C_OFDM0_AGCPARAM1, 0x30, 0x10); 157 158 rtwn_bb_setbits(sc, 0xe74, 0x0c000000, 0x08000000); 159 rtwn_bb_setbits(sc, 0xe78, 0x0c000000, 0x08000000); 160 rtwn_bb_setbits(sc, 0xe7c, 0x0c000000, 0x08000000); 161 rtwn_bb_setbits(sc, 0xe80, 0x0c000000, 0x08000000); 162 rtwn_bb_setbits(sc, 0xe88, 0x0c000000, 0x08000000); 163 } 164 165 /* Write AGC values. */ 166 for (i = 0; i < sc->agc_size; i++) { 167 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 168 169 while (!rtwn_check_condition(sc, agc_prog->cond)) { 170 KASSERT(agc_prog->next != NULL, 171 ("%s: wrong condition value (2) (i %d)\n", 172 __func__, i)); 173 agc_prog = agc_prog->next; 174 } 175 176 for (j = 0; j < agc_prog->count; j++) { 177 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 178 "AGC: val 0x%08x\n", agc_prog->val[j]); 179 180 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 181 agc_prog->val[j]); 182 rtwn_delay(sc, 1); 183 } 184 } 185 186 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 187 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 188 } 189 190 int 191 r92c_init_rf_chain(struct rtwn_softc *sc, 192 const struct rtwn_rf_prog *rf_prog, int chain) 193 { 194 int i, j; 195 196 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, "%s: chain %d\n", 197 __func__, chain); 198 199 for (i = 0; rf_prog[i].reg != NULL; i++) { 200 const struct rtwn_rf_prog *prog = &rf_prog[i]; 201 202 while (!rtwn_check_condition(sc, prog->cond)) { 203 KASSERT(prog->next != NULL, 204 ("%s: wrong condition value (i %d)\n", 205 __func__, i)); 206 prog = prog->next; 207 } 208 209 for (j = 0; j < prog->count; j++) { 210 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 211 "RF: reg 0x%02x, val 0x%05x\n", 212 prog->reg[j], prog->val[j]); 213 214 /* 215 * These are fake RF registers offsets that 216 * indicate a delay is required. 217 */ 218 /* NB: we are using 'value' to store required delay. */ 219 if (prog->reg[j] > 0xf8) { 220 rtwn_delay(sc, prog->val[j]); 221 continue; 222 } 223 224 rtwn_rf_write(sc, chain, prog->reg[j], prog->val[j]); 225 rtwn_delay(sc, 1); 226 } 227 } 228 229 return (i); 230 } 231 232 void 233 r92c_init_rf(struct rtwn_softc *sc) 234 { 235 struct r92c_softc *rs = sc->sc_priv; 236 uint32_t reg, type; 237 int i, chain, idx, off; 238 239 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 240 /* Save RF_ENV control type. */ 241 idx = chain / 2; 242 off = (chain % 2) * 16; 243 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 244 type = (reg >> off) & 0x10; 245 246 /* Set RF_ENV enable. */ 247 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 248 0, 0x100000); 249 rtwn_delay(sc, 1); 250 /* Set RF_ENV output high. */ 251 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 252 0, 0x10); 253 rtwn_delay(sc, 1); 254 /* Set address and data lengths of RF registers. */ 255 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 256 R92C_HSSI_PARAM2_ADDR_LENGTH, 0); 257 rtwn_delay(sc, 1); 258 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 259 R92C_HSSI_PARAM2_DATA_LENGTH, 0); 260 rtwn_delay(sc, 1); 261 262 /* Write RF initialization values for this chain. */ 263 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 264 265 /* Restore RF_ENV control type. */ 266 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(idx), 267 0x10 << off, type << off); 268 269 /* Cache RF register CHNLBW. */ 270 rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, 271 R92C_RF_CHNLBW); 272 } 273 274 if ((rs->chip & (R92C_CHIP_UMC_A_CUT | R92C_CHIP_92C)) == 275 R92C_CHIP_UMC_A_CUT) { 276 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 277 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 278 } 279 280 /* Turn CCK and OFDM blocks on. */ 281 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN); 282 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN); 283 } 284 285 void 286 r92c_init_edca(struct rtwn_softc *sc) 287 { 288 /* SIFS */ 289 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 290 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 291 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 292 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 293 /* TXOP */ 294 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 295 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 296 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 297 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 298 } 299 300 void 301 r92c_init_ampdu(struct rtwn_softc *sc) 302 { 303 304 /* Setup AMPDU aggregation. */ 305 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 306 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 307 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 308 } 309 310 void 311 r92c_init_antsel(struct rtwn_softc *sc) 312 { 313 uint32_t reg; 314 315 if (sc->ntxchains != 1 || sc->nrxchains != 1) 316 return; 317 318 rtwn_setbits_1(sc, R92C_LEDCFG2, 0, 0x80); 319 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); 320 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 321 sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); /* XXX */ 322 rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0); 323 } 324 325 void 326 r92c_pa_bias_init(struct rtwn_softc *sc) 327 { 328 struct r92c_softc *rs = sc->sc_priv; 329 int i; 330 331 for (i = 0; i < sc->nrxchains; i++) { 332 if (rs->pa_setting & (1 << i)) 333 continue; 334 r92c_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 335 r92c_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 336 r92c_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 337 r92c_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 338 } 339 if (!(rs->pa_setting & 0x10)) 340 rtwn_setbits_1(sc, 0x16, 0xf0, 0x90); 341 } 342