1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 #include "opt_wlan.h" 25 26 #include <sys/param.h> 27 #include <sys/lock.h> 28 #include <sys/mutex.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/linker.h> 39 40 #include <net/if.h> 41 #include <net/ethernet.h> 42 #include <net/if_media.h> 43 44 #include <net80211/ieee80211_var.h> 45 #include <net80211/ieee80211_radiotap.h> 46 47 #include <dev/rtwn/if_rtwnreg.h> 48 #include <dev/rtwn/if_rtwnvar.h> 49 #include <dev/rtwn/if_rtwn_debug.h> 50 51 #include <dev/rtwn/rtl8192c/r92c.h> 52 #include <dev/rtwn/rtl8192c/r92c_priv.h> 53 #include <dev/rtwn/rtl8192c/r92c_reg.h> 54 #include <dev/rtwn/rtl8192c/r92c_var.h> 55 56 57 int 58 r92c_check_condition(struct rtwn_softc *sc, const uint8_t cond[]) 59 { 60 struct r92c_softc *rs = sc->sc_priv; 61 uint8_t mask; 62 int i; 63 64 if (cond[0] == 0) 65 return (1); 66 67 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 68 "%s: condition byte 0: %02X; chip %02X, board %02X\n", 69 __func__, cond[0], rs->chip, rs->board_type); 70 71 if (!(rs->chip & R92C_CHIP_92C)) { 72 if (rs->board_type == R92C_BOARD_TYPE_HIGHPA) 73 mask = R92C_COND_RTL8188RU; 74 else if (rs->board_type == R92C_BOARD_TYPE_MINICARD) 75 mask = R92C_COND_RTL8188CE; 76 else 77 mask = R92C_COND_RTL8188CU; 78 } else { 79 if (rs->board_type == R92C_BOARD_TYPE_MINICARD) 80 mask = R92C_COND_RTL8192CE; 81 else 82 mask = R92C_COND_RTL8192CU; 83 } 84 85 for (i = 0; i < RTWN_MAX_CONDITIONS && cond[i] != 0; i++) 86 if ((cond[i] & mask) == mask) 87 return (1); 88 89 return (0); 90 } 91 92 int 93 r92c_llt_init(struct rtwn_softc *sc) 94 { 95 int i, error; 96 97 /* Reserve pages [0; page_count]. */ 98 for (i = 0; i < sc->page_count; i++) { 99 if ((error = r92c_llt_write(sc, i, i + 1)) != 0) 100 return (error); 101 } 102 /* NB: 0xff indicates end-of-list. */ 103 if ((error = r92c_llt_write(sc, i, 0xff)) != 0) 104 return (error); 105 /* 106 * Use pages [page_count + 1; pktbuf_count - 1] 107 * as ring buffer. 108 */ 109 for (++i; i < sc->pktbuf_count - 1; i++) { 110 if ((error = r92c_llt_write(sc, i, i + 1)) != 0) 111 return (error); 112 } 113 /* Make the last page point to the beginning of the ring buffer. */ 114 error = r92c_llt_write(sc, i, sc->page_count + 1); 115 return (error); 116 } 117 118 int 119 r92c_set_page_size(struct rtwn_softc *sc) 120 { 121 return (rtwn_write_1(sc, R92C_PBP, SM(R92C_PBP_PSRX, R92C_PBP_128) | 122 SM(R92C_PBP_PSTX, R92C_PBP_128)) == 0); 123 } 124 125 void 126 r92c_init_bb_common(struct rtwn_softc *sc) 127 { 128 struct r92c_softc *rs = sc->sc_priv; 129 int i, j; 130 131 /* Write BB initialization values. */ 132 for (i = 0; i < sc->bb_size; i++) { 133 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; 134 135 while (!rtwn_check_condition(sc, bb_prog->cond)) { 136 KASSERT(bb_prog->next != NULL, 137 ("%s: wrong condition value (i %d)\n", 138 __func__, i)); 139 bb_prog = bb_prog->next; 140 } 141 142 for (j = 0; j < bb_prog->count; j++) { 143 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 144 "BB: reg 0x%03x, val 0x%08x\n", 145 bb_prog->reg[j], bb_prog->val[j]); 146 147 rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); 148 rtwn_delay(sc, 1); 149 } 150 } 151 152 if (rs->chip & R92C_CHIP_92C_1T2R) { 153 /* 8192C 1T only configuration. */ 154 rtwn_bb_setbits(sc, R92C_FPGA0_TXINFO, 0x03, 0x02); 155 rtwn_bb_setbits(sc, R92C_FPGA1_TXINFO, 0x300033, 0x200022); 156 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0xff000000, 157 0x45000000); 158 rtwn_bb_setbits(sc, R92C_OFDM0_TRXPATHENA, 0xff, 0x23); 159 rtwn_bb_setbits(sc, R92C_OFDM0_AGCPARAM1, 0x30, 0x10); 160 161 rtwn_bb_setbits(sc, 0xe74, 0x0c000000, 0x08000000); 162 rtwn_bb_setbits(sc, 0xe78, 0x0c000000, 0x08000000); 163 rtwn_bb_setbits(sc, 0xe7c, 0x0c000000, 0x08000000); 164 rtwn_bb_setbits(sc, 0xe80, 0x0c000000, 0x08000000); 165 rtwn_bb_setbits(sc, 0xe88, 0x0c000000, 0x08000000); 166 } 167 168 /* Write AGC values. */ 169 for (i = 0; i < sc->agc_size; i++) { 170 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; 171 172 while (!rtwn_check_condition(sc, agc_prog->cond)) { 173 KASSERT(agc_prog->next != NULL, 174 ("%s: wrong condition value (2) (i %d)\n", 175 __func__, i)); 176 agc_prog = agc_prog->next; 177 } 178 179 for (j = 0; j < agc_prog->count; j++) { 180 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 181 "AGC: val 0x%08x\n", agc_prog->val[j]); 182 183 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 184 agc_prog->val[j]); 185 rtwn_delay(sc, 1); 186 } 187 } 188 189 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 190 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 191 } 192 193 int 194 r92c_init_rf_chain(struct rtwn_softc *sc, 195 const struct rtwn_rf_prog *rf_prog, int chain) 196 { 197 int i, j; 198 199 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, "%s: chain %d\n", 200 __func__, chain); 201 202 for (i = 0; rf_prog[i].reg != NULL; i++) { 203 const struct rtwn_rf_prog *prog = &rf_prog[i]; 204 205 while (!rtwn_check_condition(sc, prog->cond)) { 206 KASSERT(prog->next != NULL, 207 ("%s: wrong condition value (i %d)\n", 208 __func__, i)); 209 prog = prog->next; 210 } 211 212 for (j = 0; j < prog->count; j++) { 213 RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, 214 "RF: reg 0x%02x, val 0x%05x\n", 215 prog->reg[j], prog->val[j]); 216 217 /* 218 * These are fake RF registers offsets that 219 * indicate a delay is required. 220 */ 221 /* NB: we are using 'value' to store required delay. */ 222 if (prog->reg[j] > 0xf8) { 223 rtwn_delay(sc, prog->val[j]); 224 continue; 225 } 226 227 rtwn_rf_write(sc, chain, prog->reg[j], prog->val[j]); 228 rtwn_delay(sc, 1); 229 } 230 } 231 232 return (i); 233 } 234 235 void 236 r92c_init_rf(struct rtwn_softc *sc) 237 { 238 struct r92c_softc *rs = sc->sc_priv; 239 uint32_t reg, type; 240 int i, chain, idx, off; 241 242 for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) { 243 /* Save RF_ENV control type. */ 244 idx = chain / 2; 245 off = (chain % 2) * 16; 246 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 247 type = (reg >> off) & 0x10; 248 249 /* Set RF_ENV enable. */ 250 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 251 0, 0x100000); 252 rtwn_delay(sc, 1); 253 /* Set RF_ENV output high. */ 254 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain), 255 0, 0x10); 256 rtwn_delay(sc, 1); 257 /* Set address and data lengths of RF registers. */ 258 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 259 R92C_HSSI_PARAM2_ADDR_LENGTH, 0); 260 rtwn_delay(sc, 1); 261 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain), 262 R92C_HSSI_PARAM2_DATA_LENGTH, 0); 263 rtwn_delay(sc, 1); 264 265 /* Write RF initialization values for this chain. */ 266 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain); 267 268 /* Restore RF_ENV control type. */ 269 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(idx), 270 0x10 << off, type << off); 271 272 /* Cache RF register CHNLBW. */ 273 rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, 274 R92C_RF_CHNLBW); 275 } 276 277 if ((rs->chip & (R92C_CHIP_UMC_A_CUT | R92C_CHIP_92C)) == 278 R92C_CHIP_UMC_A_CUT) { 279 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 280 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 281 } 282 283 /* Turn CCK and OFDM blocks on. */ 284 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN); 285 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN); 286 } 287 288 void 289 r92c_init_edca(struct rtwn_softc *sc) 290 { 291 /* SIFS */ 292 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 293 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 294 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 295 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 296 /* TXOP */ 297 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 298 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 299 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 300 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 301 } 302 303 void 304 r92c_init_ampdu(struct rtwn_softc *sc) 305 { 306 307 /* Setup AMPDU aggregation. */ 308 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 309 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 310 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 311 } 312 313 void 314 r92c_init_antsel(struct rtwn_softc *sc) 315 { 316 uint32_t reg; 317 318 if (sc->ntxchains != 1 || sc->nrxchains != 1) 319 return; 320 321 rtwn_setbits_1(sc, R92C_LEDCFG2, 0, 0x80); 322 rtwn_bb_setbits(sc, R92C_FPGA0_RFPARAM(0), 0, 0x2000); 323 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 324 sc->sc_ant = MS(reg, R92C_FPGA0_RFIFACEOE0_ANT); /* XXX */ 325 } 326 327 void 328 r92c_pa_bias_init(struct rtwn_softc *sc) 329 { 330 struct r92c_softc *rs = sc->sc_priv; 331 int i; 332 333 for (i = 0; i < sc->nrxchains; i++) { 334 if (rs->pa_setting & (1 << i)) 335 continue; 336 r92c_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 337 r92c_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 338 r92c_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 339 r92c_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 340 } 341 if (!(rs->pa_setting & 0x10)) 342 rtwn_setbits_1(sc, 0x16, 0xf0, 0x90); 343 } 344