1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 #include "opt_wlan.h" 23 24 #include <sys/param.h> 25 #include <sys/lock.h> 26 #include <sys/mutex.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/queue.h> 33 #include <sys/taskqueue.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/linker.h> 37 38 #include <net/if.h> 39 #include <net/ethernet.h> 40 #include <net/if_media.h> 41 42 #include <net80211/ieee80211_var.h> 43 #include <net80211/ieee80211_radiotap.h> 44 45 #include <dev/rtwn/if_rtwnreg.h> 46 #include <dev/rtwn/if_rtwnvar.h> 47 48 #include <dev/rtwn/if_rtwn_debug.h> 49 #include <dev/rtwn/if_rtwn_ridx.h> 50 51 #include <dev/rtwn/rtl8192c/r92c.h> 52 #include <dev/rtwn/rtl8192c/r92c_priv.h> 53 #include <dev/rtwn/rtl8192c/r92c_reg.h> 54 #include <dev/rtwn/rtl8192c/r92c_var.h> 55 56 void 57 r92c_dump_txpower(struct rtwn_softc *sc, int chain, 58 uint8_t power[RTWN_RIDX_COUNT]) 59 { 60 61 #ifdef RTWN_DEBUG 62 if (sc->sc_debug & RTWN_DEBUG_TXPWR) { 63 int i; 64 65 /* Print CCK */ 66 RTWN_DPRINTF(sc, RTWN_DEBUG_TXPWR, 67 "TX [%d]: CCK: 1M: %d 2M: %d 5.5M: %d 11M: %d\n", 68 chain, 69 power[RTWN_RIDX_CCK1], 70 power[RTWN_RIDX_CCK2], 71 power[RTWN_RIDX_CCK55], 72 power[RTWN_RIDX_CCK11]); 73 /* Print OFDM */ 74 RTWN_DPRINTF(sc, RTWN_DEBUG_TXPWR, 75 "TX [%d]: OFDM: 6M: %d 9M: %d 12M: %d 18M: %d 24M: %d " 76 "36M: %d 48M: %d 54M: %d\n", 77 chain, 78 power[RTWN_RIDX_OFDM6], 79 power[RTWN_RIDX_OFDM9], 80 power[RTWN_RIDX_OFDM12], 81 power[RTWN_RIDX_OFDM18], 82 power[RTWN_RIDX_OFDM24], 83 power[RTWN_RIDX_OFDM36], 84 power[RTWN_RIDX_OFDM48], 85 power[RTWN_RIDX_OFDM54]); 86 /* Print HT, 1 and 2 stream */ 87 for (i = 0; i < sc->ntxchains; i++) { 88 RTWN_DPRINTF(sc, RTWN_DEBUG_TXPWR, 89 "TX [%d]: MCS%d-%d: %d %d %d %d %d %d %d %d\n", 90 chain, 91 i * 8, 92 i * 8 + 7, 93 power[RTWN_RIDX_HT_MCS(i * 8 + 0)], 94 power[RTWN_RIDX_HT_MCS(i * 8 + 1)], 95 power[RTWN_RIDX_HT_MCS(i * 8 + 2)], 96 power[RTWN_RIDX_HT_MCS(i * 8 + 3)], 97 power[RTWN_RIDX_HT_MCS(i * 8 + 4)], 98 power[RTWN_RIDX_HT_MCS(i * 8 + 5)], 99 power[RTWN_RIDX_HT_MCS(i * 8 + 6)], 100 power[RTWN_RIDX_HT_MCS(i * 8 + 7)]); 101 } 102 } 103 #endif 104 } 105 106 static int 107 r92c_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c) 108 { 109 uint8_t chan; 110 int group; 111 112 chan = rtwn_chan2centieee(c); 113 if (IEEE80211_IS_CHAN_2GHZ(c)) { 114 if (chan <= 3) group = 0; 115 else if (chan <= 9) group = 1; 116 else if (chan <= 14) group = 2; 117 else { 118 KASSERT(0, ("wrong 2GHz channel %d!\n", chan)); 119 return (-1); 120 } 121 } else { 122 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags)); 123 return (-1); 124 } 125 126 return (group); 127 } 128 129 /* XXX recheck */ 130 void 131 r92c_get_txpower(struct rtwn_softc *sc, int chain, 132 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT]) 133 { 134 const struct ieee80211com *ic = &sc->sc_ic; 135 struct r92c_softc *rs = sc->sc_priv; 136 struct rtwn_r92c_txpwr *rt = rs->rs_txpwr; 137 const struct rtwn_r92c_txagc *base = rs->rs_txagc; 138 uint8_t ofdmpow, htpow, diff, max; 139 int max_mcs, ridx, group; 140 141 /* Determine channel group. */ 142 group = r92c_get_power_group(sc, c); 143 if (group == -1) { /* shouldn't happen */ 144 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__); 145 return; 146 } 147 148 /* 149 * Treat the entries in 1/2 dBm resolution where 0 = 0dBm. 150 * Apply the adjustments afterwards; assume that the vendor 151 * driver is applying offsets to make up for the actual 152 * target power in dBm. 153 */ 154 155 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1); 156 KASSERT(max_mcs <= RTWN_RIDX_LEGACY_HT_COUNT, ("increase ridx limit\n")); 157 158 if (rs->regulatory == 0) { 159 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 160 power[ridx] = base[chain].pwr[0][ridx]; 161 } 162 for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_LEGACY_HT_COUNT; ridx++) { 163 if (rs->regulatory == 3) { 164 power[ridx] = base[chain].pwr[0][ridx]; 165 /* Apply vendor limits. */ 166 if (IEEE80211_IS_CHAN_HT40(c)) 167 max = rt->ht40_max_pwr[chain][group]; 168 else 169 max = rt->ht20_max_pwr[chain][group]; 170 if (power[ridx] > max) 171 power[ridx] = max; 172 } else if (rs->regulatory == 1) { 173 if (!IEEE80211_IS_CHAN_HT40(c)) 174 power[ridx] = base[chain].pwr[group][ridx]; 175 } else if (rs->regulatory != 2) 176 power[ridx] = base[chain].pwr[0][ridx]; 177 } 178 179 /* Compute per-CCK rate Tx power. */ 180 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 181 power[ridx] += rt->cck_tx_pwr[chain][group]; 182 183 htpow = rt->ht40_1s_tx_pwr[chain][group]; 184 if (sc->ntxchains > 1) { 185 /* Apply reduction for 2 spatial streams. */ 186 diff = rt->ht40_2s_tx_pwr_diff[chain][group]; 187 htpow = (htpow > diff) ? htpow - diff : 0; 188 } 189 190 /* Compute per-OFDM rate Tx power. */ 191 diff = rt->ofdm_tx_pwr_diff[chain][group]; 192 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 193 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) 194 power[ridx] += ofdmpow; 195 196 /* Compute per-MCS Tx power. */ 197 if (!IEEE80211_IS_CHAN_HT40(c)) { 198 diff = rt->ht20_tx_pwr_diff[chain][group]; 199 htpow += diff; /* HT40->HT20 correction. */ 200 } 201 for (ridx = RTWN_RIDX_HT_MCS(0); ridx <= max_mcs; ridx++) 202 power[ridx] += htpow; 203 204 /* Apply max limit. */ 205 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) { 206 if (power[ridx] > R92C_MAX_TX_PWR) 207 power[ridx] = R92C_MAX_TX_PWR; 208 /* Apply net80211 limits */ 209 if (power[ridx] > ic->ic_txpowlimit) 210 power[ridx] = ic->ic_txpowlimit; 211 212 } 213 } 214 215 void 216 r92c_write_txpower(struct rtwn_softc *sc, int chain, 217 uint8_t power[RTWN_RIDX_COUNT]) 218 { 219 uint32_t reg; 220 221 /* Write per-CCK rate Tx power. */ 222 if (chain == 0) { 223 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 224 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]); 225 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 226 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 227 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]); 228 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]); 229 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]); 230 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 231 } else { 232 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 233 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]); 234 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]); 235 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]); 236 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 237 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 238 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]); 239 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 240 } 241 /* Write per-OFDM rate Tx power. */ 242 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 243 SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) | 244 SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) | 245 SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) | 246 SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18])); 247 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 248 SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) | 249 SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) | 250 SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) | 251 SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54])); 252 /* Write per-MCS Tx power. */ 253 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 254 SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_HT_MCS(0)]) | 255 SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_HT_MCS(1)]) | 256 SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_HT_MCS(2)]) | 257 SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_HT_MCS(3)])); 258 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 259 SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_HT_MCS(4)]) | 260 SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_HT_MCS(5)]) | 261 SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_HT_MCS(6)]) | 262 SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_HT_MCS(7)])); 263 if (sc->ntxchains >= 2) { 264 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 265 SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_HT_MCS(8)]) | 266 SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_HT_MCS(9)]) | 267 SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) | 268 SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)])); 269 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 270 SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) | 271 SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) | 272 SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) | 273 SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)])); 274 } 275 } 276 277 static void 278 r92c_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c) 279 { 280 uint8_t power[RTWN_RIDX_COUNT]; 281 int i; 282 283 for (i = 0; i < sc->ntxchains; i++) { 284 memset(power, 0, sizeof(power)); 285 /* Compute per-rate Tx power values. */ 286 rtwn_r92c_get_txpower(sc, i, c, power); 287 /* Optionally print out the power table */ 288 r92c_dump_txpower(sc, i, power); 289 /* Write per-rate Tx power values to hardware. */ 290 r92c_write_txpower(sc, i, power); 291 } 292 } 293 294 /* 295 * Only reconfigure the transmit power if there's a valid BSS node and 296 * channel. Otherwise just let the next call to r92c_set_chan() 297 * configure the transmit power. 298 */ 299 int 300 r92c_set_tx_power(struct rtwn_softc *sc, struct ieee80211vap *vap) 301 { 302 if (vap->iv_bss == NULL) 303 return (EINVAL); 304 if (vap->iv_bss->ni_chan == IEEE80211_CHAN_ANYC) 305 return (EINVAL); 306 307 /* Set it for the current channel */ 308 r92c_set_txpower(sc, vap->iv_bss->ni_chan); 309 310 return (0); 311 } 312 313 static void 314 r92c_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo) 315 { 316 struct r92c_softc *rs = sc->sc_priv; 317 318 rtwn_setbits_1(sc, R92C_BWOPMODE, R92C_BWOPMODE_20MHZ, 0); 319 rtwn_setbits_1(sc, R92C_RRSR + 2, 0x6f, (prichlo ? 1 : 2) << 5); 320 321 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ); 322 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ); 323 324 /* Set CCK side band. */ 325 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 326 (prichlo ? 0 : 1) << 4); 327 328 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, 329 (prichlo ? 1 : 2) << 10); 330 331 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 332 R92C_FPGA0_ANAPARAM2_CBW20, 0); 333 334 rtwn_bb_setbits(sc, R92C_FPGA0_POWER_SAVE, 335 R92C_FPGA0_POWER_SAVE_PS_MASK, (prichlo ? 2 : 1) << 26); 336 337 /* Select 40MHz bandwidth. */ 338 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 339 (rs->rf_chnlbw[0] & ~0xfff) | chan); 340 } 341 342 void 343 r92c_set_bw20(struct rtwn_softc *sc, uint8_t chan) 344 { 345 struct r92c_softc *rs = sc->sc_priv; 346 347 rtwn_setbits_1(sc, R92C_BWOPMODE, 0, R92C_BWOPMODE_20MHZ); 348 349 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0); 350 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0); 351 352 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 0, 353 R92C_FPGA0_ANAPARAM2_CBW20); 354 355 /* Select 20MHz bandwidth. */ 356 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 357 (rs->rf_chnlbw[0] & ~0xfff) | chan | R92C_RF_CHNLBW_BW20); 358 } 359 360 void 361 r92c_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c) 362 { 363 struct r92c_softc *rs = sc->sc_priv; 364 u_int chan; 365 int i; 366 367 chan = rtwn_chan2centieee(c); 368 369 /* Set Tx power for this new channel. */ 370 r92c_set_txpower(sc, c); 371 372 for (i = 0; i < sc->nrxchains; i++) { 373 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 374 RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 375 } 376 if (IEEE80211_IS_CHAN_HT40(c)) 377 r92c_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c)); 378 else 379 rtwn_r92c_set_bw20(sc, chan); 380 } 381 382 void 383 r92c_set_gain(struct rtwn_softc *sc, uint8_t gain) 384 { 385 386 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0), 387 R92C_OFDM0_AGCCORE1_GAIN_M, gain); 388 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(1), 389 R92C_OFDM0_AGCCORE1_GAIN_M, gain); 390 } 391 392 void 393 r92c_scan_start(struct ieee80211com *ic) 394 { 395 struct rtwn_softc *sc = ic->ic_softc; 396 struct r92c_softc *rs = sc->sc_priv; 397 398 RTWN_LOCK(sc); 399 /* Set gain for scanning. */ 400 rtwn_r92c_set_gain(sc, 0x20); 401 RTWN_UNLOCK(sc); 402 403 rs->rs_scan_start(ic); 404 } 405 406 void 407 r92c_scan_end(struct ieee80211com *ic) 408 { 409 struct rtwn_softc *sc = ic->ic_softc; 410 struct r92c_softc *rs = sc->sc_priv; 411 412 RTWN_LOCK(sc); 413 /* Set gain under link. */ 414 rtwn_r92c_set_gain(sc, 0x32); 415 RTWN_UNLOCK(sc); 416 417 rs->rs_scan_end(ic); 418 } 419