1 /* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 #include "opt_wlan.h" 25 26 #include <sys/param.h> 27 #include <sys/lock.h> 28 #include <sys/mutex.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/linker.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/rman.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnvar.h> 52 53 #include <dev/rtwn/pci/rtwn_pci_var.h> 54 55 #include <dev/rtwn/rtl8192c/r92c_var.h> 56 57 #include <dev/rtwn/rtl8192c/pci/r92ce.h> 58 #include <dev/rtwn/rtl8192c/pci/r92ce_reg.h> 59 60 61 void 62 r92ce_init_intr(struct rtwn_softc *sc) 63 { 64 /* Disable interrupts. */ 65 rtwn_write_4(sc, R92C_HISR, 0x00000000); 66 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 67 } 68 69 void 70 r92ce_init_edca(struct rtwn_softc *sc) 71 { 72 /* SIFS */ 73 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 74 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 75 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 76 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 77 /* TXOP */ 78 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 79 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 80 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 81 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 82 } 83 84 void 85 r92ce_init_bb(struct rtwn_softc *sc) 86 { 87 88 /* Enable BB and RF. */ 89 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0, 90 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 91 R92C_SYS_FUNC_EN_DIO_RF); 92 93 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 94 95 rtwn_write_1(sc, R92C_RF_CTRL, 96 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 97 98 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 99 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 100 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 101 R92C_SYS_FUNC_EN_BBRSTB); 102 103 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 104 105 rtwn_setbits_4(sc, R92C_LEDCFG0, 0, 0x00800000); 106 107 r92c_init_bb_common(sc); 108 109 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 110 R92C_HSSI_PARAM2_CCK_HIPWR) 111 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 112 } 113 114 int 115 r92ce_power_on(struct rtwn_softc *sc) 116 { 117 struct r92c_softc *rs = sc->sc_priv; 118 uint32_t reg; 119 int ntries; 120 121 /* Wait for autoload done bit. */ 122 for (ntries = 0; ntries < 1000; ntries++) { 123 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 124 break; 125 DELAY(5); 126 } 127 if (ntries == 1000) { 128 device_printf(sc->sc_dev, 129 "timeout waiting for chip autoload\n"); 130 return (ETIMEDOUT); 131 } 132 133 /* Unlock ISO/CLK/Power control register. */ 134 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 135 136 if (rs->board_type != R92C_BOARD_TYPE_DONGLE) { 137 /* bt coex */ 138 rtwn_setbits_4(sc, R92C_APS_FSMCO, 0, 139 R92C_APS_FSMCO_SOP_ABG | 140 R92C_APS_FSMCO_SOP_AMB | 141 R92C_APS_FSMCO_XOP_BTCK); 142 } 143 144 /* Move SPS into PWM mode. */ 145 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 146 147 /* Set low byte to 0x0f, leave others unchanged. */ 148 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0f); 149 150 /* TODO: check if we need this for 8188CE */ 151 if (rs->board_type != R92C_BOARD_TYPE_DONGLE) { 152 /* bt coex */ 153 /* XXX magic from linux */ 154 rtwn_setbits_4(sc, R92C_AFE_XTAL_CTRL, 0x024800, 0); 155 } 156 157 rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, 0xff00, 158 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 159 160 DELAY(200); 161 162 /* TODO: linux does additional btcoex stuff here */ 163 164 /* Auto enable WLAN. */ 165 rtwn_setbits_2(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_ONMAC); 166 for (ntries = 0; ntries < 1000; ntries++) { 167 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 168 R92C_APS_FSMCO_APFM_ONMAC)) 169 break; 170 DELAY(5); 171 } 172 if (ntries == 1000) { 173 device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n"); 174 return (ETIMEDOUT); 175 } 176 177 /* Enable radio, GPIO and LED functions. */ 178 rtwn_write_2(sc, R92C_APS_FSMCO, 179 R92C_APS_FSMCO_AFSM_PCIE | 180 R92C_APS_FSMCO_PDN_EN | 181 R92C_APS_FSMCO_PFM_ALDN); 182 /* Release RF digital isolation. */ 183 rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, R92C_SYS_ISO_CTRL_DIOR, 0); 184 185 if (rs->chip & R92C_CHIP_92C) 186 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 187 else 188 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 189 190 rtwn_write_4(sc, R92C_INT_MIG, 0); 191 192 if (rs->board_type != R92C_BOARD_TYPE_DONGLE) { 193 /* bt coex */ 194 /* XXX magic from linux */ 195 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0x02, 0); 196 } 197 198 rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_RFKILL, 0); 199 200 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 201 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 202 device_printf(sc->sc_dev, 203 "radio is disabled by hardware switch\n"); 204 /* XXX how driver will know when radio will be enabled? */ 205 return (EPERM); 206 } 207 208 /* Initialize MAC. */ 209 rtwn_setbits_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF, 0); 210 for (ntries = 0; ntries < 200; ntries++) { 211 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 212 R92C_APSD_CTRL_OFF_STATUS)) 213 break; 214 DELAY(500); 215 } 216 if (ntries == 200) { 217 device_printf(sc->sc_dev, 218 "timeout waiting for MAC initialization\n"); 219 return (ETIMEDOUT); 220 } 221 222 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 223 rtwn_setbits_2(sc, R92C_CR, 0, 224 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 225 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 226 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 227 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0)); 228 229 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 230 231 return (0); 232 } 233 234 void 235 r92ce_power_off(struct rtwn_softc *sc) 236 { 237 #ifndef RTWN_WITHOUT_UCODE 238 struct r92c_softc *rs = sc->sc_priv; 239 240 /* Deinit C2H event handler. */ 241 callout_stop(&rs->rs_c2h_report); 242 rs->rs_c2h_paused = 0; 243 rs->rs_c2h_pending = 0; 244 rs->rs_c2h_timeout = hz; 245 #endif 246 247 /* Stop hardware. */ 248 /* Disable interrupts. */ 249 rtwn_write_4(sc, R92C_HISR, 0); 250 rtwn_write_4(sc, R92C_HIMR, 0); 251 252 /* Stop hardware. */ 253 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 254 255 /* Turn off RF. */ 256 rtwn_write_1(sc, R92C_RF_CTRL, 0); 257 258 /* Reset BB state machine */ 259 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_BB_GLB_RST); 260 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0); 261 262 /* Disable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 263 rtwn_setbits_2(sc, R92C_CR, 264 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 265 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 266 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 267 R92C_CR_ENSEC, 268 0); 269 270 /* If firmware in ram code, do reset. */ 271 #ifndef RTWN_WITHOUT_UCODE 272 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 273 r92ce_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN); 274 #endif 275 276 /* TODO: linux does additional btcoex stuff here */ 277 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 278 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 279 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 280 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 281 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 282 } 283 284 void 285 r92ce_init_ampdu(struct rtwn_softc *sc) 286 { 287 288 /* Setup AMPDU aggregation. */ 289 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 290 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 291 } 292 293 void 294 r92ce_post_init(struct rtwn_softc *sc) 295 { 296 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 297 0x1f00 | R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 298 299 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 300 301 /* Perform LO and IQ calibrations. */ 302 r92ce_iq_calib(sc); 303 /* Perform LC calibration. */ 304 r92c_lc_calib(sc); 305 306 r92c_pa_bias_init(sc); 307 308 /* Fix for lower temperature. */ 309 rtwn_write_1(sc, 0x15, 0xe9); 310 311 #ifndef RTWN_WITHOUT_UCODE 312 if (sc->sc_flags & RTWN_FW_LOADED) { 313 struct r92c_softc *rs = sc->sc_priv; 314 315 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) { 316 /* XXX TODO: fix (see comment in r92cu_init.c) */ 317 sc->sc_ratectl = RTWN_RATECTL_NET80211; 318 } else 319 sc->sc_ratectl = sc->sc_ratectl_sysctl; 320 321 /* Start C2H event handling. */ 322 callout_reset(&rs->rs_c2h_report, rs->rs_c2h_timeout, 323 r92c_handle_c2h_report, sc); 324 } else 325 #endif 326 sc->sc_ratectl = RTWN_RATECTL_NONE; 327 } 328