1 /* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __FBSDID("$FreeBSD$"); 23 24 #include "opt_wlan.h" 25 26 #include <sys/param.h> 27 #include <sys/lock.h> 28 #include <sys/mutex.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/linker.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/rman.h> 43 44 #include <net/if.h> 45 #include <net/ethernet.h> 46 #include <net/if_media.h> 47 48 #include <net80211/ieee80211_var.h> 49 #include <net80211/ieee80211_radiotap.h> 50 51 #include <dev/rtwn/if_rtwnreg.h> 52 #include <dev/rtwn/if_rtwnvar.h> 53 #include <dev/rtwn/if_rtwn_debug.h> 54 55 #include <dev/rtwn/pci/rtwn_pci_var.h> 56 57 #include <dev/rtwn/rtl8192c/pci/r92ce.h> 58 #include <dev/rtwn/rtl8192c/pci/r92ce_reg.h> 59 60 61 /* Registers to save and restore during IQ calibration. */ 62 struct r92ce_iq_cal_reg_vals { 63 uint32_t adda[16]; 64 uint8_t txpause; 65 uint8_t bcn_ctrl[2]; 66 uint32_t gpio_muxcfg; 67 uint32_t ofdm0_trxpathena; 68 uint32_t ofdm0_trmuxpar; 69 uint32_t fpga0_rfifacesw1; 70 }; 71 72 /* XXX 92CU? */ 73 static int 74 r92ce_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 75 uint16_t rx[2]) 76 { 77 uint32_t status; 78 int offset = chain * 0x20; 79 80 if (chain == 0) { /* IQ calibration for chain 0. */ 81 /* IQ calibration settings for chain 0. */ 82 rtwn_bb_write(sc, 0xe30, 0x10008c1f); 83 rtwn_bb_write(sc, 0xe34, 0x10008c1f); 84 rtwn_bb_write(sc, 0xe38, 0x82140102); 85 86 if (sc->ntxchains > 1) { 87 rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */ 88 /* IQ calibration settings for chain 1. */ 89 rtwn_bb_write(sc, 0xe50, 0x10008c22); 90 rtwn_bb_write(sc, 0xe54, 0x10008c22); 91 rtwn_bb_write(sc, 0xe58, 0x82140102); 92 rtwn_bb_write(sc, 0xe5c, 0x28160202); 93 } else 94 rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */ 95 96 /* LO calibration settings. */ 97 rtwn_bb_write(sc, 0xe4c, 0x001028d1); 98 /* We're doing LO and IQ calibration in one shot. */ 99 rtwn_bb_write(sc, 0xe48, 0xf9000000); 100 rtwn_bb_write(sc, 0xe48, 0xf8000000); 101 102 } else { /* IQ calibration for chain 1. */ 103 /* We're doing LO and IQ calibration in one shot. */ 104 rtwn_bb_write(sc, 0xe60, 0x00000002); 105 rtwn_bb_write(sc, 0xe60, 0x00000000); 106 } 107 108 /* Give LO and IQ calibrations the time to complete. */ 109 rtwn_delay(sc, 1000); 110 111 /* Read IQ calibration status. */ 112 status = rtwn_bb_read(sc, 0xeac); 113 114 if (status & (1 << (28 + chain * 3))) 115 return (0); /* Tx failed. */ 116 /* Read Tx IQ calibration results. */ 117 tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff; 118 tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff; 119 if (tx[0] == 0x142 || tx[1] == 0x042) 120 return (0); /* Tx failed. */ 121 122 if (status & (1 << (27 + chain * 3))) 123 return (1); /* Rx failed. */ 124 /* Read Rx IQ calibration results. */ 125 rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff; 126 rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff; 127 if (rx[0] == 0x132 || rx[1] == 0x036) 128 return (1); /* Rx failed. */ 129 130 return (3); /* Both Tx and Rx succeeded. */ 131 } 132 133 static void 134 r92ce_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 135 uint16_t rx[2][2], struct r92ce_iq_cal_reg_vals *vals) 136 { 137 /* Registers to save and restore during IQ calibration. */ 138 static const uint16_t reg_adda[16] = { 139 0x85c, 0xe6c, 0xe70, 0xe74, 140 0xe78, 0xe7c, 0xe80, 0xe84, 141 0xe88, 0xe8c, 0xed0, 0xed4, 142 0xed8, 0xedc, 0xee0, 0xeec 143 }; 144 int i, chain; 145 uint32_t hssi_param1; 146 147 if (n == 0) { 148 for (i = 0; i < nitems(reg_adda); i++) 149 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]); 150 151 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE); 152 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0)); 153 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1)); 154 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 155 } 156 157 if (sc->ntxchains == 1) { 158 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 159 for (i = 1; i < nitems(reg_adda); i++) 160 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 161 } else { 162 for (i = 0; i < nitems(reg_adda); i++) 163 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 164 } 165 166 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 167 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 168 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 169 hssi_param1 | R92C_HSSI_PARAM1_PI); 170 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 171 hssi_param1 | R92C_HSSI_PARAM1_PI); 172 } 173 174 if (n == 0) { 175 vals->ofdm0_trxpathena = 176 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 177 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 178 vals->fpga0_rfifacesw1 = 179 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 180 } 181 182 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 183 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 184 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 185 if (sc->ntxchains > 1) { 186 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 187 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 188 } 189 190 rtwn_write_1(sc, R92C_TXPAUSE, 191 R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH); 192 rtwn_write_1(sc, R92C_BCN_CTRL(0), 193 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN); 194 rtwn_write_1(sc, R92C_BCN_CTRL(1), 195 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN); 196 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 197 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT); 198 199 rtwn_bb_write(sc, 0x0b68, 0x00080000); 200 if (sc->ntxchains > 1) 201 rtwn_bb_write(sc, 0x0b6c, 0x00080000); 202 203 rtwn_bb_write(sc, 0x0e28, 0x80800000); 204 rtwn_bb_write(sc, 0x0e40, 0x01007c00); 205 rtwn_bb_write(sc, 0x0e44, 0x01004800); 206 207 rtwn_bb_write(sc, 0x0b68, 0x00080000); 208 209 for (chain = 0; chain < sc->ntxchains; chain++) { 210 if (chain > 0) { 211 /* Put chain 0 on standby. */ 212 rtwn_bb_write(sc, 0x0e28, 0x00); 213 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 214 rtwn_bb_write(sc, 0x0e28, 0x80800000); 215 216 /* Enable chain 1. */ 217 for (i = 0; i < nitems(reg_adda); i++) 218 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 219 } 220 221 /* Run IQ calibration twice. */ 222 for (i = 0; i < 2; i++) { 223 int ret; 224 225 ret = r92ce_iq_calib_chain(sc, chain, 226 tx[chain], rx[chain]); 227 if (ret == 0) { 228 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 229 "%s: chain %d: Tx failed.\n", 230 __func__, chain); 231 tx[chain][0] = 0xff; 232 tx[chain][1] = 0xff; 233 rx[chain][0] = 0xff; 234 rx[chain][1] = 0xff; 235 } else if (ret == 1) { 236 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 237 "%s: chain %d: Rx failed.\n", 238 __func__, chain); 239 rx[chain][0] = 0xff; 240 rx[chain][1] = 0xff; 241 } else if (ret == 3) { 242 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 243 "%s: chain %d: Both Tx and Rx " 244 "succeeded.\n", __func__, chain); 245 } 246 } 247 248 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB, 249 "%s: results for run %d chain %d: tx[0] 0x%x, " 250 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain, 251 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]); 252 } 253 254 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 255 vals->ofdm0_trxpathena); 256 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 257 vals->fpga0_rfifacesw1); 258 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar); 259 260 rtwn_bb_write(sc, 0x0e28, 0x00); 261 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 262 if (sc->ntxchains > 1) 263 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 264 265 if (n != 0) { 266 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 267 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 268 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 269 } 270 271 for (i = 0; i < nitems(reg_adda); i++) 272 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]); 273 274 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause); 275 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]); 276 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]); 277 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg); 278 } 279 } 280 281 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 282 static int 283 r92ce_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2], 284 uint16_t rx1[2][2], uint16_t tx2[2][2], uint16_t rx2[2][2]) 285 { 286 int chain, i, tx_ok[2], rx_ok[2]; 287 288 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 289 for (chain = 0; chain < sc->ntxchains; chain++) { 290 for (i = 0; i < 2; i++) { 291 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 292 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 293 continue; 294 295 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 296 RTWN_IQ_CAL_MAX_TOLERANCE); 297 298 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 299 RTWN_IQ_CAL_MAX_TOLERANCE); 300 } 301 } 302 303 if (sc->ntxchains > 1) 304 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 305 else 306 return (tx_ok[0] && rx_ok[0]); 307 } 308 #undef RTWN_IQ_CAL_MAX_TOLERANCE 309 310 static void 311 r92ce_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 312 uint16_t rx[2], int chain) 313 { 314 uint32_t reg, val, x; 315 long y, tx_c; 316 317 if (tx[0] == 0xff || tx[1] == 0xff) 318 return; 319 320 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 321 val = ((reg >> 22) & 0x3ff); 322 x = tx[0]; 323 if (x & 0x00000200) 324 x |= 0xfffffc00; 325 reg = (((x * val) >> 8) & 0x3ff); 326 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg); 327 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000, 328 ((x * val) & 0x80) << 24); 329 330 y = tx[1]; 331 if (y & 0x00000200) 332 y |= 0xfffffc00; 333 tx_c = (y * val) >> 8; 334 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000, 335 (tx_c & 0x3c0) << 22); 336 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000, 337 (tx_c & 0x3f) << 16); 338 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000, 339 ((y * val) & 0x80) << 22); 340 341 if (rx[0] == 0xff || rx[1] == 0xff) 342 return; 343 344 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff, 345 rx[0] & 0x3ff); 346 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00, 347 (rx[1] & 0x3f) << 10); 348 349 if (chain == 0) { 350 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000, 351 (rx[1] & 0x3c0) << 22); 352 } else { 353 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000, 354 (rx[1] & 0x3c0) << 6); 355 } 356 } 357 358 #define RTWN_IQ_CAL_NRUN 3 359 void 360 r92ce_iq_calib(struct rtwn_softc *sc) 361 { 362 struct r92ce_iq_cal_reg_vals vals; 363 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 364 int n, valid; 365 366 valid = 0; 367 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 368 r92ce_iq_calib_run(sc, n, tx[n], rx[n], &vals); 369 370 if (n == 0) 371 continue; 372 373 /* Valid results remain stable after consecutive runs. */ 374 valid = r92ce_iq_calib_compare_results(sc, tx[n - 1], 375 rx[n - 1], tx[n], rx[n]); 376 if (valid) 377 break; 378 } 379 380 if (valid) { 381 r92ce_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 382 if (sc->ntxchains > 1) 383 r92ce_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 384 } 385 } 386 #undef RTWN_IQ_CAL_NRUN 387