xref: /freebsd/sys/dev/rtwn/rtl8188e/usb/r88eu_init.c (revision a163403b62d3d32fddbde14991d67624945e78df)
1 /*	$OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $	*/
2 
3 /*-
4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5  * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6  * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
7  *
8  * Permission to use, copy, modify, and distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  */
20 
21 #include <sys/cdefs.h>
22 __FBSDID("$FreeBSD$");
23 
24 #include "opt_wlan.h"
25 
26 #include <sys/param.h>
27 #include <sys/lock.h>
28 #include <sys/mutex.h>
29 #include <sys/mbuf.h>
30 #include <sys/kernel.h>
31 #include <sys/socket.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/queue.h>
35 #include <sys/taskqueue.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/linker.h>
39 
40 #include <net/if.h>
41 #include <net/ethernet.h>
42 #include <net/if_media.h>
43 
44 #include <net80211/ieee80211_var.h>
45 #include <net80211/ieee80211_radiotap.h>
46 
47 #include <dev/rtwn/if_rtwnreg.h>
48 #include <dev/rtwn/if_rtwnvar.h>
49 
50 #include <dev/rtwn/rtl8192c/r92c.h>
51 #include <dev/rtwn/rtl8192c/r92c_var.h>
52 
53 #include <dev/rtwn/rtl8188e/usb/r88eu.h>
54 #include <dev/rtwn/rtl8188e/usb/r88eu_reg.h>
55 
56 
57 void
58 r88eu_init_bb(struct rtwn_softc *sc)
59 {
60 
61 	/* Enable BB and RF. */
62 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
63 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
64 	    R92C_SYS_FUNC_EN_DIO_RF);
65 
66 	rtwn_write_1(sc, R92C_RF_CTRL,
67 	    R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
68 	rtwn_write_1(sc, R92C_SYS_FUNC_EN,
69 	    R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
70 	    R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
71 
72 	r88e_init_bb_common(sc);
73 }
74 
75 int
76 r88eu_power_on(struct rtwn_softc *sc)
77 {
78 #define RTWN_CHK(res) do {	\
79 	if (res != 0)		\
80 		return (EIO);	\
81 } while(0)
82 	int ntries;
83 
84 	/* Wait for power ready bit. */
85 	for (ntries = 0; ntries < 5000; ntries++) {
86 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
87 			break;
88 		rtwn_delay(sc, 10);
89 	}
90 	if (ntries == 5000) {
91 		device_printf(sc->sc_dev,
92 		    "timeout waiting for chip power up\n");
93 		return (ETIMEDOUT);
94 	}
95 
96 	/* Reset BB. */
97 	RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
98 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
99 
100 	RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
101 
102 	/* Disable HWPDN. */
103 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
104 	    R92C_APS_FSMCO_APDM_HPDN, 0, 1));
105 
106 	/* Disable WL suspend. */
107 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
108 	    R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
109 
110 	RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
111 	    0, R92C_APS_FSMCO_APFM_ONMAC, 1));
112 	for (ntries = 0; ntries < 5000; ntries++) {
113 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
114 		    R92C_APS_FSMCO_APFM_ONMAC))
115 			break;
116 		rtwn_delay(sc, 10);
117 	}
118 	if (ntries == 5000)
119 		return (ETIMEDOUT);
120 
121 	/* Enable LDO normal mode. */
122 	RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
123 	    R92C_LPLDO_CTRL_SLEEP, 0));
124 
125 	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
126 	RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
127 	RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
128 	    R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
129 	    R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
130 	    R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
131 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
132 	    R92C_CR_CALTMR_EN));
133 
134 	return (0);
135 #undef RTWN_CHK
136 }
137 
138 void
139 r88eu_power_off(struct rtwn_softc *sc)
140 {
141 	uint8_t reg;
142 	int error, ntries;
143 
144 	/* Disable any kind of TX reports. */
145 	error = rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
146 	    R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
147 	if (error == ENXIO)	/* hardware gone */
148 		return;
149 
150 	/* Stop Rx. */
151 	rtwn_write_1(sc, R92C_CR, 0);
152 
153 	/* Move card to Low Power State. */
154 	/* Block all Tx queues. */
155 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
156 
157 	for (ntries = 0; ntries < 10; ntries++) {
158 		/* Should be zero if no packet is transmitting. */
159 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
160 			break;
161 
162 		rtwn_delay(sc, 5000);
163 	}
164 	if (ntries == 10) {
165 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
166 		    __func__);
167 		return;
168 	}
169 
170 	/* CCK and OFDM are disabled, and clock are gated. */
171 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
172 
173 	rtwn_delay(sc, 1);
174 
175 	/* Reset MAC TRX */
176 	rtwn_write_1(sc, R92C_CR,
177 	    R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
178 	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
179 	    R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
180 
181 	/* check if removed later */
182 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
183 
184 	/* Respond TxOK to scheduler */
185 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
186 
187 	/* If firmware in ram code, do reset. */
188 #ifndef RTWN_WITHOUT_UCODE
189 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
190 		r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
191 #endif
192 
193 	/* Reset MCU ready status. */
194 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
195 
196 	/* Disable 32k. */
197 	rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
198 
199 	/* Move card to Disabled state. */
200 	/* Turn off RF. */
201 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
202 
203 	/* LDO Sleep mode. */
204 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
205 
206 	/* Turn off MAC by HW state machine */
207 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
208 	    R92C_APS_FSMCO_APFM_OFF, 1);
209 
210 	for (ntries = 0; ntries < 10; ntries++) {
211 		/* Wait until it will be disabled. */
212 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
213 		    R92C_APS_FSMCO_APFM_OFF) == 0)
214 			break;
215 
216 		rtwn_delay(sc, 5000);
217 	}
218 	if (ntries == 10) {
219 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
220 		    __func__);
221 		return;
222 	}
223 
224 	/* schmit trigger */
225 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
226 
227 	/* Enable WL suspend. */
228 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
229 	    R92C_APS_FSMCO_AFSM_PCIE, R92C_APS_FSMCO_AFSM_HSUS, 1);
230 
231 	/* Enable bandgap mbias in suspend. */
232 	rtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
233 
234 	/* Clear SIC_EN register. */
235 	rtwn_setbits_1(sc, R92C_GPIO_MUXCFG + 1, 0x10, 0);
236 
237 	/* Set USB suspend enable local register */
238 	rtwn_setbits_1(sc, R92C_USB_SUSPEND, 0, 0x10);
239 
240 	/* Reset MCU IO Wrapper. */
241 	reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
242 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
243 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
244 
245 	/* marked as 'For Power Consumption' code. */
246 	rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
247 	rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
248 
249 	rtwn_write_1(sc, R92C_GPIO_IO_SEL,
250 	    rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
251 	rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
252 
253 	/* Set LNA, TRSW, EX_PA Pin to output mode. */
254 	rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
255 }
256 
257 void
258 r88eu_init_intr(struct rtwn_softc *sc)
259 {
260 	/* TODO: adjust */
261 	rtwn_write_4(sc, R88E_HISR, 0xffffffff);
262 	rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
263 	    R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
264 	rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
265 	    R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
266 	rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
267 	    R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
268 }
269 
270 void
271 r88eu_init_rx_agg(struct rtwn_softc *sc)
272 {
273 	/* XXX merge? */
274 	rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
275 	    R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
276 	/* XXX dehardcode */
277 	rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
278 	rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
279 }
280 
281 void
282 r88eu_post_init(struct rtwn_softc *sc)
283 {
284 
285 	/* Enable per-packet TX report. */
286 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
287 
288 	/* Disable Tx if MACID is not associated. */
289 	rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
290 	rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
291 	r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
292 
293 	/* Perform LO and IQ calibrations. */
294 	r88e_iq_calib(sc);
295 	/* Perform LC calibration. */
296 	r92c_lc_calib(sc);
297 
298 	rtwn_write_1(sc, R92C_USB_HRPWM, 0);
299 
300 	if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
301 		/* No support (yet?) for f/w rate adaptation. */
302 		sc->sc_ratectl = RTWN_RATECTL_NET80211;
303 	} else
304 		sc->sc_ratectl = sc->sc_ratectl_sysctl;
305 }
306