1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $ 18 * $FreeBSD$ 19 */ 20 21 #ifndef R88E_REG_H 22 #define R88E_REG_H 23 24 #include <dev/rtwn/rtl8192c/r92c_reg.h> 25 26 /* 27 * MAC registers. 28 */ 29 /* System Configuration. */ 30 #define R88E_BB_PAD_CTRL 0x064 31 #define R88E_HIMR 0x0b0 32 #define R88E_HISR 0x0b4 33 #define R88E_HIMRE 0x0b8 34 #define R88E_HISRE 0x0bc 35 #define R88E_XCK_OUT_CTRL 0x07c 36 /* MAC General Configuration. */ 37 #define R88E_32K_CTRL 0x194 38 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4) 39 /* Protocol Configuration. */ 40 #define R88E_TXPKTBUF_BCNQ1_BDNY 0x457 41 #define R88E_MACID_NO_LINK 0x484 42 #define R88E_TX_RPT_CTRL 0x4ec 43 #define R88E_TX_RPT_MACID_MAX 0x4ed 44 #define R88E_TX_RPT_TIME 0x4f0 45 #define R88E_SCH_TXCMD 0x5f8 46 47 48 /* Bits for R88E_HIMR. */ 49 #define R88E_HIMR_ROK 0x00000001 /* receive DMA OK */ 50 #define R88E_HIMR_RDU 0x00000002 /* Rx descriptor unavailable */ 51 #define R88E_HIMR_VODOK 0x00000004 /* AC_VO DMA OK */ 52 #define R88E_HIMR_VIDOK 0x00000008 /* AC_VI DMA OK */ 53 #define R88E_HIMR_BEDOK 0x00000010 /* AC_BE DMA OK */ 54 #define R88E_HIMR_BKDOK 0x00000020 /* AC_BK DMA OK */ 55 #define R88E_HIMR_MGNTDOK 0x00000040 /* management queue DMA OK */ 56 #define R88E_HIMR_HIGHDOK 0x00000080 /* high queue DMA OK */ 57 #define R88E_HIMR_CPWM 0x00000100 /* CPU power mode intr 1 */ 58 #define R88E_HIMR_CPWM2 0x00000200 /* CPU power mode intr 2 */ 59 #define R88E_HIMR_C2HCMD 0x00000400 /* C2H command interrupt */ 60 #define R88E_HIMR_HISR 0x00000800 /* (HISR & HIMR) != 0 */ 61 #define R88E_HIMR_ATIMEND 0x00001000 /* ATIM window end interrupt */ 62 #define R88E_HIMR_HSISR 0x00008000 /* (HSIMR & HSISR) != 0 */ 63 #define R88E_HIMR_BCNDERR 0x00010000 /* beacon queue DMA error */ 64 #define R88E_HIMR_BCNINT 0x00100000 /* beacon DMA interrupt 0 */ 65 #define R88E_HIMR_TSF32 0x01000000 /* TSF 32 bit interrupt */ 66 #define R88E_HIMR_TBDOK 0x02000000 /* beacon transmit OK */ 67 #define R88E_HIMR_TBDER 0x04000000 /* beacon transmit error */ 68 #define R88E_HIMR_GTIMER3 0x08000000 /* GTIMER3 interrupt */ 69 #define R88E_HIMR_GTIMER4 0x10000000 /* GTIMER4 interrupt */ 70 #define R88E_HIMR_PSTIMEOUT 0x20000000 /* powersave timeout */ 71 #define R88E_HIMR_TXRPT 0x40000000 /* Tx report interrupt */ 72 73 /* Bits for R88E_HIMRE.*/ 74 #define R88E_HIMRE_RXFOVW 0x00000100 /* receive FIFO overflow */ 75 #define R88E_HIMRE_TXFOVW 0x00000200 /* transmit FIFO overflow */ 76 #define R88E_HIMRE_RXERR 0x00000400 /* receive error */ 77 #define R88E_HIMRE_TXERR 0x00000800 /* transmit error */ 78 #define R88E_HIMRE_BCNDOK1 0x00004000 /* beacon queue DMA OK (1) */ 79 #define R88E_HIMRE_BCNDOK2 0x00008000 /* beacon queue DMA OK (2) */ 80 #define R88E_HIMRE_BCNDOK3 0x00010000 /* beacon queue DMA OK (3) */ 81 #define R88E_HIMRE_BCNDOK4 0x00020000 /* beacon queue DMA OK (4) */ 82 #define R88E_HIMRE_BCNDOK5 0x00040000 /* beacon queue DMA OK (5) */ 83 #define R88E_HIMRE_BCNDOK6 0x00080000 /* beacon queue DMA OK (6) */ 84 #define R88E_HIMRE_BCNDOK7 0x00100000 /* beacon queue DMA OK (7) */ 85 #define R88E_HIMRE_BCNDMAINT1 0x00200000 /* beacon DMA interrupt 1 */ 86 #define R88E_HIMRE_BCNDMAINT2 0x00400000 /* beacon DMA interrupt 2 */ 87 #define R88E_HIMRE_BCNDMAINT3 0x00800000 /* beacon DMA interrupt 3 */ 88 #define R88E_HIMRE_BCNDMAINT4 0x01000000 /* beacon DMA interrupt 4 */ 89 #define R88E_HIMRE_BCNDMAINT5 0x02000000 /* beacon DMA interrupt 5 */ 90 #define R88E_HIMRE_BCNDMAINT6 0x04000000 /* beacon DMA interrupt 6 */ 91 #define R88E_HIMRE_BCNDMAINT7 0x08000000 /* beacon DMA interrupt 7 */ 92 93 /* Bits for R88E_TX_RPT_CTRL. */ 94 #define R88E_TX_RPT1_ENA 0x01 95 #define R88E_TX_RPT2_ENA 0x02 96 97 /* Bits for R92C_MBID_NUM. */ 98 #define R88E_MBID_TXBCN_RPT(id) (0x08 << (id)) 99 100 /* Bits for R92C_SECCFG. */ 101 #define R88E_SECCFG_CHK_KEYID 0x0100 102 103 104 /* 105 * Baseband registers. 106 */ 107 /* Bits for R92C_LSSI_PARAM(i). */ 108 #define R88E_LSSI_PARAM_ADDR_M 0x0ff00000 109 #define R88E_LSSI_PARAM_ADDR_S 20 110 111 112 /* 113 * RF (6052) registers. 114 */ 115 #define R88E_RF_T_METER 0x42 116 #define R88E_RF_WE_LUT 0xef 117 118 /* Bits for R92C_RF_CHNLBW. */ 119 #define R88E_RF_CHNLBW_BW20 0x00c00 120 121 /* Bits for R88E_RF_T_METER. */ 122 #define R88E_RF_T_METER_VAL_M 0x0fc00 123 #define R88E_RF_T_METER_VAL_S 10 124 #define R88E_RF_T_METER_START 0x30000 125 126 /* Bits for R88E_XCK_OUT_CTRL. */ 127 #define R88E_XCK_OUT_CTRL_EN 1 128 129 #endif /* R88E_REG_H */ 130