xref: /freebsd/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c (revision 48f21a05da2988fb4643e6b8fdf34a6cdff211f2)
1b3f3786eSAndriy Voskoboinyk /*-
2b3f3786eSAndriy Voskoboinyk  * Copyright (c) 2017 Farhan Khan <khanzf@gmail.com>
3b3f3786eSAndriy Voskoboinyk  *
4b3f3786eSAndriy Voskoboinyk  * Permission to use, copy, modify, and distribute this software for any
5b3f3786eSAndriy Voskoboinyk  * purpose with or without fee is hereby granted, provided that the above
6b3f3786eSAndriy Voskoboinyk  * copyright notice and this permission notice appear in all copies.
7b3f3786eSAndriy Voskoboinyk  *
8b3f3786eSAndriy Voskoboinyk  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9b3f3786eSAndriy Voskoboinyk  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10b3f3786eSAndriy Voskoboinyk  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11b3f3786eSAndriy Voskoboinyk  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12b3f3786eSAndriy Voskoboinyk  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13b3f3786eSAndriy Voskoboinyk  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14b3f3786eSAndriy Voskoboinyk  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15b3f3786eSAndriy Voskoboinyk  */
16b3f3786eSAndriy Voskoboinyk 
17b3f3786eSAndriy Voskoboinyk #include <sys/cdefs.h>
18b3f3786eSAndriy Voskoboinyk __FBSDID("$FreeBSD$");
19b3f3786eSAndriy Voskoboinyk 
20b3f3786eSAndriy Voskoboinyk #include "opt_wlan.h"
21b3f3786eSAndriy Voskoboinyk 
22b3f3786eSAndriy Voskoboinyk #include <sys/param.h>
23b3f3786eSAndriy Voskoboinyk #include <sys/lock.h>
24b3f3786eSAndriy Voskoboinyk #include <sys/mutex.h>
25b3f3786eSAndriy Voskoboinyk #include <sys/mbuf.h>
26b3f3786eSAndriy Voskoboinyk #include <sys/kernel.h>
27b3f3786eSAndriy Voskoboinyk #include <sys/socket.h>
28b3f3786eSAndriy Voskoboinyk #include <sys/systm.h>
29b3f3786eSAndriy Voskoboinyk #include <sys/malloc.h>
30b3f3786eSAndriy Voskoboinyk #include <sys/queue.h>
31b3f3786eSAndriy Voskoboinyk #include <sys/taskqueue.h>
32b3f3786eSAndriy Voskoboinyk #include <sys/bus.h>
33b3f3786eSAndriy Voskoboinyk #include <sys/endian.h>
34b3f3786eSAndriy Voskoboinyk #include <sys/linker.h>
35b3f3786eSAndriy Voskoboinyk 
36b3f3786eSAndriy Voskoboinyk #include <machine/bus.h>
37b3f3786eSAndriy Voskoboinyk #include <machine/resource.h>
38b3f3786eSAndriy Voskoboinyk #include <sys/rman.h>
39b3f3786eSAndriy Voskoboinyk 
40b3f3786eSAndriy Voskoboinyk #include <net/if.h>
41b3f3786eSAndriy Voskoboinyk #include <net/ethernet.h>
42b3f3786eSAndriy Voskoboinyk #include <net/if_media.h>
43b3f3786eSAndriy Voskoboinyk 
44b3f3786eSAndriy Voskoboinyk #include <net80211/ieee80211_var.h>
45b3f3786eSAndriy Voskoboinyk #include <net80211/ieee80211_radiotap.h>
46b3f3786eSAndriy Voskoboinyk 
47b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/if_rtwnvar.h>
48b3f3786eSAndriy Voskoboinyk 
49b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/pci/rtwn_pci_var.h>
50b3f3786eSAndriy Voskoboinyk 
51b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/rtl8192c/r92c.h>
52b3f3786eSAndriy Voskoboinyk 
53b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/rtl8188e/pci/r88ee.h>
54b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/rtl8188e/pci/r88ee_reg.h>
55b3f3786eSAndriy Voskoboinyk 
56b3f3786eSAndriy Voskoboinyk void
57b3f3786eSAndriy Voskoboinyk r88ee_init_bb(struct rtwn_softc *sc)
58b3f3786eSAndriy Voskoboinyk {
59b3f3786eSAndriy Voskoboinyk 
60b3f3786eSAndriy Voskoboinyk 	/* Enable BB and RF. */
61b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
62b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
63b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_DIO_RF);
64b3f3786eSAndriy Voskoboinyk 
65b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RF_CTRL,
66b3f3786eSAndriy Voskoboinyk 	    R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
67b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_PPLL |
68b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_PCIEA | R92C_SYS_FUNC_EN_DIO_PCIE |
69b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
70b3f3786eSAndriy Voskoboinyk 
71b3f3786eSAndriy Voskoboinyk 	r88e_init_bb_common(sc);
72b3f3786eSAndriy Voskoboinyk }
73b3f3786eSAndriy Voskoboinyk 
74b3f3786eSAndriy Voskoboinyk void
75b3f3786eSAndriy Voskoboinyk r88ee_init_intr(struct rtwn_softc *sc)
76b3f3786eSAndriy Voskoboinyk {
77b3f3786eSAndriy Voskoboinyk 	/* Disable interrupts. */
78b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_HIMR, 0x00000000);
79b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
80b3f3786eSAndriy Voskoboinyk }
81b3f3786eSAndriy Voskoboinyk 
82b3f3786eSAndriy Voskoboinyk int
83b3f3786eSAndriy Voskoboinyk r88ee_power_on(struct rtwn_softc *sc)
84b3f3786eSAndriy Voskoboinyk {
85b3f3786eSAndriy Voskoboinyk 	int ntries;
86b3f3786eSAndriy Voskoboinyk 
87*48f21a05SAndriy Voskoboinyk 	/* Disable XTAL output for power saving. */
88*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
89*48f21a05SAndriy Voskoboinyk 
90*48f21a05SAndriy Voskoboinyk 	/* Unlock ISO/CLK/Power control register. */
91*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
92*48f21a05SAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
93*48f21a05SAndriy Voskoboinyk 
94*48f21a05SAndriy Voskoboinyk 	/* Wait for power ready bit */
95b3f3786eSAndriy Voskoboinyk 	for(ntries = 0; ntries < 5000; ntries++) {
96b3f3786eSAndriy Voskoboinyk 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
97b3f3786eSAndriy Voskoboinyk 			break;
98b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 10);
99b3f3786eSAndriy Voskoboinyk 	}
100b3f3786eSAndriy Voskoboinyk 	if (ntries == 5000) {
101b3f3786eSAndriy Voskoboinyk 		device_printf(sc->sc_dev,
102b3f3786eSAndriy Voskoboinyk 		    "timeout waiting for chip power up\n");
103b3f3786eSAndriy Voskoboinyk 		return (ETIMEDOUT);
104b3f3786eSAndriy Voskoboinyk 	}
105b3f3786eSAndriy Voskoboinyk 
106b3f3786eSAndriy Voskoboinyk 	/* Reset BB. */
107b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
108b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
109b3f3786eSAndriy Voskoboinyk 
110b3f3786eSAndriy Voskoboinyk 	/* schmit trigger */
111b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
112b3f3786eSAndriy Voskoboinyk 
113b3f3786eSAndriy Voskoboinyk 	/* Disable HWPDN. */
114b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
115b3f3786eSAndriy Voskoboinyk 	    R92C_APS_FSMCO_APDM_HPDN, 0, 1);
116b3f3786eSAndriy Voskoboinyk 
117b3f3786eSAndriy Voskoboinyk 	/* Disable WL suspend. */
118b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
119b3f3786eSAndriy Voskoboinyk 	    R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
120b3f3786eSAndriy Voskoboinyk 
121*48f21a05SAndriy Voskoboinyk 	/* Auto-enable WLAN */
122b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
123b3f3786eSAndriy Voskoboinyk 	    0, R92C_APS_FSMCO_APFM_ONMAC, 1);
124b3f3786eSAndriy Voskoboinyk 	for (ntries = 0; ntries < 5000; ntries++) {
125b3f3786eSAndriy Voskoboinyk 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
126b3f3786eSAndriy Voskoboinyk 		    R92C_APS_FSMCO_APFM_ONMAC))
127b3f3786eSAndriy Voskoboinyk 			break;
128b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 10);
129b3f3786eSAndriy Voskoboinyk 	}
130b3f3786eSAndriy Voskoboinyk 	if (ntries == 5000)
131b3f3786eSAndriy Voskoboinyk 		return (ETIMEDOUT);
132b3f3786eSAndriy Voskoboinyk 
133b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
134b3f3786eSAndriy Voskoboinyk 
135b3f3786eSAndriy Voskoboinyk 	/* Enable LDO normal mode. */
136b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
137b3f3786eSAndriy Voskoboinyk 
138*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
139*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
140*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
141*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
142*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
143*48f21a05SAndriy Voskoboinyk 
144b3f3786eSAndriy Voskoboinyk 	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
145b3f3786eSAndriy Voskoboinyk 	rtwn_write_2(sc, R92C_CR, 0);
146b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_CR, 0,
147b3f3786eSAndriy Voskoboinyk 	    R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
148b3f3786eSAndriy Voskoboinyk 	    R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
149b3f3786eSAndriy Voskoboinyk 	    R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
150b3f3786eSAndriy Voskoboinyk 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
151b3f3786eSAndriy Voskoboinyk 	    R92C_CR_CALTMR_EN);
152b3f3786eSAndriy Voskoboinyk 
153b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R92C_INT_MIG, 0);
154b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R92C_MCUTST_1, 0);
155b3f3786eSAndriy Voskoboinyk 
156b3f3786eSAndriy Voskoboinyk 	return (0);
157b3f3786eSAndriy Voskoboinyk }
158b3f3786eSAndriy Voskoboinyk 
159b3f3786eSAndriy Voskoboinyk void
160b3f3786eSAndriy Voskoboinyk r88ee_power_off(struct rtwn_softc *sc)
161b3f3786eSAndriy Voskoboinyk {
162b3f3786eSAndriy Voskoboinyk 	uint8_t reg;
163b3f3786eSAndriy Voskoboinyk 	int ntries;
164b3f3786eSAndriy Voskoboinyk 
165b3f3786eSAndriy Voskoboinyk 	/* Disable any kind of TX reports. */
166b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
167b3f3786eSAndriy Voskoboinyk 	    R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
168b3f3786eSAndriy Voskoboinyk 
169b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0xFF);
170b3f3786eSAndriy Voskoboinyk 
171b3f3786eSAndriy Voskoboinyk 	/* Move card to Low Power State. */
172b3f3786eSAndriy Voskoboinyk 	/* Block all Tx queues. */
173b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
174b3f3786eSAndriy Voskoboinyk 
175b3f3786eSAndriy Voskoboinyk 	for (ntries = 0; ntries < 10; ntries++) {
176b3f3786eSAndriy Voskoboinyk 		/* Should be zero if no packet is transmitting. */
177b3f3786eSAndriy Voskoboinyk 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
178b3f3786eSAndriy Voskoboinyk 			break;
179b3f3786eSAndriy Voskoboinyk 
180b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 5000);
181b3f3786eSAndriy Voskoboinyk 	}
182b3f3786eSAndriy Voskoboinyk 	if (ntries == 10) {
183b3f3786eSAndriy Voskoboinyk 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
184b3f3786eSAndriy Voskoboinyk 		    __func__);
185b3f3786eSAndriy Voskoboinyk 		return;
186b3f3786eSAndriy Voskoboinyk 	}
187b3f3786eSAndriy Voskoboinyk 
188b3f3786eSAndriy Voskoboinyk 	/* CCK and OFDM are disabled, and clock are gated. */
189b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
190b3f3786eSAndriy Voskoboinyk 
191b3f3786eSAndriy Voskoboinyk 	rtwn_delay(sc, 1);
192b3f3786eSAndriy Voskoboinyk 
193b3f3786eSAndriy Voskoboinyk 	/* Reset MAC TRX */
194b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_CR,
195b3f3786eSAndriy Voskoboinyk 	    R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
196b3f3786eSAndriy Voskoboinyk 	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
197b3f3786eSAndriy Voskoboinyk 	    R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
198b3f3786eSAndriy Voskoboinyk 
199b3f3786eSAndriy Voskoboinyk 	/* Disable h/w encryption. */
200b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
201b3f3786eSAndriy Voskoboinyk 
202b3f3786eSAndriy Voskoboinyk 	/* Respond TxOK to scheduler */
203b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
204b3f3786eSAndriy Voskoboinyk 
205b3f3786eSAndriy Voskoboinyk 	/* If firmware in ram code, do reset. */
206b3f3786eSAndriy Voskoboinyk #ifndef RTWN_WITHOUT_UCODE
207b3f3786eSAndriy Voskoboinyk 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
208b3f3786eSAndriy Voskoboinyk 		r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
209b3f3786eSAndriy Voskoboinyk #endif
210b3f3786eSAndriy Voskoboinyk 
211b3f3786eSAndriy Voskoboinyk 	/* Reset MCU ready status. */
212b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
213b3f3786eSAndriy Voskoboinyk 
214b3f3786eSAndriy Voskoboinyk 	/* Disable 32k. */
215b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
216b3f3786eSAndriy Voskoboinyk 
217b3f3786eSAndriy Voskoboinyk 	/* Move card to Disabled state. */
218b3f3786eSAndriy Voskoboinyk 	/* Turn off RF. */
219b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
220b3f3786eSAndriy Voskoboinyk 
221b3f3786eSAndriy Voskoboinyk 	/* LDO Sleep mode. */
222b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
223b3f3786eSAndriy Voskoboinyk 
224b3f3786eSAndriy Voskoboinyk 	/* Turn off MAC by HW state machine */
225b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
226b3f3786eSAndriy Voskoboinyk 	    R92C_APS_FSMCO_APFM_OFF, 1);
227b3f3786eSAndriy Voskoboinyk 
228b3f3786eSAndriy Voskoboinyk 	for (ntries = 0; ntries < 10; ntries++) {
229b3f3786eSAndriy Voskoboinyk 		/* Wait until it will be disabled. */
230b3f3786eSAndriy Voskoboinyk 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
231b3f3786eSAndriy Voskoboinyk 		    R92C_APS_FSMCO_APFM_OFF) == 0)
232b3f3786eSAndriy Voskoboinyk 			break;
233b3f3786eSAndriy Voskoboinyk 
234b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 5000);
235b3f3786eSAndriy Voskoboinyk 	}
236b3f3786eSAndriy Voskoboinyk 	if (ntries == 10) {
237b3f3786eSAndriy Voskoboinyk 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
238b3f3786eSAndriy Voskoboinyk 		    __func__);
239b3f3786eSAndriy Voskoboinyk 		return;
240b3f3786eSAndriy Voskoboinyk 	}
241b3f3786eSAndriy Voskoboinyk 
242b3f3786eSAndriy Voskoboinyk 	/* schmit trigger */
243b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
244b3f3786eSAndriy Voskoboinyk 
245b3f3786eSAndriy Voskoboinyk 	/* Reset MCU IO Wrapper. */
246b3f3786eSAndriy Voskoboinyk 	reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
247b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
248b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
249b3f3786eSAndriy Voskoboinyk 
250b3f3786eSAndriy Voskoboinyk 	/* marked as 'For Power Consumption' code. */
251b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
252b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
253b3f3786eSAndriy Voskoboinyk 
254b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_GPIO_IO_SEL,
255b3f3786eSAndriy Voskoboinyk 	    rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
256b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
257b3f3786eSAndriy Voskoboinyk 
258b3f3786eSAndriy Voskoboinyk 	/* Set LNA, TRSW, EX_PA Pin to output mode. */
259b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
260b3f3786eSAndriy Voskoboinyk }
261b3f3786eSAndriy Voskoboinyk 
262b3f3786eSAndriy Voskoboinyk void
263b3f3786eSAndriy Voskoboinyk r88ee_post_init(struct rtwn_softc *sc)
264b3f3786eSAndriy Voskoboinyk {
265b3f3786eSAndriy Voskoboinyk 
266b3f3786eSAndriy Voskoboinyk 	/* Enable per-packet TX report. */
267b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
268b3f3786eSAndriy Voskoboinyk 
269b3f3786eSAndriy Voskoboinyk 	/* Disable Tx if MACID is not associated. */
270b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
271b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
272b3f3786eSAndriy Voskoboinyk 	r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
273b3f3786eSAndriy Voskoboinyk 
274b3f3786eSAndriy Voskoboinyk 	/* Perform LO and IQ calibrations. */
275b3f3786eSAndriy Voskoboinyk 	r88e_iq_calib(sc);
276b3f3786eSAndriy Voskoboinyk 	/* Perform LC calibration. */
277b3f3786eSAndriy Voskoboinyk 	r92c_lc_calib(sc);
278b3f3786eSAndriy Voskoboinyk 
279b3f3786eSAndriy Voskoboinyk 	/* Enable Rx DMA */
280b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0);
281b3f3786eSAndriy Voskoboinyk 
282b3f3786eSAndriy Voskoboinyk 	if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
283b3f3786eSAndriy Voskoboinyk 		/* No support (yet?) for f/w rate adaptation. */
284b3f3786eSAndriy Voskoboinyk 		sc->sc_ratectl = RTWN_RATECTL_NET80211;
285b3f3786eSAndriy Voskoboinyk 	} else
286b3f3786eSAndriy Voskoboinyk 		sc->sc_ratectl = sc->sc_ratectl_sysctl;
287b3f3786eSAndriy Voskoboinyk }
288