xref: /freebsd/sys/dev/rtwn/rtl8188e/pci/r88ee_init.c (revision 685dc743dc3b5645e34836464128e1c0558b404b)
1b3f3786eSAndriy Voskoboinyk /*-
2b3f3786eSAndriy Voskoboinyk  * Copyright (c) 2017 Farhan Khan <khanzf@gmail.com>
3b3f3786eSAndriy Voskoboinyk  *
4b3f3786eSAndriy Voskoboinyk  * Permission to use, copy, modify, and distribute this software for any
5b3f3786eSAndriy Voskoboinyk  * purpose with or without fee is hereby granted, provided that the above
6b3f3786eSAndriy Voskoboinyk  * copyright notice and this permission notice appear in all copies.
7b3f3786eSAndriy Voskoboinyk  *
8b3f3786eSAndriy Voskoboinyk  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9b3f3786eSAndriy Voskoboinyk  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10b3f3786eSAndriy Voskoboinyk  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11b3f3786eSAndriy Voskoboinyk  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12b3f3786eSAndriy Voskoboinyk  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13b3f3786eSAndriy Voskoboinyk  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14b3f3786eSAndriy Voskoboinyk  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15b3f3786eSAndriy Voskoboinyk  */
16b3f3786eSAndriy Voskoboinyk 
17b3f3786eSAndriy Voskoboinyk #include <sys/cdefs.h>
18b3f3786eSAndriy Voskoboinyk #include "opt_wlan.h"
19b3f3786eSAndriy Voskoboinyk 
20b3f3786eSAndriy Voskoboinyk #include <sys/param.h>
21b3f3786eSAndriy Voskoboinyk #include <sys/lock.h>
22b3f3786eSAndriy Voskoboinyk #include <sys/mutex.h>
23b3f3786eSAndriy Voskoboinyk #include <sys/mbuf.h>
24b3f3786eSAndriy Voskoboinyk #include <sys/kernel.h>
25b3f3786eSAndriy Voskoboinyk #include <sys/socket.h>
26b3f3786eSAndriy Voskoboinyk #include <sys/systm.h>
27b3f3786eSAndriy Voskoboinyk #include <sys/malloc.h>
28b3f3786eSAndriy Voskoboinyk #include <sys/queue.h>
29b3f3786eSAndriy Voskoboinyk #include <sys/taskqueue.h>
30b3f3786eSAndriy Voskoboinyk #include <sys/bus.h>
31b3f3786eSAndriy Voskoboinyk #include <sys/endian.h>
32b3f3786eSAndriy Voskoboinyk #include <sys/linker.h>
33b3f3786eSAndriy Voskoboinyk 
34b3f3786eSAndriy Voskoboinyk #include <machine/bus.h>
35b3f3786eSAndriy Voskoboinyk #include <machine/resource.h>
36b3f3786eSAndriy Voskoboinyk #include <sys/rman.h>
37b3f3786eSAndriy Voskoboinyk 
38b3f3786eSAndriy Voskoboinyk #include <net/if.h>
39b3f3786eSAndriy Voskoboinyk #include <net/ethernet.h>
40b3f3786eSAndriy Voskoboinyk #include <net/if_media.h>
41b3f3786eSAndriy Voskoboinyk 
42b3f3786eSAndriy Voskoboinyk #include <net80211/ieee80211_var.h>
43b3f3786eSAndriy Voskoboinyk #include <net80211/ieee80211_radiotap.h>
44b3f3786eSAndriy Voskoboinyk 
45b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/if_rtwnvar.h>
46b3f3786eSAndriy Voskoboinyk 
47b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/pci/rtwn_pci_var.h>
48b3f3786eSAndriy Voskoboinyk 
49b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/rtl8192c/r92c.h>
50b3f3786eSAndriy Voskoboinyk 
51b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/rtl8188e/pci/r88ee.h>
52b3f3786eSAndriy Voskoboinyk #include <dev/rtwn/rtl8188e/pci/r88ee_reg.h>
53b3f3786eSAndriy Voskoboinyk 
54b3f3786eSAndriy Voskoboinyk void
r88ee_init_bb(struct rtwn_softc * sc)55b3f3786eSAndriy Voskoboinyk r88ee_init_bb(struct rtwn_softc *sc)
56b3f3786eSAndriy Voskoboinyk {
57b3f3786eSAndriy Voskoboinyk 
58b3f3786eSAndriy Voskoboinyk 	/* Enable BB and RF. */
59b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
60b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
61b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_DIO_RF);
62b3f3786eSAndriy Voskoboinyk 
63b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RF_CTRL,
64b3f3786eSAndriy Voskoboinyk 	    R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
65b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_PPLL |
66b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_PCIEA | R92C_SYS_FUNC_EN_DIO_PCIE |
67b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
68b3f3786eSAndriy Voskoboinyk 
69b3f3786eSAndriy Voskoboinyk 	r88e_init_bb_common(sc);
70b3f3786eSAndriy Voskoboinyk }
71b3f3786eSAndriy Voskoboinyk 
72b3f3786eSAndriy Voskoboinyk void
r88ee_init_intr(struct rtwn_softc * sc)73b3f3786eSAndriy Voskoboinyk r88ee_init_intr(struct rtwn_softc *sc)
74b3f3786eSAndriy Voskoboinyk {
75b3f3786eSAndriy Voskoboinyk 	/* Disable interrupts. */
76b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_HIMR, 0x00000000);
77b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
78b3f3786eSAndriy Voskoboinyk }
79b3f3786eSAndriy Voskoboinyk 
80b3f3786eSAndriy Voskoboinyk int
r88ee_power_on(struct rtwn_softc * sc)81b3f3786eSAndriy Voskoboinyk r88ee_power_on(struct rtwn_softc *sc)
82b3f3786eSAndriy Voskoboinyk {
83b3f3786eSAndriy Voskoboinyk 	int ntries;
84b3f3786eSAndriy Voskoboinyk 
85*48f21a05SAndriy Voskoboinyk 	/* Disable XTAL output for power saving. */
86*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
87*48f21a05SAndriy Voskoboinyk 
88*48f21a05SAndriy Voskoboinyk 	/* Unlock ISO/CLK/Power control register. */
89*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
90*48f21a05SAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
91*48f21a05SAndriy Voskoboinyk 
92*48f21a05SAndriy Voskoboinyk 	/* Wait for power ready bit */
93b3f3786eSAndriy Voskoboinyk 	for(ntries = 0; ntries < 5000; ntries++) {
94b3f3786eSAndriy Voskoboinyk 		if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
95b3f3786eSAndriy Voskoboinyk 			break;
96b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 10);
97b3f3786eSAndriy Voskoboinyk 	}
98b3f3786eSAndriy Voskoboinyk 	if (ntries == 5000) {
99b3f3786eSAndriy Voskoboinyk 		device_printf(sc->sc_dev,
100b3f3786eSAndriy Voskoboinyk 		    "timeout waiting for chip power up\n");
101b3f3786eSAndriy Voskoboinyk 		return (ETIMEDOUT);
102b3f3786eSAndriy Voskoboinyk 	}
103b3f3786eSAndriy Voskoboinyk 
104b3f3786eSAndriy Voskoboinyk 	/* Reset BB. */
105b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
106b3f3786eSAndriy Voskoboinyk 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
107b3f3786eSAndriy Voskoboinyk 
108b3f3786eSAndriy Voskoboinyk 	/* schmit trigger */
109b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
110b3f3786eSAndriy Voskoboinyk 
111b3f3786eSAndriy Voskoboinyk 	/* Disable HWPDN. */
112b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
113b3f3786eSAndriy Voskoboinyk 	    R92C_APS_FSMCO_APDM_HPDN, 0, 1);
114b3f3786eSAndriy Voskoboinyk 
115b3f3786eSAndriy Voskoboinyk 	/* Disable WL suspend. */
116b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
117b3f3786eSAndriy Voskoboinyk 	    R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
118b3f3786eSAndriy Voskoboinyk 
119*48f21a05SAndriy Voskoboinyk 	/* Auto-enable WLAN */
120b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
121b3f3786eSAndriy Voskoboinyk 	    0, R92C_APS_FSMCO_APFM_ONMAC, 1);
122b3f3786eSAndriy Voskoboinyk 	for (ntries = 0; ntries < 5000; ntries++) {
123b3f3786eSAndriy Voskoboinyk 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
124b3f3786eSAndriy Voskoboinyk 		    R92C_APS_FSMCO_APFM_ONMAC))
125b3f3786eSAndriy Voskoboinyk 			break;
126b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 10);
127b3f3786eSAndriy Voskoboinyk 	}
128b3f3786eSAndriy Voskoboinyk 	if (ntries == 5000)
129b3f3786eSAndriy Voskoboinyk 		return (ETIMEDOUT);
130b3f3786eSAndriy Voskoboinyk 
131b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
132b3f3786eSAndriy Voskoboinyk 
133b3f3786eSAndriy Voskoboinyk 	/* Enable LDO normal mode. */
134b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
135b3f3786eSAndriy Voskoboinyk 
136*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
137*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
138*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
139*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
140*48f21a05SAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
141*48f21a05SAndriy Voskoboinyk 
142b3f3786eSAndriy Voskoboinyk 	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
143b3f3786eSAndriy Voskoboinyk 	rtwn_write_2(sc, R92C_CR, 0);
144b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_2(sc, R92C_CR, 0,
145b3f3786eSAndriy Voskoboinyk 	    R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
146b3f3786eSAndriy Voskoboinyk 	    R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
147b3f3786eSAndriy Voskoboinyk 	    R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
148b3f3786eSAndriy Voskoboinyk 	    ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
149b3f3786eSAndriy Voskoboinyk 	    R92C_CR_CALTMR_EN);
150b3f3786eSAndriy Voskoboinyk 
151b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R92C_INT_MIG, 0);
152b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R92C_MCUTST_1, 0);
153b3f3786eSAndriy Voskoboinyk 
154b3f3786eSAndriy Voskoboinyk 	return (0);
155b3f3786eSAndriy Voskoboinyk }
156b3f3786eSAndriy Voskoboinyk 
157b3f3786eSAndriy Voskoboinyk void
r88ee_power_off(struct rtwn_softc * sc)158b3f3786eSAndriy Voskoboinyk r88ee_power_off(struct rtwn_softc *sc)
159b3f3786eSAndriy Voskoboinyk {
160b3f3786eSAndriy Voskoboinyk 	uint8_t reg;
161b3f3786eSAndriy Voskoboinyk 	int ntries;
162b3f3786eSAndriy Voskoboinyk 
163b3f3786eSAndriy Voskoboinyk 	/* Disable any kind of TX reports. */
164b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
165b3f3786eSAndriy Voskoboinyk 	    R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
166b3f3786eSAndriy Voskoboinyk 
167b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0xFF);
168b3f3786eSAndriy Voskoboinyk 
169b3f3786eSAndriy Voskoboinyk 	/* Move card to Low Power State. */
170b3f3786eSAndriy Voskoboinyk 	/* Block all Tx queues. */
171b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
172b3f3786eSAndriy Voskoboinyk 
173b3f3786eSAndriy Voskoboinyk 	for (ntries = 0; ntries < 10; ntries++) {
174b3f3786eSAndriy Voskoboinyk 		/* Should be zero if no packet is transmitting. */
175b3f3786eSAndriy Voskoboinyk 		if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
176b3f3786eSAndriy Voskoboinyk 			break;
177b3f3786eSAndriy Voskoboinyk 
178b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 5000);
179b3f3786eSAndriy Voskoboinyk 	}
180b3f3786eSAndriy Voskoboinyk 	if (ntries == 10) {
181b3f3786eSAndriy Voskoboinyk 		device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
182b3f3786eSAndriy Voskoboinyk 		    __func__);
183b3f3786eSAndriy Voskoboinyk 		return;
184b3f3786eSAndriy Voskoboinyk 	}
185b3f3786eSAndriy Voskoboinyk 
186b3f3786eSAndriy Voskoboinyk 	/* CCK and OFDM are disabled, and clock are gated. */
187b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
188b3f3786eSAndriy Voskoboinyk 
189b3f3786eSAndriy Voskoboinyk 	rtwn_delay(sc, 1);
190b3f3786eSAndriy Voskoboinyk 
191b3f3786eSAndriy Voskoboinyk 	/* Reset MAC TRX */
192b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_CR,
193b3f3786eSAndriy Voskoboinyk 	    R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
194b3f3786eSAndriy Voskoboinyk 	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
195b3f3786eSAndriy Voskoboinyk 	    R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
196b3f3786eSAndriy Voskoboinyk 
197b3f3786eSAndriy Voskoboinyk 	/* Disable h/w encryption. */
198b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
199b3f3786eSAndriy Voskoboinyk 
200b3f3786eSAndriy Voskoboinyk 	/* Respond TxOK to scheduler */
201b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
202b3f3786eSAndriy Voskoboinyk 
203b3f3786eSAndriy Voskoboinyk 	/* If firmware in ram code, do reset. */
204b3f3786eSAndriy Voskoboinyk #ifndef RTWN_WITHOUT_UCODE
205b3f3786eSAndriy Voskoboinyk 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
206b3f3786eSAndriy Voskoboinyk 		r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
207b3f3786eSAndriy Voskoboinyk #endif
208b3f3786eSAndriy Voskoboinyk 
209b3f3786eSAndriy Voskoboinyk 	/* Reset MCU ready status. */
210b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_MCUFWDL, 0);
211b3f3786eSAndriy Voskoboinyk 
212b3f3786eSAndriy Voskoboinyk 	/* Disable 32k. */
213b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
214b3f3786eSAndriy Voskoboinyk 
215b3f3786eSAndriy Voskoboinyk 	/* Move card to Disabled state. */
216b3f3786eSAndriy Voskoboinyk 	/* Turn off RF. */
217b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RF_CTRL, 0);
218b3f3786eSAndriy Voskoboinyk 
219b3f3786eSAndriy Voskoboinyk 	/* LDO Sleep mode. */
220b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
221b3f3786eSAndriy Voskoboinyk 
222b3f3786eSAndriy Voskoboinyk 	/* Turn off MAC by HW state machine */
223b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
224b3f3786eSAndriy Voskoboinyk 	    R92C_APS_FSMCO_APFM_OFF, 1);
225b3f3786eSAndriy Voskoboinyk 
226b3f3786eSAndriy Voskoboinyk 	for (ntries = 0; ntries < 10; ntries++) {
227b3f3786eSAndriy Voskoboinyk 		/* Wait until it will be disabled. */
228b3f3786eSAndriy Voskoboinyk 		if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
229b3f3786eSAndriy Voskoboinyk 		    R92C_APS_FSMCO_APFM_OFF) == 0)
230b3f3786eSAndriy Voskoboinyk 			break;
231b3f3786eSAndriy Voskoboinyk 
232b3f3786eSAndriy Voskoboinyk 		rtwn_delay(sc, 5000);
233b3f3786eSAndriy Voskoboinyk 	}
234b3f3786eSAndriy Voskoboinyk 	if (ntries == 10) {
235b3f3786eSAndriy Voskoboinyk 		device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
236b3f3786eSAndriy Voskoboinyk 		    __func__);
237b3f3786eSAndriy Voskoboinyk 		return;
238b3f3786eSAndriy Voskoboinyk 	}
239b3f3786eSAndriy Voskoboinyk 
240b3f3786eSAndriy Voskoboinyk 	/* schmit trigger */
241b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
242b3f3786eSAndriy Voskoboinyk 
243b3f3786eSAndriy Voskoboinyk 	/* Reset MCU IO Wrapper. */
244b3f3786eSAndriy Voskoboinyk 	reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
245b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
246b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
247b3f3786eSAndriy Voskoboinyk 
248b3f3786eSAndriy Voskoboinyk 	/* marked as 'For Power Consumption' code. */
249b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
250b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
251b3f3786eSAndriy Voskoboinyk 
252b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_GPIO_IO_SEL,
253b3f3786eSAndriy Voskoboinyk 	    rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
254b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
255b3f3786eSAndriy Voskoboinyk 
256b3f3786eSAndriy Voskoboinyk 	/* Set LNA, TRSW, EX_PA Pin to output mode. */
257b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
258b3f3786eSAndriy Voskoboinyk }
259b3f3786eSAndriy Voskoboinyk 
260b3f3786eSAndriy Voskoboinyk void
r88ee_post_init(struct rtwn_softc * sc)261b3f3786eSAndriy Voskoboinyk r88ee_post_init(struct rtwn_softc *sc)
262b3f3786eSAndriy Voskoboinyk {
263b3f3786eSAndriy Voskoboinyk 
264b3f3786eSAndriy Voskoboinyk 	/* Enable per-packet TX report. */
265b3f3786eSAndriy Voskoboinyk 	rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
266b3f3786eSAndriy Voskoboinyk 
267b3f3786eSAndriy Voskoboinyk 	/* Disable Tx if MACID is not associated. */
268b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
269b3f3786eSAndriy Voskoboinyk 	rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
270b3f3786eSAndriy Voskoboinyk 	r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
271b3f3786eSAndriy Voskoboinyk 
272b3f3786eSAndriy Voskoboinyk 	/* Perform LO and IQ calibrations. */
273b3f3786eSAndriy Voskoboinyk 	r88e_iq_calib(sc);
274b3f3786eSAndriy Voskoboinyk 	/* Perform LC calibration. */
275b3f3786eSAndriy Voskoboinyk 	r92c_lc_calib(sc);
276b3f3786eSAndriy Voskoboinyk 
277b3f3786eSAndriy Voskoboinyk 	/* Enable Rx DMA */
278b3f3786eSAndriy Voskoboinyk 	rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0);
279b3f3786eSAndriy Voskoboinyk 
280b3f3786eSAndriy Voskoboinyk 	if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
281b3f3786eSAndriy Voskoboinyk 		/* No support (yet?) for f/w rate adaptation. */
282b3f3786eSAndriy Voskoboinyk 		sc->sc_ratectl = RTWN_RATECTL_NET80211;
283b3f3786eSAndriy Voskoboinyk 	} else
284b3f3786eSAndriy Voskoboinyk 		sc->sc_ratectl = sc->sc_ratectl_sysctl;
285b3f3786eSAndriy Voskoboinyk }
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